Monday, June 4
6:00 p.m. to 8:30 p.m.
San Francisco Marriott Marquis, Golden Gate Ballroom A
At this event, you will hear Synopsys' R&D team unveil the new underlying engines, and industry experts will share their experience on this innovative new technology resulting in up to 10X faster and smaller full-chip timing analysis runs, with the same signoff quality results compared to flat analysis.
Who should attend?
Design engineers and managers interested in static timing analysis.
Attendance at this event is free, but registration is required. Seating is limited, so reserve your seat today.