Best of DAC 2011: Standards Videos 

IEEE-ISTO—Standards Through Collaboration

IEEE-ISTO
MIPI Alliance: Pushing the Boundaries of Mobile Interface Technology


IEEE 1800—SystemVerilog

AMIQ EDA
The DVT IDE for Efficient SystemVerilog Code Development
   
Doulos
VMM and UVM Training from Doulos
   
eInfochips
VMM / UVM Enabled Verification
   
Paradigm Works
VerificationWorks™ - Creating and Maintaining Reusable Verification Environments Using Industry Proven Best Practices
   
SpringSoft
Verdi & SystemVerilog
   
Vennsa Technologies
Vennsa OnPoint™ - Beyond Debug

IEEE 1666—OSCI SystemC TLM-2.0

ARM
Chasing the Envelope – SystemC TLM for Design Exploration of ARM AMBA Protocol-based Systems
   
Arteris
NoC Interconnect Architecture Exploration and Refinement Using SystemC
   
DOCEA Power
ESL Solutions for Low Power Design
   
Doulos
Improving Your SystemC Success with Doulos
   
emsys Embedded Systems GmbH Power
Power Efficient Firmware for DesignWare USB IP Cores
   
Embedded Systems Technology (EST)
Active Safety Interacting Cyber-Physical Systems
   
EVE
EVE ZeBu System-Level Interoperability with TLM
   
JEDA Technologies, Inc.
Achieve Confidence in ESL Model Quality – Working with Platform Architect
   
MCCI
Software/Hardware Integration with Synopsys USB IP
   
Semifore
Register Management for Virtual Prototyping

IPL Alliance—OpenAccess Custom Design

IPL Alliance Luncheon: Interoperable PDKs are Here to Stay: New Era of Analog/Custom Innovations
At the fifth annual IPL Luncheon, the IPL Alliance presented an update on the current and future success of IPL standards.
Hear about:
  • How the industry is embracing the IPL 1.0 standard
  • Specs of the new interoperable design constraint standard
  • Collaboration among standards: How oPDK and iPDK will work together
   
Interoperability Breakfast:
On Safari with Custom Design Interoperability & Interconnect Modeling Standards

Hear the latest on the industry's collaborative efforts benefiting advances custom design. See how the interconnect technology format is fostering greater efficiency in advanced node modeling and design.