Best of DAC 2011: Implementation Videos 

RTL Synthesis

DC Explorer: Accelerate Design Schedules with Early RTL Exploration
DC Explorer, the latest product in the Design Compiler family, enables you to develop high-quality RTL and constraints faster and create a better starting point for RTL synthesis. See how DC Explorer can accelerate your design schedules through early RTL exploration that drives a faster, more convergent design flow.

Physical Implementation

IC Compiler Lunch Panel: Realizing Gigascale Designs with IC Compiler
Hear from your peers at Intel, Lantiq, LSI Logic, Panasonic, and Renesas who have successfully taped out multimillion-instance, gigascale designs with IC Compiler.
What is behind this success?
  • Faster runtimes
  • Exploration and feasibility
  • On-demand loading
  • All of the above and more

Custom Implementation

Custom Designer: Advances in Custom Design Layout Productivity
Learn about Custom Designer Layout Editor (LE), Schematic-driven Layout (SDL) and integration with physical verification (StarRC, IC Validator) and reliability analysis (CustomSim). We give special emphasis to advanced productivity features such as interactive routing and SmartDRD for automatically fixing DRC violations.
IPL Alliance Luncheon: Interoperable PDKs are Here to Stay: New Era of Analog/Custom Innovations
At the fifth annual IPL Luncheon, the IPL Alliance presented an update on the current and future success of IPL standards.
Hear about:
  • How the industry is embracing the IPL 1.0 standard
  • Specs of the new interoperable design constraint standard
  • Collaboration among standards: How oPDK and iPDK will work together
Interoperability Breakfast: On Safari with Custom Design Interoperability & Interconnect Modeling Standards
Hear the latest on the industry's collaborative efforts benefiting advanced custom design. See how the interconnect technology format is fostering greater efficiency in advanced node modeling and design.


PrimeTime: The Only STA Solution for Gigascale Design
Learn about the latest innovations in PrimeTime that enable the fastest timing signoff closure for today's large, complex designs. PrimeTime's HyperScale approach enables up to a 10X runtime speed-up without sacrificing accuracy, and new hierarchical and incremental ECO guidance technology is optimized for IC Compiler.
PrimeTime SIG Panel: Next-Generation ECO Guidance Technology
At this event, Synopsys unveiled its next-generation PrimeTime ECO guidance technology. Synopsys' R&D team discuss the new underlying engines resulting in up to 10X faster and better QoR with fewer ECO changes. Industry timing experts from Broadcom Corporation, Cisco Systems, LSI Corporation, and STMicroelectronics shared their experiences with this new technology by highlighting benefits in improved QoR, turnaround time, and designer productivity.
StarRC: Fastest Extraction with No-compromise 28-nm Accuracy
Learn about the latest innovations in StarRC that enable the fastest extraction with no compromise on accuracy. StarRC's high-performance multicore architecture delivers a significant boost in performance, new incremental and hierarchical links to PrimeTime enable faster ECO, and advanced 28/20nm modeling provides unmatched accuracy.
In-Design Rail Analysis: Accelerate Power Network Design
See how In-Design Rail Analysis links with IC Compiler and CustomSim improve designer productivity. The latest link minimizes late-stage design changes to accelerate power network design closure for physical designers.
NanoTime: Static Timing Analysis and CCS Model Generation for Custom Digital Blocks
Learn how to use NanoTime from the Custom Designer environment to perform transistor-level static timing SI analysis, debug timing issues, and generate CCS timing and noise models of custom digital blocks. See how those models are then used as part of a hierarchical full-chip analysis with PrimeTime.

Physical Verification

IC Validator: In-Design Physical Verification with Smart Error Management for Faster Design Closure
Learn how new capabilities, such as automated mapping of violations to design properties and intelligent filtering per design stage, can eliminate excessive design iterations and save weeks in turnaround time—all within IC Compiler. In-Design physical verification with IC Validator now features Smart Error Management, making it even easier for physical designers to check designs at critical stages during implementation.

Lynx Design System

Lynx Design System: Accelerating Time-to-Results for ARC 600 Core
See how to use the Lynx Design System to configure and implement a 40-nm low power ARC 600 core from RTL-to-GDSII using the Synopsys standard cell libraries, memory compilers and Galaxy Implementation Platform. The Lynx flow and its advanced visualization capabilities enables you to accelerate TTR with proven predictable methodologies for optimal performance, power, and area.

NewsArticlesBlogsSuccess StoriesWhite PapersWebinarsVideos