Video Library 

WHAT'S NEXT


Why buy IP from an IP supplier with lots of customers?
Does proven IP have more value?
Eric Huang, Product Manager, Synopsys and Theo Goguely, Product Manager, DisplayLink
Synopsys Demonstrates DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair
This demonstration will feature the post-silicon interactive automation capabilities of the DesignWare STAR Silicon Browser, which utilizes the DesignWare STAR Memory System's embedded test & repair IP solution.
Yervant Zorian, Chief Architect, Synopsys, Gevorg Torjyan, R&D Engineer, Synopsys
Synopsys Demonstrates MIPI Camera and Display Prototyping System
Synopsys demonstrates proven system-level interoperability utilizing Synopsys' DesignWare MIPI CSI-2 and DSI host controller as well as the DesignWare MIPI D-PHY IP solution
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP; Miguel Falcao Sousa, R&D Manager, Solutions Group
MCCI USB 3.0 Software on Synopsys' HAPS with DesignWare SuperSpeed USB 3.0 Cores & PHYs
This demonstration will showcase Synopsys' HAPS platform with a DesignWare SuperSpeed USB 3.0 core and PHY running MCCI's USB 3.0 software stack. Designers will learn how they can start their design process for mobile phone and multimedia portable USB products with working drivers.
Eric Huang, Product Marketing Manager, USB Digital Cores; Terry Moore, CEO, MCCI
Meet the Prototypers - Introducing the FPMM
Meet the Prototypers: Introducing the FPMM was a panel discussion held at the 2011 DVCon show in San Jose, March 2, at the DoubleTree Hotel.
Phil Dworsky, Synopsys; Kevin Morris, Synopsys
IC Validator
Antun Domic, Senior VP and GM, Implementation Group, Synopsys, Inc.
DisplayLink Demonstrates Video Streaming with Synopsys’ DesignWare® SuperSpeed USB 3.0 and HDMI IP
Learn how DisplayLink uses Synopsys DesignWare SuperSpeed USB 3.0 and HDMI IP to create their next-generation USB graphics technology.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP; Jason Slaughter, Director of Marketing, DisplayLink
DisplayLink Explains Video Compression Over USB 3.0
Discover how DisplayLink leverages adaptive compression over USB 3.0 to create a smooth, full screen video and graphic experience with low latency.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP; Jason Slaughter, Director of Marketing, DisplayLink
Implementing a Audio Video Bridge with DesignWare Ethernet QoS
With the release of the IEEE 802.1 specifications for Audio Video Bridging (AVB) designers can now include this functionality in their designs with the DesignWare® Ethernet QOS core. This demonstration will show how a Ethernet design can easily be configured to support AVB capable networks.
John Swanson, Senior Manager, Synopsys
Mini Demo: SmartDRD Technology
SmartDRD is a new, innovative technology built into Galaxy Custom Designer LE for interactive DRC violation visualization, detection and correction. This mini demo shows how the DRDAutoFix feature automatically detects and corrects DRC violations in a fraction of a second.
Demo
Mini Demo: High-performance Bus Editing with Bridge and Tunnel
Bus, Bridge and Tunnel are innovative technologies built into Galaxy Custom Designer LE for higher productivity in high-performance interactive bus routing and editing. This mini demo illustrates interactive bus routing with user-selectable cornering options and automatic via insertion working with and without connectivity. The Bridge and Tunnel command allows quick layer changes in regions of a routed bus or net with automatic via insertion.
Demo
Mini Demo: SDL Migrate Featuring the SDL Import Command
Custom Designer's SDL Import command aids designers challenged with developing new design derivatives from existing SDL IP that requires targeting new PDKs and new schematics with the same circuit topology. This mini demo shows how easy it is to regenerate the design (placement and wiring) from an existing design while maintaining the device/P-cell placement locations and target a new PDK. The newly characterized schematic sizes are referenced in the newly-generated layout.
Demo
Mini Demo: Advances in Schematic Capture Featuring the Custom Designer Schematic Editor
Custom Designer SE’s schematic entry system enables designers to be more productive in meeting the design challenges of today’s complex circuits. This mini demo shows how, with little or no learning curve, all Custom Designer’s schematic editing tasks are accomplished with fewer clicks, quicker menu access and less pop-up menu clutter, thereby maximizing productivity.
Demo
Mini Demo: Advanced SDL Cloning
Custom Designer’s SDL Auto Cloning feature provides designers with an intuitive schematic-to-layout cloning solution with high capacity and performance. This capability will clone both exact and inexact schematic device sizes. The innovative SDL cloning technology enables designers to layout repetitive circuitry much faster while maintaining full SDL compliance.
Demo
Mini Demo: SDL Interdigitation
SDL interdigitation is an intuitive, simple approach to interdigitate devices for matching purposes while maintaining device-to-device connectivity from the schematic. The placement is row-based, and ABBA, AABB and ABAB patterns are supported. Dummy device insertion and cross-coupling of patterns are also supported.
Demo
Mini Demo: Layout Commands - Part One
SmartDRD DRDAssist enables layout designers to perform DRC-correct layout tasks at zoomed-out “high altitude", greatly reducing the number of zooming-in and zooming-out iterations. DRDAssist ensures DRC correctness by keeping objects separated at the minimum design rule distance, in real time.
Demo
Mini Demo: Layout Commands – Part Two
Automated Via Generation helps layout designers accelerate the tedious and repetitive tasks of wire connecting, substrate contact insertion, and power and ground tapping. This mini demo illustrates 5 different modes of operation from Custom Designer’s Auto-Via command.
Demo
Mini Demo: Productive DRC Debugging with IC Validator and Custom Designer
IC Validator's error classification capability provides layout designers and CAD engineers the ability to classify and comment individual DRC error markers according to their root cause. IC Validator runs can read these classified errors into a GUI, allowing users to track the previously-classified violations within the Custom Designer cockpit.
Demo
Mini Demo: Interactive Auto-Router
Custom Designer's Interactive Auto-Router is an innovative feature that improves single-net routing productivity. It comes in two modes of operation: Point-to-Point (P2P) and Follow-the-Cursor (FTC) routing. Both P2P and FTC will follow the preferred layer routing direction while routing nets LVS and DRC correct in real-time.
Demo
CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS co-simulation solution, CustomExplorer Ultra aids engineers in rapidly performing customized advanced analyses for transistor-level analog, mixed-signal and SoC designs.
Demo
Synphony Model Compiler
Quickly create complex multi-rate algorithms that are synthesizable into optimized FPGA or ASIC implementations.
Demo
Introducing Galaxy Test 2010.12
Mona Marmash introduces the latest releases and new capabilities of DFTMAX compression and TetraMAX ATPG.
Mona, Marmash, Sr. Staff Support Center Engineer, Synopsys
Synphony C Compiler
Overview of how to synthesize complex C/C++ algorithms into optimized RTL implementations.
Demo
Faster Design Closure with PrimeTime AOCV
PrimeTime Advanced OCV, is a mature and proven technology in Static Timing Analysis to address the variation challenges in designs at 65nm or below process nodes.
Feroze Taraporevala, senior R&D manager, Implementation Group, Synopsys
PrimeTime Scales Timing Analysis Beyond 500 Million Instances
PrimeTime HyperScale technology extends PrimeTime static timing analysis to support designs beyond 500 million instances. It delivers between 5 and 10X better runtimes for the full chip timing analysis and 5 to 10X smaller memory footprint compared with classic flat analysis.
Antun Domic, senior vice president and general manager, Implementation Group, Synopsys
In-Design physical verification with IC Validator and IC Compiler delivers 100 tapeouts just one year after introduction.
In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.
Aart de Geus, Synopsys Chairman and CEO
DC Explorer Demo
Early RTL exploration accelerates synthesis and place & route
Demo
Lynx Design System Readiness for 28nm
Andy Potemski, Director, Global Technical Services, Synopsys, presents at the Common Platform Technology Forum.
Andy Potemski, Director, Global Technical Services, Synopsys
S2S Verification Overview Video
High-level overview of the Systems to Silicon Solution with David Park
David Park, Solutions Manager, Synopsys
S2S Verification Video
Interview with Rajiv Maheshwary and Janick Bergeron
Janick Bergeron, Scientist, Synopsys, Inc.; Rajiv Maheshwary, Senior director, Synopsys, Inc.
Customer Highlight
ST meets AMS simulation criteria with VCS-MX and CustomSim
Yuval Shay, Staff Engineer, Mixed-Signal Verificatin
Migrating a USB 2.0 design to USB 3.0 using Synopsys’ DesignWare SuperSpeed USB 3.0 IP and MCCI’s solution
In this video, you will discover how to quickly migrate an existing USB 2.0 design to USB 3.0. By leveraging Synopsys’ silicon-proven, complete DesignWare SuperSpeed USB 3.0 IP solution with MCCI’s software stack, you can lower integration risk and improve time-to-market of your next-generation USB 3.0 design.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI
DC Explorer Video
Introducing DC Explorer
Antun Domic, General Manager, Implementation Group, Synopsys, Inc.
DesignWare SuperSpeed USB 3.0 IP on a Synopsys HAPS-51 platform
In this video, you will see how the Synopsys DesignWare® SuperSpeed USB 3.0 controller and PHY IP enable faster performance speeds, reaching up to 335 MB/s. Using MCCI’s USB 3.0 software stack on a Synopsys HAPS platform, the DesignWare SuperSpeed USB 3.0 IP solution offers USB 3.0 speeds in both 2.0 and 3.0 modes.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP
An Introduction to the FPMM
The FPMM represents not only a collaborative work between Xilinx and Synopsys, but also decades of best-practices in prototyping, drawing upon the expertise of teams in leading semiconductor and application companies around the world. This video features two of the three authors of the FPMM: Doug Amos, Business Development Manager, Solutions Marketing, Synopsys, and Austin Lesea, Principal Engineer, Xilinx. Together, they share their insights on the history and impetus behind the development of the FPMM, and the benefits of prototyping.
Doug Amos, Business Development Manager, Solutions Marketing, Synopsys; Austin Lesea, Principal Engineer, Xilinx.
Synopsys Demonstrates the Industry's First Silicon-Proven MIPI M-PHY
This video demonstrates the fully characterized, silicon-proven capabilities of the DesignWare MIPI M-PHY IP solution, highlighting its silicon performance as well as its electrical characteristics, which exceed target specifications.
Celio Albuquerque, R&D Manager, DesignWare MIPI PHY IP
Modern Verification Challenges
In this short but insightful interview, Warren Stapleton, Senior Fellow at AMD, discusses the unique challenges of modern day verification, including the growing complexity of today’s microprocessors designs and what this means for verification engineers.
Warren Stapleton, Senior Fellow, AMD; Michael Sanie, Director of Marketing, Verification Group, Synopsys
SNUG Preview Demo
Synopsys
Understanding MIPI
This video provides a high level view of popular MIPI protocols and helps you get up to speed with latest mobile market innovations. We will also introduce IP solutions that can help you differentiate your products in the mobile market space.
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP
Statistical Eye Diagram Analysis
This mini demo shows how the HSPICE statistical eye diagram feature can evaluate eye diagrams and bit error rate quickly and accurately. Statistical analysis setup, input syntax and outputs are demonstrated.
Synopsys Inc.
HSPICE Precision Parallel technology
This mini demo shows how HSPICE can improve analog designers’ productivity through superior performance and accuracy and tight integration with Galaxy Custom Designer.
Synopsys Inc.
Synopsys Demonstrates Silicon-Proven Implementation of DesignWare® Audio IP
See how Synopsys’ DesignWare Audio IP delivers superb audio quality, featuring a full set of audio functions needed by most of today’s consumer electronic devices. Synopsys also showcases the true Hi-Fi audio quality delivered by the DesignWare Audio Codec with dynamic range exceeding 96dB, while keeping the power consumption at minimum levels.
João Risques, Product Manager for DesignWare Audio and Video AFE IP, Synopsys
Innovation Optimized! Video
ARM, Common Platform and Synopsys executives share their views on the recent collaboration announcement to deliver a technology enablement solution for the design and manufacture of 32nm mobile devices.
Dr. Aart de Geus, Chairman of the Board and CEO, Synopsys; Michael Cadigan, General Manager, Microelectronics Division, IBM Systems and Technology Group; Dr. C.S. Choi, Executive Vice President, LSI Division, Samsung Electronics; Chia Song Hwee, President and CEO, Chartered Semiconductor Manufacturing ; Warren East, Chief Executive Office, ARM Holdings
Introduction to Synthesis-Based Test
Watch this short video to learn about Synopsys’ Synthesis-Based Test technology and Test product portfolio.
Arif Samad, VP Engineering, Synopsys
Explore R&D Engineering
Explore the life of an R&D engineer at Synopsys. Do you have a passion for software? Do you enjoy solving difficult problems? Find out what it takes to be an R&D Engineer at Synopsys.
Synopsys Inc.
Explore Applications Engineering
Find out what it takes to be an Applications Engineer at Synopsys. If you enjoy working with customer and sharing in their success, this may be a position for you!
Synopsys Inc.
A Look Inside Synopsys
Take a look at what it is like to work at Synopsys, our work culture, values, global reach, employee impact and career opportunities.
Synopsys Inc.
VLSI Research: Synopsys’ new custom IC design suite
Finally . . . an integrated EDA tool for custom IC design. It’s a totally new, ground-up, software package. Yet, its user interface is so similar to what you’ve been using that you’ll be surprised as to how familiar it seems.
Ed Lechner
The Birth of the VMM-LP
In this video you will hear how the VMM-LP came to be and how it addresses the challenges of low power verification.
Srikanth Jadcherla, Group R&D Director in the Verification Group
IC Compiler Customer Successes
In March 2009, SNUG (Synopsys User Group) San Jose drew a large crowd of Synopsys users who gathered to hear from others about their experiences presented in papers, tutorials, and panels. The videos below provide you with a brief overview from customers who presented at San Jose SNUG. Visit the SNUG website for a complete list of IC Compiler papers and presentations. This DAC 2008 event provided an opportunity for members of the electronic design community to learn more about customer design successes with IC Compiler. The event drew a capacity crowd as guest speakers from ARM, Intel, STMicroelectronics, Texas Instruments, and Toshiba shared their experiences from a variety of high-end designs utilizing the latest technology advances in IC Compiler: Concurrent Hierarchical Design, MinChip technology, DFM and IC Compiler’s new Zroute routing technology.
Philip Watson, Implementation Environment Program Manager; Raj Varada, Principal Engineer; Naveen Raina, Technical Specialist & Mutsunori Igarashi, Chief Specialist, Design Methodology Development.
Latest Features of PrimeTime
George Mekhtarian, Product Marketing Manager in Synopsys’ Implementation Group
Power-Aware Test
Conventional compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop and overheating.
Tom Williams, Synopsys Fellow
Eclypse Low Power Solution
Josefina Hobbs introduces the Eclypse Low Power Solution
Joselina Hobbs
Expert Shootout: Parasitic Extraction
Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys
Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys
DesignCon 2010: VCS Named DesignVision Award Finalist
Following the annoucement that VCS was honored as a finalist in the 2010 DesignVision Awards, Swami Venkat, Sr. Director of Verification Marketing at Synopsys, discusses the latest innovations within Synopsys' industry-leading functional verification solution at Designcon 2010.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys
An Introduction to The Lynx Design System
Neel Desai, Product Marketing Manager, provides an overview of this unique and comprehensive chip development platform.
Neel Desai, Product Marketing Manager
VMM User Forum Lunch Event: NVIDIA
Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering
Tips for Getting the Best PrimeTime Performance
Few easy ways for getting the best PrimeTime performance and achieving faster sign-off analysis.
Karen Linser, staff applications engineer in Synopsys’ Implementation Group
Small Delay Defects: The Need for Better At-Speed Tests
Manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures. Dr. T.W. Williams introduces technology developed at Synopsys to detect defects creating these delays, thereby increasing the test quality.
Tom Williams, Synopsys Fellow
IC Compiler Lunch Event: ARM, Ltd.
ARM Cortex-A9 MPCore Multi-core Processor Hierarchical Implementation with IC Compiler Learn how ARM utilized IC Compiler’s concurrent hierarchical design for multi-core implementation, driving better performance as well as better throughput.
Philip Watson, Implementation Environment Program Manager
IC Compiler Lunch Event: Toshiba Corp
Concurrent Hierarchical Design with IC Compiler, Real Life Application on Mobile Multi-Media Processor IC Compiler offers the industry’s first concurrent hierarchical design system that delivers a high degree of automation combined with high-quality optimization. Learn more about the results Toshiba achieved with the latest advances in IC Compiler.
Mutsunori Igarashi, Chief Specialist, Design Methodology Development
Perspective: Boost your design productivity
Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule.
Antun Domic, senior vice president and general manager of Synopsys' Implementation Group
DAC 2010 IC Compiler In-Design Videolog
At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics
In-Design Physical Verification Milestone
In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.
Dr. Aart de Geus, Synopsys Chairman and CEO
Modern-era Custom Design
Tired of using two-generations-old EDA technology for your next-generation mixed-signal IC? Synopsys’ new custom design solution can quickly bring you into the modern era of custom chip design.
Joe Mastroianni, Synopsys VP of AMS R&D,
VMM User Forum Lunch Event: ARM, Ltd.
Need for a Low Power Verification Methodology. Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead
The Unique Challenge of Low Power Verification
With over 30 industry experts contributing to the book, the methodology documented in the VMM-LP is based on real-life design.
Janick Bergeron, Fellow in the Verification Group
Accelerate Product Ramp with TetraMAX ATPG and Yield Explorer
Girish Patankar discusses diagnostics in TetraMAX ATPG, accuracy improvements with physical diagnostics, and how TetraMAX ATPG and Yield Explorer form a complete solution for volume diagnostics.
Girish Patankar, Sr. R&D Manager
Synopsys and LeCroy Showcase PCI Express® 3.0 Interoperability at PCI-SIG 2010
This demonstration features LeCroy’s Summit T3-16 Protocol Analyzer, Summit Z3-16 Protocol Exerciser and the Summit Z3-16 Test Platform to test a PCI Express 3.0-based design for compliance to the PCI Express 3.0 specification. The design-under-test (DUT) utilizes the DesignWare® IP for PCI Express 3.0.
Featuring: John Wiedemeier, Product Manager, LeCroy; Scott Knowlton, Product Marketing Manager, Synopsys
Synopsys and Agilent Enable PCI Express 3.0 Ecosystem at PCI-SIG 2010
Utilizing a DUT that implements the DesignWare IP for PCI Express 3.0, this demonstration features Agilent’s complete test solution for PCI Express 3.0 and the Digital Test Console to check for compliance to the PCI Express 3.0 specification.
Featuring: Yenyi Fu, Product Manager, Agilent; Scott Knowlton, Product Marketing Manager, Synopsys
Optimized Implementation Methodology for High Performance Low Power Processor Cores at 40nm and Below
Both mobile and tethered devices require increased performance with decreased power consumption. In this tutorial, we present how the optimized methodology for processor cores at 40nm and below address these needs. This tutorial describes results using some of the latest DC Topographical and IC Compiler capabilities together with a highly tuned set of user constraints, delivering impressive performance results. Key techniques covered include: shorten wires for higher clock frequency, methodology to minimize congestion and best convergence with high utilization and high cell density, crosstalk prevention and fixing, clock tree synthesis constraints and methodology, leakage optimization, and signoff optimization. Target audience: Experienced physical designers.
Daniel Biset, Corporate Application Engineer - Synopsys, Inc.
DAC 2010: Galaxy Implementation Platform Overview
Steve Smith, Sr. Director of Marketing for the Galaxy Platform provides an overview of the many advancements made in the last year to Synopsys' comprehensive RTL-to-GDSII implementation solution, including a tighter connection between synthesis and place-and-route with physical guidance, new In-Design physical verification, enhanced signoff for large designs, improved multicore capabilities, the Lynx Design System and 28nm readiness.
Synopsys
Lynx Design System @ DAC 2010
Neel talks about the Lynx Design System and recent updates since its introduction last year including recent customer successes. At DAC2010 we announced a new multi-year collaboration with ARM and the Common Platform alliance that optimizes the Lynx Design System and its Galaxy™ Implementation Platform-enabled flow for ARM's advanced physical IP and the ARM Cortex™ A9 MPCore processor.
Neel Desai, Product Marketing Manager
Make it EASY with Synopsys DesignWare DDR HARD PHY IP
By using DDR Hard PHY IP, you achieve: quicker integration, easier timing closure, better performance and less silicon area. With a hard PHY, all the IP is supplied by one IP vendor and includes I/Os. Hard PHYs have lower jitter, better duty cycle, an overall superior clock strategy and use identical circuits for every bit of the parallel DDR interface reducing skew. In addition, hard PHYs implemented in test chips are equivalent to the customer's PHY where as soft PHYs are different GDSII every time.
Synopsys Super Stars
DesignWare SuperSpeed USB 3.0 xHCI demo
See high-definition video using the DesignWare® SuperSpeed USB 3.0 xHCI Host and Device Controller implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video streaming from a standard PC running on a Linux operating system with a SuperSpeed USB 3.0 xHCI Host Stack, into mass storage device.
Eric Huang, Product Marketing Manager, USB Digital
Design Compiler 2010 Video
Antun Domic, General Manager, Implementation Group, Synopsys, Inc
Galaxy Test 2010.03 Introduction
Amy Mitby introduces the latest release and highlights four new powerful features
Amy Mitby, Sr. Test Applications Consultant
Synopsys Demonstrates SuperSpeed USB 3.0 Interoperability
This demonstration shows proven interoperability of Synopsys' DesignWare USB 3.0 PHY with the DesignWare USB 3.0 host and device controllers implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Gervais Fong Product Marketing Manager, USB PHY IP
DesignWare DDR3/2 IP Demo at 1600 Mbps
Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Graham Allan, Product Marketing Manager, Memory Interface IP; Vishal Thareja, Test Engineer
Automotive
Join our FREE Robust Design Webcast Series to discover how Robust Design methodologies coupled with Synopsys Saber simulation and analysis solution can improve your design performance and reliability for Mechatronic Systems.
Mike Jensen, Coporate Applications Engineer, Saber product line, Synopsys Inc.
DisplayLink Streams Uncompressed HD 1080p Video Using Synopsys’ USB 3.0 IP
DisplayLink demonstrates how it uses DesignWare SuperSpeed USB 3.0 and HDMI IP to show full HD resolution over USB 3.0 by taking video directly out of USB 3.0 on the PC, convert it to HDMI and display it directly to a high-resolution monitor.
Gervais Fong, Product Marketing Manager, USB PHY IP Dennis Crespo, Vice President of Marketing, DisplayLink
Silicon-proven DesignWare® HDMI TX Controller and PHY IP on Synopsys’ HAPS-51 Platform
Synopsys shows how fixed video and audio patterns are transmitted by the DesignWare HDMI TX controller and PHY. See the image quality improve as resolution of video test pattern is increased from 480p to 720p to 1080p, 60 Hz frame formats. Also see the EDID info collected by TX Controller/PHY Display Data Channel (DDC) from the sink device (DTV) to support negotiation and find the best supported color format and frame rate.
Manmeet Walia, Product Manager for Mixed-Signal PHY IP, Synopsys
Pin-Limited Test
Current trends are accelerating the need for pin-limited test. Amy Mitby introduces capabilities in DFTMAX compression that allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins.
Amy Mitby, Sr. Test Applications Consultant
Synopsys and MCCI SuperSpeed Media Player Demonstration
See Synopsys and MCCI demonstrate how music can be synchronized in a matter of seconds in a USB 3.0 media player compared to minutes in a USB 2.0 media player. The demonstration consists of the Synopsys DesignWare® SuperSpeed USB Digital Controller and MCCI SuperSpeed USB Software on an FPGA hardware platform.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI
TI Demonstrates USB 3.0 Interoperability at IDF with DesignWare IP
TI demonstrates SuperSpeed USB interoperability and USB 2.0 backward compatibility. The demo showcases TI's TUSB80x0 Hub and TUSB9260 SATA bridge controller with the Synopsys DesignWare SuperSpeed USB 3.0 IP
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI
DesignWare IP for PCI Express 2.0 Complete Solution Demo
See a live demonstration of the 45-nm DesignWare PHY and controller IP for PCI Express® 2.0 operating in a single-lane configuration at 5 GT/s. The demonstration verifies 5 GT/s operation using the PCI® Tree software and executes Reads and Writes between the demo hardware and a PC to show throughput performance levels.
Scott Knowlton, Sr. Produt Marketing Manager, Synopsys
See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device
See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device digital controllers in a single demonstration. In this video, Synopsys shows interoperability between the DesignWare SuperSpeed USB 3.0 controllers and a USB 3.0 mass storage device, USB 2.0 flash controller and USB 1.1 mouse.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP
See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution
See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution, consisting of digital controllers, mixed-signal PHY and Verification IP. This video consists of hardware demonstrations for the DesignWare SATA AHCI Host, Device, PHY and 6 Gb/s IP solutions.
Mat Loikkanen Sr. R&D Engineer, Synopsys; Mick Posner Sr. Product Marketing Manager, Synopsys
IC Compiler In-Design Technology
At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics
PrimeTime SIG 2009
In July 2009, Synopsys hosted two PrimeTime SIG events in Bangalore, India and San Francisco, CA focused on STA performance and productivity, as well as new timing constraints management technology. Hear what experts from leading companies had to say about taking advantage of the latest PrimeTime features to boost productivity.
T.W. Williams, Synopsys Fellow; Jagan Ayyaswami, Principal Manager, Physical Design Group, Qualcomm; Rajagopal K.A., Technologist, Texas Instruments; Rich Laubhan, Manager of Design Integrity, LSI Corp.; Michio Komoda, Sr. Engineer, DFM & Digital EDA Technology Development, Renesas Corp.
How Does the VMM-LP Benefit the Industry?
Hear about some of the potential problems of low power verification and how the VMM-LP helps overcome them.
David Flynn, Fellow at ARM
See Synopsys and Texas Instruments demonstrate SuperSpeed USB 3.0 Interoperability
Join us in the Synopsys lab to see proven interoperability between the Texas Instrument’s USB 3.0 transceiver and the Synopsys DesignWare USB 3.0 host and device controller implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI
See Global Unichip’s SSD Demo Featuring DesignWare® SATA IP
See how Global Unichip (GUC) utilized Synopsys' silicon-proven DesignWare® SATA IP in its Solid State Device (SSD) GP5080 platform to demonstrate a netbook boot-up time of less than half a minute. The hardware platform consists of a high-performance 32-bit ARM7 processor, SATA 3Gb/s interface, SLC/MLC NAND Flash management of up to 4 channels, 8 banks with ECC.
Kurt Huang, Director of Marketing, Global Unichip Corp.
See an actual USB 3.0 data transfer utilizing the DesignWare SuperSpeed USB Host and Device Controllers implemented in an FPGA
Join Synopsys in our lab to see actual USB 3.0 data transfer utilizing the DesignWare Superspeed USB Host and Device Controllers implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video, streaming from the device into the host with a measured throughput of 460 MB/s utilizing the Lecroy CATC analyzer.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP
SNUG San Jose Keynote
Aart de Geus, Synopsys CEO, delivers the opening keynote address at SNUG San Jose 2008.
Aart de Geus, Synopsys CEO
Mike Keating: The Future of Low Power 2008
Mike Keating, Synopsys Fellow, presents a 2008 update to last year's popular SNUG presentation. This talk consists of a leisurely walk through the power management spectrum, with digressions into various interesting side-issues.
Mike Keating
Perspective: How to Improve Design TTR
John Chilton, senior vice president of Marketing and Business Development at Synopsys, talks about the importance of utilizing today’s widely-available multi-core processor-based compute infrastructures to accelerate design TTR.
John Chilton, senior vice president of Marketing and Business Development at Synopsys
10X Faster Routing Runtime
Combine advanced routing algorithms with multi-threading technology, and you get a speed increase of >10X on quad-core machines.
Tong Gao, Synopsys Scientist and architect of Zroute,
VMM User Forum Lunch Event: IBM
"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead
VMM User Forum Lunch Event: Renesas Technology Corporation
Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer
IC Compiler Lunch Event: Intel Corp.
IC Compiler: Routing and Design for Manufacturability (DFM) IC Compiler uses concurrent optimization techniques to simultaneously consider the impact of manufacturing rules, timing, and other design goals for high QoR and improved manufacturability.
Raj Varada, Principal Engineer
IC Compiler Lunch Event: STMicroelectronics
Automatic Block Size Reduction with IC Compiler MinChip Technology IC Compiler reduces runtime and memory while delivering hand-craft-quality macro placement, MinChip die size reduction, clock tree synthesis, skew optimization, clock-gate merging, and more. STMicroelectronics achieved a huge reduction in die-size with a runtime of only 4 to 6 hours!
Naveen Raina, Technical Specialist
Perspective: SDD Test to the Rescue
Carl Holzwarth, director of Test R&D
See how we verify the DesignWare IP for DDR2/3 PHY and Controllers
See firsthand the test equipment and custom boards developed and used by Synopsys to verify our DDR IP. Witness full speed write and read data eyes, at speed functionality testing, duty cycle and phase error tests and jitter analysis results.
Graham Allan, Product Marketing Manager, DDR IP
Godwin Maben: Low Power Trends and Methodology
Godwin Maben
Join us in the Synopsys lab to see how we verify the DesignWare USB 2.0 NanoPHY IP
The video will take you through our silicon verification board set up, show the unique tunability feature and highlight the extensive characterization process of the USB 2.0 nanoPHY.
Gervais Fong, Product Marketing Manager, USB PHY IP
See a silicon demo of the DesignWare PHY for PCI Express 2.0
Join Synopsys in our lab to see how we deliver a compliant, robust PCI Express 2.0 PHY and enable visibility into the link performance through unique on-chip diagnostics.
Navraj Nandra, Marketing Director MSIP
Unifying or Overrated: A System Level Design Strategy
Joachim Kunkel, VP and GM of the Synopsys Solutions Group discusses trends and best practices regarding the development of a system-level design strategy.
Joachim Kunkel
SNUG Boston 2008: Galaxy Custom Designer Launch
On September 22 at SNUG Boston 2008, Synopsys unveiled Galaxy Custom Designer™, the modern-era custom AMS implementation solution. On hand to support the launch were representatives from Cray and Priva Technologies who presented their experiences using/supporting Custom Designer.
Aart de Geus, CEO, Synopsys, Inc.; Tom Quan, Design Methodology & Service Marketing; Matt Priest, Hardware Engineer; Jeff Berkman, CTO
FPGA prototyping gains ground
At the Design Automation Conference (DAC) in Anaheim, Calif., Mark LaPedus, semiconductor editor from EE Times, caught up with Andy Haines, vice president of marketing of Synplicity, which was recently acquired by Synopsys. In a video, Smith, Haines discusses the growing importance of FPGA prototyping.
Mark LaPedus and Andy Haines
Design and Verification of Ultra Low Power SoCs with ARM Cores
This presentation describes the common challenges and solutions in the design and verification of SoCs striving for power and performance efficiency. In particular, we discuss how ARM's IEM technology can control power and performance, focusing on the integration of ARM cores, IEM technology, and the process of architecting and verifying a low power scheme using these components. We also provide guidance in the hardware and software partitioning of low power schemes.
Srikanth Jadcherla, Group Director of R&D, Synopsys -- Prapanna Tiwari, Manager, Corporate Applications Engineer, Synopsys
Why buy IP from an IP supplier with lots of customers?
Does proven IP have more value?
Eric Huang, Product Manager, Synopsys and Theo Goguely, Product Manager, DisplayLink

Meet the Prototypers - Introducing the FPMM
Meet the Prototypers: Introducing the FPMM was a panel discussion held at the 2011 DVCon show in San Jose, March 2, at the DoubleTree Hotel.
Phil Dworsky, Synopsys; Kevin Morris, Synopsys
49:53
/Community/PublishingImages/videoimages/images6851/FPMM-meet6851.jpg
http://synopsys1.http.internapcdn.net/synopsys1/intro-fpmm-dvcon2011/main.htm
Synphony Model Compiler
Quickly create complex multi-rate algorithms that are synthesizable into optimized FPGA or ASIC implementations.
Demo
20:09
/Community/PublishingImages/videoimages/images6851/SynphonyModelCompiler.jpg
http://www.synopsys.com/cgi-bin/sld/hlsdemos/reg1.cgi?file=hls-synpho-model-compiler-mar14.html
Synphony C Compiler
Overview of how to synthesize complex C/C++ algorithms into optimized RTL implementations.
Demo
26:05
/Community/PublishingImages/videoimages/images6851/SynphonyCCompiler.jpg
http://www.synopsys.com/cgi-bin/sld/hlsdemos/reg1.cgi?file=hls-synphoc-compiler-mar14.html
An Introduction to the FPMM
The FPMM represents not only a collaborative work between Xilinx and Synopsys, but also decades of best-practices in prototyping, drawing upon the expertise of teams in leading semiconductor and application companies around the world. This video features two of the three authors of the FPMM: Doug Amos, Business Development Manager, Solutions Marketing, Synopsys, and Austin Lesea, Principal Engineer, Xilinx. Together, they share their insights on the history and impetus behind the development of the FPMM, and the benefits of prototyping.
Doug Amos, Business Development Manager, Solutions Marketing, Synopsys; Austin Lesea, Principal Engineer, Xilinx.
09:05
/Community/PublishingImages/videoimages/images6851/fpmm.jpg
none
Modern-era Custom Design
Tired of using two-generations-old EDA technology for your next-generation mixed-signal IC? Synopsys’ new custom design solution can quickly bring you into the modern era of custom chip design.
Joe Mastroianni, Synopsys VP of AMS R&D,
01:46
/Community/PublishingImages/videoimages/images6851/4_videothumbnail.jpg
none
The Unique Challenge of Low Power Verification
With over 30 industry experts contributing to the book, the methodology documented in the VMM-LP is based on real-life design.
Janick Bergeron, Fellow in the Verification Group
02:21
/Community/PublishingImages/videoimages/images6851/2_videothumbnail.jpg
none
Meet the Prototypers - Introducing the FPMM 49:53
Synphony Model Compiler 20:09
Synphony C Compiler 26:05
An Introduction to the FPMM 09:05
Modern-era Custom Design 01:46
The Unique Challenge of Low Power Verification 02:21
Modern Verification Challenges
In this short but insightful interview, Warren Stapleton, Senior Fellow at AMD, discusses the unique challenges of modern day verification, including the growing complexity of today’s microprocessors designs and what this means for verification engineers.
Warren Stapleton, Senior Fellow, AMD; Michael Sanie, Director of Marketing, Verification Group, Synopsys
05:37
/Community/PublishingImages/videoimages/images6851/ModernVerificationChallenges.jpg
none
Statistical Eye Diagram Analysis
This mini demo shows how the HSPICE statistical eye diagram feature can evaluate eye diagrams and bit error rate quickly and accurately. Statistical analysis setup, input syntax and outputs are demonstrated.
Synopsys Inc.
06:53
/Community/PublishingImages/videoimages/images6851/StatisticalEye.jpg
http://www.synopsys.com/cgi-bin/hmd/reg1.cgi?file=hspice-stat-eyediagram-nov13.html
HSPICE Precision Parallel technology
This mini demo shows how HSPICE can improve analog designers’ productivity through superior performance and accuracy and tight integration with Galaxy Custom Designer.
Synopsys Inc.
08:36
/Community/PublishingImages/videoimages/images6851/HSPICEPrecision.jpg
http://www.synopsys.com/cgi-bin/hmd/reg1.cgi?file=hspice-precision-tech-nov13.html
The Birth of the VMM-LP
In this video you will hear how the VMM-LP came to be and how it addresses the challenges of low power verification.
Srikanth Jadcherla, Group R&D Director in the Verification Group
03:30
/Community/PublishingImages/videoimages/images6851/Srikanth.jpg
none
DesignCon 2010: VCS Named DesignVision Award Finalist
Following the annoucement that VCS was honored as a finalist in the 2010 DesignVision Awards, Swami Venkat, Sr. Director of Verification Marketing at Synopsys, discusses the latest innovations within Synopsys' industry-leading functional verification solution at Designcon 2010.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys
04:37
/Community/PublishingImages/videoimages/images6851/DesignCon2010.jpg
http://www10.edacafe.com/video/display_media.php?link_id_display=30345
VMM User Forum Lunch Event: NVIDIA
Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering
04:17
/Community/PublishingImages/videoimages/images6851/dac08vmm_nvidia_soma.jpg
none
VMM User Forum Lunch Event: ARM, Ltd.
Need for a Low Power Verification Methodology. Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead
09:59
/Community/PublishingImages/videoimages/images6851/3_videothumbnail.jpg
none
How Does the VMM-LP Benefit the Industry?
Hear about some of the potential problems of low power verification and how the VMM-LP helps overcome them.
David Flynn, Fellow at ARM
04:01
/Community/PublishingImages/videoimages/images6851/vmm_snps-jun09-david.jpg
none
VMM User Forum Lunch Event: IBM
"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead
12:18
/Community/PublishingImages/videoimages/images6851/dac08vmm_ibm_pratt.jpg
none
VMM User Forum Lunch Event: Renesas Technology Corporation
Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer
09:15
/Community/PublishingImages/videoimages/images6851/dac08vmm_renesas_inoue.jpg
none
Unifying or Overrated: A System Level Design Strategy
Joachim Kunkel, VP and GM of the Synopsys Solutions Group discusses trends and best practices regarding the development of a system-level design strategy.
Joachim Kunkel
05:18
/Community/PublishingImages/videoimages/images6851/Joachim_Kunkel.jpg
http://www.iet.tv/dpx_iet_techelx/dpx.php?dpxuser=dpx_iet_techelx&cmd=autoplay&pres=1156&type=solo
Design and Verification of Ultra Low Power SoCs with ARM Cores
This presentation describes the common challenges and solutions in the design and verification of SoCs striving for power and performance efficiency. In particular, we discuss how ARM's IEM technology can control power and performance, focusing on the integration of ARM cores, IEM technology, and the process of architecting and verifying a low power scheme using these components. We also provide guidance in the hardware and software partitioning of low power schemes.
Srikanth Jadcherla, Group Director of R&D, Synopsys -- Prapanna Tiwari, Manager, Corporate Applications Engineer, Synopsys
50:31
/Community/PublishingImages/videoimages/images6851/DesignVerificationARM_Cores.jpg
none
Modern Verification Challenges 05:37
Statistical Eye Diagram Analysis 06:53
HSPICE Precision Parallel technology 08:36
The Birth of the VMM-LP 03:30
DesignCon 2010: VCS Named DesignVision Award Finalist 04:37
VMM User Forum Lunch Event: NVIDIA 04:17
VMM User Forum Lunch Event: ARM, Ltd. 09:59
How Does the VMM-LP Benefit the Industry? 04:01
VMM User Forum Lunch Event: IBM 12:18
VMM User Forum Lunch Event: Renesas Technology Corporation 09:15
Unifying or Overrated: A System Level Design Strategy 05:18
Design and Verification of Ultra Low Power SoCs with ARM Cores 50:31
IC Validator
Antun Domic, Senior VP and GM, Implementation Group, Synopsys, Inc.
06:47
/Community/PublishingImages/videoimages/images6851/ICValidator_Domic.jpg
none
Mini Demo: SmartDRD Technology
SmartDRD is a new, innovative technology built into Galaxy Custom Designer LE for interactive DRC violation visualization, detection and correction. This mini demo shows how the DRDAutoFix feature automatically detects and corrects DRC violations in a fraction of a second.
Demo
05:33
/Community/PublishingImages/videoimages/images6851/SmartDRD.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo.html
Mini Demo: High-performance Bus Editing with Bridge and Tunnel
Bus, Bridge and Tunnel are innovative technologies built into Galaxy Custom Designer LE for higher productivity in high-performance interactive bus routing and editing. This mini demo illustrates interactive bus routing with user-selectable cornering options and automatic via insertion working with and without connectivity. The Bridge and Tunnel command allows quick layer changes in regions of a routed bus or net with automatic via insertion.
Demo
05:43
/Community/PublishingImages/videoimages/images6851/BusEditing.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-Bus-demo-Jun14.html
Mini Demo: SDL Migrate Featuring the SDL Import Command
Custom Designer's SDL Import command aids designers challenged with developing new design derivatives from existing SDL IP that requires targeting new PDKs and new schematics with the same circuit topology. This mini demo shows how easy it is to regenerate the design (placement and wiring) from an existing design while maintaining the device/P-cell placement locations and target a new PDK. The newly characterized schematic sizes are referenced in the newly-generated layout.
Demo
05:16
/Community/PublishingImages/videoimages/images6851/SDL_Migrate.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-SDLMigrate-July27.html
Mini Demo: Advances in Schematic Capture Featuring the Custom Designer Schematic Editor
Custom Designer SE’s schematic entry system enables designers to be more productive in meeting the design challenges of today’s complex circuits. This mini demo shows how, with little or no learning curve, all Custom Designer’s schematic editing tasks are accomplished with fewer clicks, quicker menu access and less pop-up menu clutter, thereby maximizing productivity.
Demo
09:20
/Community/PublishingImages/videoimages/images6851/SchematicCapture.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-SchematicCap-July29.html
Mini Demo: Advanced SDL Cloning
Custom Designer’s SDL Auto Cloning feature provides designers with an intuitive schematic-to-layout cloning solution with high capacity and performance. This capability will clone both exact and inexact schematic device sizes. The innovative SDL cloning technology enables designers to layout repetitive circuitry much faster while maintaining full SDL compliance.
Demo
05:03
/Community/PublishingImages/videoimages/images6851/SDL_Cloning.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-SDLCloning-Aug23.html
Mini Demo: SDL Interdigitation
SDL interdigitation is an intuitive, simple approach to interdigitate devices for matching purposes while maintaining device-to-device connectivity from the schematic. The placement is row-based, and ABBA, AABB and ABAB patterns are supported. Dummy device insertion and cross-coupling of patterns are also supported.
Demo
06:34
/Community/PublishingImages/videoimages/images6851/SDL_Interdigitation.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-SDL-Interdigitation-Oct27.html
Mini Demo: Layout Commands - Part One
SmartDRD DRDAssist enables layout designers to perform DRC-correct layout tasks at zoomed-out “high altitude", greatly reducing the number of zooming-in and zooming-out iterations. DRDAssist ensures DRC correctness by keeping objects separated at the minimum design rule distance, in real time.
Demo
06:54
/Community/PublishingImages/videoimages/images6851/LayoutCommands_P1.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-LayoutCommand-Nov5.html
Mini Demo: Layout Commands – Part Two
Automated Via Generation helps layout designers accelerate the tedious and repetitive tasks of wire connecting, substrate contact insertion, and power and ground tapping. This mini demo illustrates 5 different modes of operation from Custom Designer’s Auto-Via command.
Demo
04:59
/Community/PublishingImages/videoimages/images6851/LayoutCommands_P2.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-LayoutCommand-part2-Jan27.html
Mini Demo: Productive DRC Debugging with IC Validator and Custom Designer
IC Validator's error classification capability provides layout designers and CAD engineers the ability to classify and comment individual DRC error markers according to their root cause. IC Validator runs can read these classified errors into a GUI, allowing users to track the previously-classified violations within the Custom Designer cockpit.
Demo
09:03
/Community/PublishingImages/videoimages/images6851/DRC_Debugging.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-icv-drc-Jan6.html
Mini Demo: Interactive Auto-Router
Custom Designer's Interactive Auto-Router is an innovative feature that improves single-net routing productivity. It comes in two modes of operation: Point-to-Point (P2P) and Follow-the-Cursor (FTC) routing. Both P2P and FTC will follow the preferred layer routing direction while routing nets LVS and DRC correct in real-time.
Demo
07:54
/Community/PublishingImages/videoimages/images6851/AutoRouter.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-interactive-auto-Mar11-11.html
CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS co-simulation solution, CustomExplorer Ultra aids engineers in rapidly performing customized advanced analyses for transistor-level analog, mixed-signal and SoC designs.
Demo
11:38
/Community/PublishingImages/videoimages/images6851/CustomExplorer.jpg
http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=custom-explorer-demo-apr18.html
Introducing Galaxy Test 2010.12
Mona Marmash introduces the latest releases and new capabilities of DFTMAX compression and TetraMAX ATPG.
Mona, Marmash, Sr. Staff Support Center Engineer, Synopsys
02:58
/Community/PublishingImages/videoimages/images6851/MonaMarmash.jpg
none
Faster Design Closure with PrimeTime AOCV
PrimeTime Advanced OCV, is a mature and proven technology in Static Timing Analysis to address the variation challenges in designs at 65nm or below process nodes.
Feroze Taraporevala, senior R&D manager, Implementation Group, Synopsys
04:09
/Community/PublishingImages/videoimages/images6851/FerozeTaraporevala_FasterDesign.jpg
none
PrimeTime Scales Timing Analysis Beyond 500 Million Instances
PrimeTime HyperScale technology extends PrimeTime static timing analysis to support designs beyond 500 million instances. It delivers between 5 and 10X better runtimes for the full chip timing analysis and 5 to 10X smaller memory footprint compared with classic flat analysis.
Antun Domic, senior vice president and general manager, Implementation Group, Synopsys
04:11
/Community/PublishingImages/videoimages/images6851/AntunDomic_PrimeTime.jpg
none
In-Design physical verification with IC Validator and IC Compiler delivers 100 tapeouts just one year after introduction.
In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.
Aart de Geus, Synopsys Chairman and CEO
02:35
/Community/PublishingImages/videoimages/images6851/AartdeGeus.jpg
none
DC Explorer Demo
Early RTL exploration accelerates synthesis and place & route
Demo
04:44
/Community/PublishingImages/videoimages/images6851/DCExplorerDemo.jpg
http://www.synopsys.com/apps/dcexplorer2011/dcexplorer-demo.html?cmp=DCExplorer-Demo-RTL-HL-Mar28
DC Explorer Video
Introducing DC Explorer
Antun Domic, General Manager, Implementation Group, Synopsys, Inc.
02:59
/Community/PublishingImages/videoimages/images6851/AntunDomic.jpg
none
SNUG Preview Demo
Synopsys
08:22
/Community/PublishingImages/videoimages/images6851/SNUGPreviewDemo.jpg
none
Introduction to Synthesis-Based Test
Watch this short video to learn about Synopsys’ Synthesis-Based Test technology and Test product portfolio.
Arif Samad, VP Engineering, Synopsys
02:34
/Community/PublishingImages/videoimages/images6851/Synthesis-BasedTest.jpg
none
IC Compiler Customer Successes
In March 2009, SNUG (Synopsys User Group) San Jose drew a large crowd of Synopsys users who gathered to hear from others about their experiences presented in papers, tutorials, and panels. The videos below provide you with a brief overview from customers who presented at San Jose SNUG. Visit the SNUG website for a complete list of IC Compiler papers and presentations. This DAC 2008 event provided an opportunity for members of the electronic design community to learn more about customer design successes with IC Compiler. The event drew a capacity crowd as guest speakers from ARM, Intel, STMicroelectronics, Texas Instruments, and Toshiba shared their experiences from a variety of high-end designs utilizing the latest technology advances in IC Compiler: Concurrent Hierarchical Design, MinChip technology, DFM and IC Compiler’s new Zroute routing technology.
Philip Watson, Implementation Environment Program Manager; Raj Varada, Principal Engineer; Naveen Raina, Technical Specialist & Mutsunori Igarashi, Chief Specialist, Design Methodology Development.
09:14
/Community/PublishingImages/videoimages/images6851/IC_CompilerCustomerSuccesses.jpg
/Tools/Implementation/PhysicalImplementation/Pages/ICCompiler-Successes.aspx
Latest Features of PrimeTime
George Mekhtarian, Product Marketing Manager in Synopsys’ Implementation Group
03:00
/Community/PublishingImages/videoimages/images6851/pt_multicore_mekhtaria.jpg
none
Power-Aware Test
Conventional compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop and overheating.
Tom Williams, Synopsys Fellow
02:01
/Community/PublishingImages/videoimages/images6851/PowerAware09_Tom.jpg
none
Expert Shootout: Parasitic Extraction
Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys
Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys
05:39
/Community/PublishingImages/videoimages/images6851/ExpertShootout.jpg
http://chipdesignmag.com/lpd/blog/2010/02/11/the-ins-and-outs-of-parasitic-extraction/
Tips for Getting the Best PrimeTime Performance
Few easy ways for getting the best PrimeTime performance and achieving faster sign-off analysis.
Karen Linser, staff applications engineer in Synopsys’ Implementation Group
04:15
/Community/PublishingImages/videoimages/images6851/primetime4x_klinser.jpg
none
Small Delay Defects: The Need for Better At-Speed Tests
Manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures. Dr. T.W. Williams introduces technology developed at Synopsys to detect defects creating these delays, thereby increasing the test quality.
Tom Williams, Synopsys Fellow
02:00
/Community/PublishingImages/videoimages/images6851/test_sdd09_tom.jpg
none
IC Compiler Lunch Event: ARM, Ltd.
ARM Cortex-A9 MPCore Multi-core Processor Hierarchical Implementation with IC Compiler Learn how ARM utilized IC Compiler’s concurrent hierarchical design for multi-core implementation, driving better performance as well as better throughput.
Philip Watson, Implementation Environment Program Manager
12:18
/Community/PublishingImages/videoimages/images6851/dac08icc_arm_watson.jpg
none
IC Compiler Lunch Event: Toshiba Corp
Concurrent Hierarchical Design with IC Compiler, Real Life Application on Mobile Multi-Media Processor IC Compiler offers the industry’s first concurrent hierarchical design system that delivers a high degree of automation combined with high-quality optimization. Learn more about the results Toshiba achieved with the latest advances in IC Compiler.
Mutsunori Igarashi, Chief Specialist, Design Methodology Development
09:09
/Community/PublishingImages/videoimages/images6851/dac08icc_toshiba_igarshi.jpg
none
Perspective: Boost your design productivity
Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule.
Antun Domic, senior vice president and general manager of Synopsys' Implementation Group
04:38
/Community/PublishingImages/videoimages/images6851/dcgraphical_antun.jpg
none
DAC 2010 IC Compiler In-Design Videolog
At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics
01:28:53
/Community/PublishingImages/videoimages/images6851/icc_dac10lunch.jpg
/Tools/Implementation/PhysicalImplementation/Pages/ICC-DAC10Lunch.aspx
Accelerate Product Ramp with TetraMAX ATPG and Yield Explorer
Girish Patankar discusses diagnostics in TetraMAX ATPG, accuracy improvements with physical diagnostics, and how TetraMAX ATPG and Yield Explorer form a complete solution for volume diagnostics.
Girish Patankar, Sr. R&D Manager
04:22
/Community/PublishingImages/videoimages/images6851/1_videothumbnail.jpg
none
Design Compiler 2010 Video
Antun Domic, General Manager, Implementation Group, Synopsys, Inc
03:34
/Community/PublishingImages/videoimages/images6851/DesignCompiler2010.jpg
none
Galaxy Test 2010.03 Introduction
Amy Mitby introduces the latest release and highlights four new powerful features
Amy Mitby, Sr. Test Applications Consultant
03:06
/Community/PublishingImages/videoimages/images6851/GalaxyTest2010.03Introduction.jpg
none
Pin-Limited Test
Current trends are accelerating the need for pin-limited test. Amy Mitby introduces capabilities in DFTMAX compression that allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins.
Amy Mitby, Sr. Test Applications Consultant
02:41
/Community/PublishingImages/videoimages/images6851/dftmax_pin-jan26-10-amitby.jpg
none
PrimeTime SIG 2009
In July 2009, Synopsys hosted two PrimeTime SIG events in Bangalore, India and San Francisco, CA focused on STA performance and productivity, as well as new timing constraints management technology. Hear what experts from leading companies had to say about taking advantage of the latest PrimeTime features to boost productivity.
T.W. Williams, Synopsys Fellow; Jagan Ayyaswami, Principal Manager, Physical Design Group, Qualcomm; Rajagopal K.A., Technologist, Texas Instruments; Rich Laubhan, Manager of Design Integrity, LSI Corp.; Michio Komoda, Sr. Engineer, DFM & Digital EDA Technology Development, Renesas Corp.
01:16:02
/Community/PublishingImages/videoimages/images6851/PrimeTimeSIG2009.jpg
http://synopsys1.http.internapcdn.net/synopsys1/dac09ptsig/main.htm
Perspective: How to Improve Design TTR
John Chilton, senior vice president of Marketing and Business Development at Synopsys, talks about the importance of utilizing today’s widely-available multi-core processor-based compute infrastructures to accelerate design TTR.
John Chilton, senior vice president of Marketing and Business Development at Synopsys
03:05
/Community/PublishingImages/videoimages/images6851/multicore_jchilton.jpg
none
10X Faster Routing Runtime
Combine advanced routing algorithms with multi-threading technology, and you get a speed increase of >10X on quad-core machines.
Tong Gao, Synopsys Scientist and architect of Zroute,
02:40
/Community/PublishingImages/videoimages/images6851/icc_zroute08_tong.jpg
none
IC Compiler Lunch Event: Intel Corp.
IC Compiler: Routing and Design for Manufacturability (DFM) IC Compiler uses concurrent optimization techniques to simultaneously consider the impact of manufacturing rules, timing, and other design goals for high QoR and improved manufacturability.
Raj Varada, Principal Engineer
12:00
/Community/PublishingImages/videoimages/images6851/dac08icc_intel_varada.jpg
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IC Compiler Lunch Event: STMicroelectronics
Automatic Block Size Reduction with IC Compiler MinChip Technology IC Compiler reduces runtime and memory while delivering hand-craft-quality macro placement, MinChip die size reduction, clock tree synthesis, skew optimization, clock-gate merging, and more. STMicroelectronics achieved a huge reduction in die-size with a runtime of only 4 to 6 hours!
Naveen Raina, Technical Specialist
08:33
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SNUG Boston 2008: Galaxy Custom Designer Launch
On September 22 at SNUG Boston 2008, Synopsys unveiled Galaxy Custom Designer™, the modern-era custom AMS implementation solution. On hand to support the launch were representatives from Cray and Priva Technologies who presented their experiences using/supporting Custom Designer.
Aart de Geus, CEO, Synopsys, Inc.; Tom Quan, Design Methodology & Service Marketing; Matt Priest, Hardware Engineer; Jeff Berkman, CTO
44:17
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/Tools/Implementation/CustomImplementation/Pages/BostonSNUG08Videos.aspx
IC Validator 06:47
Mini Demo: SmartDRD Technology 05:33
Mini Demo: High-performance Bus Editing with Bridge and Tunnel 05:43
Mini Demo: SDL Migrate Featuring the SDL Import Command 05:16
Mini Demo: Advances in Schematic Capture Featuring the Custom Designer Schematic Editor 09:20
Mini Demo: Advanced SDL Cloning 05:03
Mini Demo: SDL Interdigitation 06:34
Mini Demo: Layout Commands - Part One 06:54
Mini Demo: Layout Commands – Part Two 04:59
Mini Demo: Productive DRC Debugging with IC Validator and Custom Designer 09:03
Mini Demo: Interactive Auto-Router 07:54
CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment 11:38
Introducing Galaxy Test 2010.12 02:58
Faster Design Closure with PrimeTime AOCV 04:09
PrimeTime Scales Timing Analysis Beyond 500 Million Instances 04:11
In-Design physical verification with IC Validator and IC Compiler delivers 100 tapeouts just one year after introduction. 02:35
DC Explorer Demo 04:44
DC Explorer Video 02:59
SNUG Preview Demo 08:22
Introduction to Synthesis-Based Test 02:34
IC Compiler Customer Successes 09:14
Latest Features of PrimeTime 03:00
Power-Aware Test 02:01
Expert Shootout: Parasitic Extraction 05:39
Tips for Getting the Best PrimeTime Performance 04:15
Small Delay Defects: The Need for Better At-Speed Tests 02:00
IC Compiler Lunch Event: ARM, Ltd. 12:18
IC Compiler Lunch Event: Toshiba Corp 09:09
Perspective: Boost your design productivity 04:38
DAC 2010 IC Compiler In-Design Videolog 01:28:53
Accelerate Product Ramp with TetraMAX ATPG and Yield Explorer 04:22
Design Compiler 2010 Video 03:34
Galaxy Test 2010.03 Introduction 03:06
Pin-Limited Test 02:41
PrimeTime SIG 2009 01:16:02
Perspective: How to Improve Design TTR 03:05
10X Faster Routing Runtime 02:40
IC Compiler Lunch Event: Intel Corp. 12:00
IC Compiler Lunch Event: STMicroelectronics 08:33
SNUG Boston 2008: Galaxy Custom Designer Launch 44:17
  
In-Design Physical Verification Milestone
In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.
Dr. Aart de Geus, Synopsys Chairman and CEO
02:35
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In-Design Physical Verification Milestone 02:35
  
Why buy IP from an IP supplier with lots of customers?
Does proven IP have more value?
Eric Huang, Product Manager, Synopsys and Theo Goguely, Product Manager, DisplayLink
01:30
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Synopsys Demonstrates DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair
This demonstration will feature the post-silicon interactive automation capabilities of the DesignWare STAR Silicon Browser, which utilizes the DesignWare STAR Memory System's embedded test & repair IP solution.
Yervant Zorian, Chief Architect, Synopsys, Gevorg Torjyan, R&D Engineer, Synopsys
05:21
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Synopsys Demonstrates MIPI Camera and Display Prototyping System
Synopsys demonstrates proven system-level interoperability utilizing Synopsys' DesignWare MIPI CSI-2 and DSI host controller as well as the DesignWare MIPI D-PHY IP solution
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP; Miguel Falcao Sousa, R&D Manager, Solutions Group
03:34
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MCCI USB 3.0 Software on Synopsys' HAPS with DesignWare SuperSpeed USB 3.0 Cores & PHYs
This demonstration will showcase Synopsys' HAPS platform with a DesignWare SuperSpeed USB 3.0 core and PHY running MCCI's USB 3.0 software stack. Designers will learn how they can start their design process for mobile phone and multimedia portable USB products with working drivers.
Eric Huang, Product Marketing Manager, USB Digital Cores; Terry Moore, CEO, MCCI
04:21
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DisplayLink Demonstrates Video Streaming with Synopsys’ DesignWare® SuperSpeed USB 3.0 and HDMI IP
Learn how DisplayLink uses Synopsys DesignWare SuperSpeed USB 3.0 and HDMI IP to create their next-generation USB graphics technology.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP; Jason Slaughter, Director of Marketing, DisplayLink
02:44
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DisplayLink Explains Video Compression Over USB 3.0
Discover how DisplayLink leverages adaptive compression over USB 3.0 to create a smooth, full screen video and graphic experience with low latency.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP; Jason Slaughter, Director of Marketing, DisplayLink
02:12
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Implementing a Audio Video Bridge with DesignWare Ethernet QoS
With the release of the IEEE 802.1 specifications for Audio Video Bridging (AVB) designers can now include this functionality in their designs with the DesignWare® Ethernet QOS core. This demonstration will show how a Ethernet design can easily be configured to support AVB capable networks.
John Swanson, Senior Manager, Synopsys
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Migrating a USB 2.0 design to USB 3.0 using Synopsys’ DesignWare SuperSpeed USB 3.0 IP and MCCI’s solution
In this video, you will discover how to quickly migrate an existing USB 2.0 design to USB 3.0. By leveraging Synopsys’ silicon-proven, complete DesignWare SuperSpeed USB 3.0 IP solution with MCCI’s software stack, you can lower integration risk and improve time-to-market of your next-generation USB 3.0 design.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI
4:56
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DesignWare SuperSpeed USB 3.0 IP on a Synopsys HAPS-51 platform
In this video, you will see how the Synopsys DesignWare® SuperSpeed USB 3.0 controller and PHY IP enable faster performance speeds, reaching up to 335 MB/s. Using MCCI’s USB 3.0 software stack on a Synopsys HAPS platform, the DesignWare SuperSpeed USB 3.0 IP solution offers USB 3.0 speeds in both 2.0 and 3.0 modes.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP
3:38
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Synopsys Demonstrates the Industry's First Silicon-Proven MIPI M-PHY
This video demonstrates the fully characterized, silicon-proven capabilities of the DesignWare MIPI M-PHY IP solution, highlighting its silicon performance as well as its electrical characteristics, which exceed target specifications.
Celio Albuquerque, R&D Manager, DesignWare MIPI PHY IP
3:41
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Understanding MIPI
This video provides a high level view of popular MIPI protocols and helps you get up to speed with latest mobile market innovations. We will also introduce IP solutions that can help you differentiate your products in the mobile market space.
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP
06:26
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Synopsys Demonstrates Silicon-Proven Implementation of DesignWare® Audio IP
See how Synopsys’ DesignWare Audio IP delivers superb audio quality, featuring a full set of audio functions needed by most of today’s consumer electronic devices. Synopsys also showcases the true Hi-Fi audio quality delivered by the DesignWare Audio Codec with dynamic range exceeding 96dB, while keeping the power consumption at minimum levels.
João Risques, Product Manager for DesignWare Audio and Video AFE IP, Synopsys
08:54
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Synopsys and LeCroy Showcase PCI Express® 3.0 Interoperability at PCI-SIG 2010
This demonstration features LeCroy’s Summit T3-16 Protocol Analyzer, Summit Z3-16 Protocol Exerciser and the Summit Z3-16 Test Platform to test a PCI Express 3.0-based design for compliance to the PCI Express 3.0 specification. The design-under-test (DUT) utilizes the DesignWare® IP for PCI Express 3.0.
Featuring: John Wiedemeier, Product Manager, LeCroy; Scott Knowlton, Product Marketing Manager, Synopsys
03:04
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Synopsys and Agilent Enable PCI Express 3.0 Ecosystem at PCI-SIG 2010
Utilizing a DUT that implements the DesignWare IP for PCI Express 3.0, this demonstration features Agilent’s complete test solution for PCI Express 3.0 and the Digital Test Console to check for compliance to the PCI Express 3.0 specification.
Featuring: Yenyi Fu, Product Manager, Agilent; Scott Knowlton, Product Marketing Manager, Synopsys
02:46
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Make it EASY with Synopsys DesignWare DDR HARD PHY IP
By using DDR Hard PHY IP, you achieve: quicker integration, easier timing closure, better performance and less silicon area. With a hard PHY, all the IP is supplied by one IP vendor and includes I/Os. Hard PHYs have lower jitter, better duty cycle, an overall superior clock strategy and use identical circuits for every bit of the parallel DDR interface reducing skew. In addition, hard PHYs implemented in test chips are equivalent to the customer's PHY where as soft PHYs are different GDSII every time.
Synopsys Super Stars
00:57
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DesignWare SuperSpeed USB 3.0 xHCI demo
See high-definition video using the DesignWare® SuperSpeed USB 3.0 xHCI Host and Device Controller implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video streaming from a standard PC running on a Linux operating system with a SuperSpeed USB 3.0 xHCI Host Stack, into mass storage device.
Eric Huang, Product Marketing Manager, USB Digital
01:30
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Synopsys Demonstrates SuperSpeed USB 3.0 Interoperability
This demonstration shows proven interoperability of Synopsys' DesignWare USB 3.0 PHY with the DesignWare USB 3.0 host and device controllers implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Gervais Fong Product Marketing Manager, USB PHY IP
03:25
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DesignWare DDR3/2 IP Demo at 1600 Mbps
Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Graham Allan, Product Marketing Manager, Memory Interface IP; Vishal Thareja, Test Engineer
03:00
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DisplayLink Streams Uncompressed HD 1080p Video Using Synopsys’ USB 3.0 IP
DisplayLink demonstrates how it uses DesignWare SuperSpeed USB 3.0 and HDMI IP to show full HD resolution over USB 3.0 by taking video directly out of USB 3.0 on the PC, convert it to HDMI and display it directly to a high-resolution monitor.
Gervais Fong, Product Marketing Manager, USB PHY IP Dennis Crespo, Vice President of Marketing, DisplayLink
03:55
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Silicon-proven DesignWare® HDMI TX Controller and PHY IP on Synopsys’ HAPS-51 Platform
Synopsys shows how fixed video and audio patterns are transmitted by the DesignWare HDMI TX controller and PHY. See the image quality improve as resolution of video test pattern is increased from 480p to 720p to 1080p, 60 Hz frame formats. Also see the EDID info collected by TX Controller/PHY Display Data Channel (DDC) from the sink device (DTV) to support negotiation and find the best supported color format and frame rate.
Manmeet Walia, Product Manager for Mixed-Signal PHY IP, Synopsys
08:43
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Synopsys and MCCI SuperSpeed Media Player Demonstration
See Synopsys and MCCI demonstrate how music can be synchronized in a matter of seconds in a USB 3.0 media player compared to minutes in a USB 2.0 media player. The demonstration consists of the Synopsys DesignWare® SuperSpeed USB Digital Controller and MCCI SuperSpeed USB Software on an FPGA hardware platform.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI
06:04
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TI Demonstrates USB 3.0 Interoperability at IDF with DesignWare IP
TI demonstrates SuperSpeed USB interoperability and USB 2.0 backward compatibility. The demo showcases TI's TUSB80x0 Hub and TUSB9260 SATA bridge controller with the Synopsys DesignWare SuperSpeed USB 3.0 IP
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI
02:05
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DesignWare IP for PCI Express 2.0 Complete Solution Demo
See a live demonstration of the 45-nm DesignWare PHY and controller IP for PCI Express® 2.0 operating in a single-lane configuration at 5 GT/s. The demonstration verifies 5 GT/s operation using the PCI® Tree software and executes Reads and Writes between the demo hardware and a PC to show throughput performance levels.
Scott Knowlton, Sr. Produt Marketing Manager, Synopsys
06:59
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See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device
See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device digital controllers in a single demonstration. In this video, Synopsys shows interoperability between the DesignWare SuperSpeed USB 3.0 controllers and a USB 3.0 mass storage device, USB 2.0 flash controller and USB 1.1 mouse.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP
02:13
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See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution
See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution, consisting of digital controllers, mixed-signal PHY and Verification IP. This video consists of hardware demonstrations for the DesignWare SATA AHCI Host, Device, PHY and 6 Gb/s IP solutions.
Mat Loikkanen Sr. R&D Engineer, Synopsys; Mick Posner Sr. Product Marketing Manager, Synopsys
05:20
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See Synopsys and Texas Instruments demonstrate SuperSpeed USB 3.0 Interoperability
Join us in the Synopsys lab to see proven interoperability between the Texas Instrument’s USB 3.0 transceiver and the Synopsys DesignWare USB 3.0 host and device controller implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI
07:36
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See Global Unichip’s SSD Demo Featuring DesignWare® SATA IP
See how Global Unichip (GUC) utilized Synopsys' silicon-proven DesignWare® SATA IP in its Solid State Device (SSD) GP5080 platform to demonstrate a netbook boot-up time of less than half a minute. The hardware platform consists of a high-performance 32-bit ARM7 processor, SATA 3Gb/s interface, SLC/MLC NAND Flash management of up to 4 channels, 8 banks with ECC.
Kurt Huang, Director of Marketing, Global Unichip Corp.
02:45
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See an actual USB 3.0 data transfer utilizing the DesignWare SuperSpeed USB Host and Device Controllers implemented in an FPGA
Join Synopsys in our lab to see actual USB 3.0 data transfer utilizing the DesignWare Superspeed USB Host and Device Controllers implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video, streaming from the device into the host with a measured throughput of 460 MB/s utilizing the Lecroy CATC analyzer.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP
02:58
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See how we verify the DesignWare IP for DDR2/3 PHY and Controllers
See firsthand the test equipment and custom boards developed and used by Synopsys to verify our DDR IP. Witness full speed write and read data eyes, at speed functionality testing, duty cycle and phase error tests and jitter analysis results.
Graham Allan, Product Marketing Manager, DDR IP
06:47
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Join us in the Synopsys lab to see how we verify the DesignWare USB 2.0 NanoPHY IP
The video will take you through our silicon verification board set up, show the unique tunability feature and highlight the extensive characterization process of the USB 2.0 nanoPHY.
Gervais Fong, Product Marketing Manager, USB PHY IP
06:54
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See a silicon demo of the DesignWare PHY for PCI Express 2.0
Join Synopsys in our lab to see how we deliver a compliant, robust PCI Express 2.0 PHY and enable visibility into the link performance through unique on-chip diagnostics.
Navraj Nandra, Marketing Director MSIP
05:51
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Why buy IP from an IP supplier with lots of customers? 01:30
Synopsys Demonstrates DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair 05:21
Synopsys Demonstrates MIPI Camera and Display Prototyping System 03:34
MCCI USB 3.0 Software on Synopsys' HAPS with DesignWare SuperSpeed USB 3.0 Cores & PHYs 04:21
DisplayLink Demonstrates Video Streaming with Synopsys’ DesignWare® SuperSpeed USB 3.0 and HDMI IP 02:44
DisplayLink Explains Video Compression Over USB 3.0 02:12
Implementing a Audio Video Bridge with DesignWare Ethernet QoS
Migrating a USB 2.0 design to USB 3.0 using Synopsys’ DesignWare SuperSpeed USB 3.0 IP and MCCI’s solution 4:56
DesignWare SuperSpeed USB 3.0 IP on a Synopsys HAPS-51 platform 3:38
Synopsys Demonstrates the Industry's First Silicon-Proven MIPI M-PHY 3:41
Understanding MIPI 06:26
Synopsys Demonstrates Silicon-Proven Implementation of DesignWare® Audio IP 08:54
Synopsys and LeCroy Showcase PCI Express® 3.0 Interoperability at PCI-SIG 2010 03:04
Synopsys and Agilent Enable PCI Express 3.0 Ecosystem at PCI-SIG 2010 02:46
Make it EASY with Synopsys DesignWare DDR HARD PHY IP 00:57
DesignWare SuperSpeed USB 3.0 xHCI demo 01:30
Synopsys Demonstrates SuperSpeed USB 3.0 Interoperability 03:25
DesignWare DDR3/2 IP Demo at 1600 Mbps 03:00
DisplayLink Streams Uncompressed HD 1080p Video Using Synopsys’ USB 3.0 IP 03:55
Silicon-proven DesignWare® HDMI TX Controller and PHY IP on Synopsys’ HAPS-51 Platform 08:43
Synopsys and MCCI SuperSpeed Media Player Demonstration 06:04
TI Demonstrates USB 3.0 Interoperability at IDF with DesignWare IP 02:05
DesignWare IP for PCI Express 2.0 Complete Solution Demo 06:59
See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device 02:13
See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution 05:20
See Synopsys and Texas Instruments demonstrate SuperSpeed USB 3.0 Interoperability 07:36
See Global Unichip’s SSD Demo Featuring DesignWare® SATA IP 02:45
See an actual USB 3.0 data transfer utilizing the DesignWare SuperSpeed USB Host and Device Controllers implemented in an FPGA 02:58
See how we verify the DesignWare IP for DDR2/3 PHY and Controllers 06:47
Join us in the Synopsys lab to see how we verify the DesignWare USB 2.0 NanoPHY IP 06:54
See a silicon demo of the DesignWare PHY for PCI Express 2.0 05:51
  
Lynx Design System Readiness for 28nm
Andy Potemski, Director, Global Technical Services, Synopsys, presents at the Common Platform Technology Forum.
Andy Potemski, Director, Global Technical Services, Synopsys
27:08
/Community/PublishingImages/videoimages/images6851/Lynx-video-28nm.jpg
http://synopsys1.http.internapcdn.net/synopsys1/lynx-cp-tech/main.htm
S2S Verification Overview Video
High-level overview of the Systems to Silicon Solution with David Park
David Park, Solutions Manager, Synopsys
02:06
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S2S Verification Video
Interview with Rajiv Maheshwary and Janick Bergeron
Janick Bergeron, Scientist, Synopsys, Inc.; Rajiv Maheshwary, Senior director, Synopsys, Inc.
27:02
/Community/PublishingImages/videoimages/images6851/s2s-verification6851.jpg
http://synopsys1.http.internapcdn.net/synopsys1/snps-journal-janickb/main.htm
Customer Highlight
ST meets AMS simulation criteria with VCS-MX and CustomSim
Yuval Shay, Staff Engineer, Mixed-Signal Verificatin
17:07
/Community/PublishingImages/videoimages/images6851/vcs_mx6851.jpg
http://synopsys1.http.internapcdn.net/synopsys1/dac10-verification-st/main.htm
VLSI Research: Synopsys’ new custom IC design suite
Finally . . . an integrated EDA tool for custom IC design. It’s a totally new, ground-up, software package. Yet, its user interface is so similar to what you’ve been using that you’ll be surprised as to how familiar it seems.
Ed Lechner
12:54
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http://vstream1.vlsiresearch.com/public/ed_lechner_080905/ed_lechner_index.htm
Eclypse Low Power Solution
Josefina Hobbs introduces the Eclypse Low Power Solution
Joselina Hobbs
02:05
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An Introduction to The Lynx Design System
Neel Desai, Product Marketing Manager, provides an overview of this unique and comprehensive chip development platform.
Neel Desai, Product Marketing Manager
06:14
/Community/PublishingImages/videoimages/images6851/lynx_video_neel.jpg
http://www.webexlivestream.com/webx001/30112/
DAC 2010: Galaxy Implementation Platform Overview
Steve Smith, Sr. Director of Marketing for the Galaxy Platform provides an overview of the many advancements made in the last year to Synopsys' comprehensive RTL-to-GDSII implementation solution, including a tighter connection between synthesis and place-and-route with physical guidance, new In-Design physical verification, enhanced signoff for large designs, improved multicore capabilities, the Lynx Design System and 28nm readiness.
Synopsys
05:16
/Community/PublishingImages/videoimages/images6851/DAC10-EdaCafe.jpg
http://www10.edacafe.com/video/Synopsys-Galaxy-Implementation-Platform-Steve-Smith/32005/media.html
Lynx Design System @ DAC 2010
Neel talks about the Lynx Design System and recent updates since its introduction last year including recent customer successes. At DAC2010 we announced a new multi-year collaboration with ARM and the Common Platform alliance that optimizes the Lynx Design System and its Galaxy™ Implementation Platform-enabled flow for ARM's advanced physical IP and the ARM Cortex™ A9 MPCore processor.
Neel Desai, Product Marketing Manager
03:42
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Automotive
Join our FREE Robust Design Webcast Series to discover how Robust Design methodologies coupled with Synopsys Saber simulation and analysis solution can improve your design performance and reliability for Mechatronic Systems.
Mike Jensen, Coporate Applications Engineer, Saber product line, Synopsys Inc.
54:56
/Community/PublishingImages/videoimages/images6851/Automative.jpg
http://www.synopsys.com/cgi-bin/saber/webinars/reg1.cgi
IC Compiler In-Design Technology
At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics
01:28:53
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/Tools/Implementation/PhysicalImplementation/Pages/ICC-DAC10Lunch.aspx
SNUG San Jose Keynote
Aart de Geus, Synopsys CEO, delivers the opening keynote address at SNUG San Jose 2008.
Aart de Geus, Synopsys CEO
53:54
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Mike Keating: The Future of Low Power 2008
Mike Keating, Synopsys Fellow, presents a 2008 update to last year's popular SNUG presentation. This talk consists of a leisurely walk through the power management spectrum, with digressions into various interesting side-issues.
Mike Keating
01:00:53
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Perspective: SDD Test to the Rescue
Carl Holzwarth, director of Test R&D
02:29
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Godwin Maben: Low Power Trends and Methodology
Godwin Maben
54:14
/Community/PublishingImages/videoimages/images6851/eclypse_lptrends_godwin.jpg
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FPGA prototyping gains ground
At the Design Automation Conference (DAC) in Anaheim, Calif., Mark LaPedus, semiconductor editor from EE Times, caught up with Andy Haines, vice president of marketing of Synplicity, which was recently acquired by Synopsys. In a video, Smith, Haines discusses the growing importance of FPGA prototyping.
Mark LaPedus and Andy Haines
04:29
/Community/PublishingImages/videoimages/images6851/FPGAprotot_gains_ground.jpg
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=208403774
Lynx Design System Readiness for 28nm 27:08
S2S Verification Overview Video 02:06
S2S Verification Video 27:02
Customer Highlight 17:07
VLSI Research: Synopsys’ new custom IC design suite 12:54
Eclypse Low Power Solution 02:05
An Introduction to The Lynx Design System 06:14
DAC 2010: Galaxy Implementation Platform Overview 05:16
Lynx Design System @ DAC 2010 03:42
Automotive 54:56
IC Compiler In-Design Technology 01:28:53
SNUG San Jose Keynote 53:54
Mike Keating: The Future of Low Power 2008 01:00:53
Perspective: SDD Test to the Rescue 02:29
Godwin Maben: Low Power Trends and Methodology 54:14
FPGA prototyping gains ground 04:29
  
Innovation Optimized! Video
ARM, Common Platform and Synopsys executives share their views on the recent collaboration announcement to deliver a technology enablement solution for the design and manufacture of 32nm mobile devices.
Dr. Aart de Geus, Chairman of the Board and CEO, Synopsys; Michael Cadigan, General Manager, Microelectronics Division, IBM Systems and Technology Group; Dr. C.S. Choi, Executive Vice President, LSI Division, Samsung Electronics; Chia Song Hwee, President and CEO, Chartered Semiconductor Manufacturing ; Warren East, Chief Executive Office, ARM Holdings
06:50
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http://www.commonplatform.com/newsroom/multimedia/dacvideo/
Explore R&D Engineering
Explore the life of an R&D engineer at Synopsys. Do you have a passion for software? Do you enjoy solving difficult problems? Find out what it takes to be an R&D Engineer at Synopsys.
Synopsys Inc.
01:22
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http://www.monstervideoprofile.com/mvp/synopsys/rd
Explore Applications Engineering
Find out what it takes to be an Applications Engineer at Synopsys. If you enjoy working with customer and sharing in their success, this may be a position for you!
Synopsys Inc.
01:22
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http://www.monstervideoprofile.com/mvp/synopsys/ac
A Look Inside Synopsys
Take a look at what it is like to work at Synopsys, our work culture, values, global reach, employee impact and career opportunities.
Synopsys Inc.
03:34
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http://www.monstervideoprofile.com/mvp/synopsys
Optimized Implementation Methodology for High Performance Low Power Processor Cores at 40nm and Below
Both mobile and tethered devices require increased performance with decreased power consumption. In this tutorial, we present how the optimized methodology for processor cores at 40nm and below address these needs. This tutorial describes results using some of the latest DC Topographical and IC Compiler capabilities together with a highly tuned set of user constraints, delivering impressive performance results. Key techniques covered include: shorten wires for higher clock frequency, methodology to minimize congestion and best convergence with high utilization and high cell density, crosstalk prevention and fixing, clock tree synthesis constraints and methodology, leakage optimization, and signoff optimization. Target audience: Experienced physical designers.
Daniel Biset, Corporate Application Engineer - Synopsys, Inc.
74:58
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http://solvnet.synopsys.com/onlinetraining/SNUG_SJ2010_biset/index.html
Innovation Optimized! Video 06:50
Explore R&D Engineering 01:22
Explore Applications Engineering 01:22
A Look Inside Synopsys 03:34
Optimized Implementation Methodology for High Performance Low Power Processor Cores at 40nm and Below 74:58
 
Why buy IP from an IP supplier with lots of customers?
Does proven IP have more value?
Eric Huang, Product Manager, Synopsys and Theo Goguely, Product Manager, DisplayLink
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Synopsys Demonstrates DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair
This demonstration will feature the post-silicon interactive automation capabilities of the DesignWare STAR Silicon Browser, which utilizes the DesignWare STAR Memory System's embedded test & repair IP solution.
Yervant Zorian, Chief Architect, Synopsys, Gevorg Torjyan, R&D Engineer, Synopsys
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Synopsys Demonstrates MIPI Camera and Display Prototyping System
Synopsys demonstrates proven system-level interoperability utilizing Synopsys' DesignWare MIPI CSI-2 and DSI host controller as well as the DesignWare MIPI D-PHY IP solution
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP; Miguel Falcao Sousa, R&D Manager, Solutions Group
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MCCI USB 3.0 Software on Synopsys' HAPS with DesignWare SuperSpeed USB 3.0 Cores & PHYs
This demonstration will showcase Synopsys' HAPS platform with a DesignWare SuperSpeed USB 3.0 core and PHY running MCCI's USB 3.0 software stack. Designers will learn how they can start their design process for mobile phone and multimedia portable USB products with working drivers.
Eric Huang, Product Marketing Manager, USB Digital Cores; Terry Moore, CEO, MCCI
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Meet the Prototypers - Introducing the FPMM
Meet the Prototypers: Introducing the FPMM was a panel discussion held at the 2011 DVCon show in San Jose, March 2, at the DoubleTree Hotel.
Phil Dworsky, Synopsys; Kevin Morris, Synopsys
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http://synopsys1.http.internapcdn.net/synopsys1/intro-fpmm-dvcon2011/main.htm
IC Validator
Antun Domic, Senior VP and GM, Implementation Group, Synopsys, Inc.
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DisplayLink Demonstrates Video Streaming with Synopsys’ DesignWare® SuperSpeed USB 3.0 and HDMI IP
Learn how DisplayLink uses Synopsys DesignWare SuperSpeed USB 3.0 and HDMI IP to create their next-generation USB graphics technology.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP; Jason Slaughter, Director of Marketing, DisplayLink
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DisplayLink Explains Video Compression Over USB 3.0
Discover how DisplayLink leverages adaptive compression over USB 3.0 to create a smooth, full screen video and graphic experience with low latency.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP; Jason Slaughter, Director of Marketing, DisplayLink
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Implementing a Audio Video Bridge with DesignWare Ethernet QoS
With the release of the IEEE 802.1 specifications for Audio Video Bridging (AVB) designers can now include this functionality in their designs with the DesignWare® Ethernet QOS core. This demonstration will show how a Ethernet design can easily be configured to support AVB capable networks.
John Swanson, Senior Manager, Synopsys
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Mini Demo: SmartDRD Technology
SmartDRD is a new, innovative technology built into Galaxy Custom Designer LE for interactive DRC violation visualization, detection and correction. This mini demo shows how the DRDAutoFix feature automatically detects and corrects DRC violations in a fraction of a second.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo.html
Mini Demo: High-performance Bus Editing with Bridge and Tunnel
Bus, Bridge and Tunnel are innovative technologies built into Galaxy Custom Designer LE for higher productivity in high-performance interactive bus routing and editing. This mini demo illustrates interactive bus routing with user-selectable cornering options and automatic via insertion working with and without connectivity. The Bridge and Tunnel command allows quick layer changes in regions of a routed bus or net with automatic via insertion.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-Bus-demo-Jun14.html
Mini Demo: SDL Migrate Featuring the SDL Import Command
Custom Designer's SDL Import command aids designers challenged with developing new design derivatives from existing SDL IP that requires targeting new PDKs and new schematics with the same circuit topology. This mini demo shows how easy it is to regenerate the design (placement and wiring) from an existing design while maintaining the device/P-cell placement locations and target a new PDK. The newly characterized schematic sizes are referenced in the newly-generated layout.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-SDLMigrate-July27.html
Mini Demo: Advances in Schematic Capture Featuring the Custom Designer Schematic Editor
Custom Designer SE’s schematic entry system enables designers to be more productive in meeting the design challenges of today’s complex circuits. This mini demo shows how, with little or no learning curve, all Custom Designer’s schematic editing tasks are accomplished with fewer clicks, quicker menu access and less pop-up menu clutter, thereby maximizing productivity.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-SchematicCap-July29.html
Mini Demo: Advanced SDL Cloning
Custom Designer’s SDL Auto Cloning feature provides designers with an intuitive schematic-to-layout cloning solution with high capacity and performance. This capability will clone both exact and inexact schematic device sizes. The innovative SDL cloning technology enables designers to layout repetitive circuitry much faster while maintaining full SDL compliance.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-SDLCloning-Aug23.html
Mini Demo: SDL Interdigitation
SDL interdigitation is an intuitive, simple approach to interdigitate devices for matching purposes while maintaining device-to-device connectivity from the schematic. The placement is row-based, and ABBA, AABB and ABAB patterns are supported. Dummy device insertion and cross-coupling of patterns are also supported.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-SDL-Interdigitation-Oct27.html
Mini Demo: Layout Commands - Part One
SmartDRD DRDAssist enables layout designers to perform DRC-correct layout tasks at zoomed-out “high altitude", greatly reducing the number of zooming-in and zooming-out iterations. DRDAssist ensures DRC correctness by keeping objects separated at the minimum design rule distance, in real time.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-LayoutCommand-Nov5.html
Mini Demo: Layout Commands – Part Two
Automated Via Generation helps layout designers accelerate the tedious and repetitive tasks of wire connecting, substrate contact insertion, and power and ground tapping. This mini demo illustrates 5 different modes of operation from Custom Designer’s Auto-Via command.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-LayoutCommand-part2-Jan27.html
Mini Demo: Productive DRC Debugging with IC Validator and Custom Designer
IC Validator's error classification capability provides layout designers and CAD engineers the ability to classify and comment individual DRC error markers according to their root cause. IC Validator runs can read these classified errors into a GUI, allowing users to track the previously-classified violations within the Custom Designer cockpit.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-icv-drc-Jan6.html
Mini Demo: Interactive Auto-Router
Custom Designer's Interactive Auto-Router is an innovative feature that improves single-net routing productivity. It comes in two modes of operation: Point-to-Point (P2P) and Follow-the-Cursor (FTC) routing. Both P2P and FTC will follow the preferred layer routing direction while routing nets LVS and DRC correct in real-time.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=cd-demo-interactive-auto-Mar11-11.html
CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS co-simulation solution, CustomExplorer Ultra aids engineers in rapidly performing customized advanced analyses for transistor-level analog, mixed-signal and SoC designs.
Demo
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http://www.synopsys.com/cgi-bin/cdmd/reg1.cgi?file=custom-explorer-demo-apr18.html
Synphony Model Compiler
Quickly create complex multi-rate algorithms that are synthesizable into optimized FPGA or ASIC implementations.
Demo
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http://www.synopsys.com/cgi-bin/sld/hlsdemos/reg1.cgi?file=hls-synpho-model-compiler-mar14.html
Introducing Galaxy Test 2010.12
Mona Marmash introduces the latest releases and new capabilities of DFTMAX compression and TetraMAX ATPG.
Mona, Marmash, Sr. Staff Support Center Engineer, Synopsys
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Synphony C Compiler
Overview of how to synthesize complex C/C++ algorithms into optimized RTL implementations.
Demo
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http://www.synopsys.com/cgi-bin/sld/hlsdemos/reg1.cgi?file=hls-synphoc-compiler-mar14.html
Faster Design Closure with PrimeTime AOCV
PrimeTime Advanced OCV, is a mature and proven technology in Static Timing Analysis to address the variation challenges in designs at 65nm or below process nodes.
Feroze Taraporevala, senior R&D manager, Implementation Group, Synopsys
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PrimeTime Scales Timing Analysis Beyond 500 Million Instances
PrimeTime HyperScale technology extends PrimeTime static timing analysis to support designs beyond 500 million instances. It delivers between 5 and 10X better runtimes for the full chip timing analysis and 5 to 10X smaller memory footprint compared with classic flat analysis.
Antun Domic, senior vice president and general manager, Implementation Group, Synopsys
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In-Design physical verification with IC Validator and IC Compiler delivers 100 tapeouts just one year after introduction.
In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.
Aart de Geus, Synopsys Chairman and CEO
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DC Explorer Demo
Early RTL exploration accelerates synthesis and place & route
Demo
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http://www.synopsys.com/apps/dcexplorer2011/dcexplorer-demo.html?cmp=DCExplorer-Demo-RTL-HL-Mar28
Lynx Design System Readiness for 28nm
Andy Potemski, Director, Global Technical Services, Synopsys, presents at the Common Platform Technology Forum.
Andy Potemski, Director, Global Technical Services, Synopsys
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http://synopsys1.http.internapcdn.net/synopsys1/lynx-cp-tech/main.htm
S2S Verification Overview Video
High-level overview of the Systems to Silicon Solution with David Park
David Park, Solutions Manager, Synopsys
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S2S Verification Video
Interview with Rajiv Maheshwary and Janick Bergeron
Janick Bergeron, Scientist, Synopsys, Inc.; Rajiv Maheshwary, Senior director, Synopsys, Inc.
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http://synopsys1.http.internapcdn.net/synopsys1/snps-journal-janickb/main.htm
Customer Highlight
ST meets AMS simulation criteria with VCS-MX and CustomSim
Yuval Shay, Staff Engineer, Mixed-Signal Verificatin
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http://synopsys1.http.internapcdn.net/synopsys1/dac10-verification-st/main.htm
Migrating a USB 2.0 design to USB 3.0 using Synopsys’ DesignWare SuperSpeed USB 3.0 IP and MCCI’s solution
In this video, you will discover how to quickly migrate an existing USB 2.0 design to USB 3.0. By leveraging Synopsys’ silicon-proven, complete DesignWare SuperSpeed USB 3.0 IP solution with MCCI’s software stack, you can lower integration risk and improve time-to-market of your next-generation USB 3.0 design.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI
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DC Explorer Video
Introducing DC Explorer
Antun Domic, General Manager, Implementation Group, Synopsys, Inc.
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DesignWare SuperSpeed USB 3.0 IP on a Synopsys HAPS-51 platform
In this video, you will see how the Synopsys DesignWare® SuperSpeed USB 3.0 controller and PHY IP enable faster performance speeds, reaching up to 335 MB/s. Using MCCI’s USB 3.0 software stack on a Synopsys HAPS platform, the DesignWare SuperSpeed USB 3.0 IP solution offers USB 3.0 speeds in both 2.0 and 3.0 modes.
Eric Huang Product Marketing Manager, USB Digital Controller and VIP
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An Introduction to the FPMM
The FPMM represents not only a collaborative work between Xilinx and Synopsys, but also decades of best-practices in prototyping, drawing upon the expertise of teams in leading semiconductor and application companies around the world. This video features two of the three authors of the FPMM: Doug Amos, Business Development Manager, Solutions Marketing, Synopsys, and Austin Lesea, Principal Engineer, Xilinx. Together, they share their insights on the history and impetus behind the development of the FPMM, and the benefits of prototyping.
Doug Amos, Business Development Manager, Solutions Marketing, Synopsys; Austin Lesea, Principal Engineer, Xilinx.
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Synopsys Demonstrates the Industry's First Silicon-Proven MIPI M-PHY
This video demonstrates the fully characterized, silicon-proven capabilities of the DesignWare MIPI M-PHY IP solution, highlighting its silicon performance as well as its electrical characteristics, which exceed target specifications.
Celio Albuquerque, R&D Manager, DesignWare MIPI PHY IP
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Modern Verification Challenges
In this short but insightful interview, Warren Stapleton, Senior Fellow at AMD, discusses the unique challenges of modern day verification, including the growing complexity of today’s microprocessors designs and what this means for verification engineers.
Warren Stapleton, Senior Fellow, AMD; Michael Sanie, Director of Marketing, Verification Group, Synopsys
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SNUG Preview Demo
Synopsys
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Understanding MIPI
This video provides a high level view of popular MIPI protocols and helps you get up to speed with latest mobile market innovations. We will also introduce IP solutions that can help you differentiate your products in the mobile market space.
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP
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Statistical Eye Diagram Analysis
This mini demo shows how the HSPICE statistical eye diagram feature can evaluate eye diagrams and bit error rate quickly and accurately. Statistical analysis setup, input syntax and outputs are demonstrated.
Synopsys Inc.
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http://www.synopsys.com/cgi-bin/hmd/reg1.cgi?file=hspice-stat-eyediagram-nov13.html
HSPICE Precision Parallel technology
This mini demo shows how HSPICE can improve analog designers’ productivity through superior performance and accuracy and tight integration with Galaxy Custom Designer.
Synopsys Inc.
/Community/PublishingImages/videoimages/images6851/HSPICEPrecision.jpg
http://www.synopsys.com/cgi-bin/hmd/reg1.cgi?file=hspice-precision-tech-nov13.html
Synopsys Demonstrates Silicon-Proven Implementation of DesignWare® Audio IP
See how Synopsys’ DesignWare Audio IP delivers superb audio quality, featuring a full set of audio functions needed by most of today’s consumer electronic devices. Synopsys also showcases the true Hi-Fi audio quality delivered by the DesignWare Audio Codec with dynamic range exceeding 96dB, while keeping the power consumption at minimum levels.
João Risques, Product Manager for DesignWare Audio and Video AFE IP, Synopsys
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Innovation Optimized! Video
ARM, Common Platform and Synopsys executives share their views on the recent collaboration announcement to deliver a technology enablement solution for the design and manufacture of 32nm mobile devices.
Dr. Aart de Geus, Chairman of the Board and CEO, Synopsys; Michael Cadigan, General Manager, Microelectronics Division, IBM Systems and Technology Group; Dr. C.S. Choi, Executive Vice President, LSI Division, Samsung Electronics; Chia Song Hwee, President and CEO, Chartered Semiconductor Manufacturing ; Warren East, Chief Executive Office, ARM Holdings
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http://www.commonplatform.com/newsroom/multimedia/dacvideo/
Introduction to Synthesis-Based Test
Watch this short video to learn about Synopsys’ Synthesis-Based Test technology and Test product portfolio.
Arif Samad, VP Engineering, Synopsys
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Explore R&D Engineering
Explore the life of an R&D engineer at Synopsys. Do you have a passion for software? Do you enjoy solving difficult problems? Find out what it takes to be an R&D Engineer at Synopsys.
Synopsys Inc.
/Community/PublishingImages/videoimages/images6851/Brent.jpg
http://www.monstervideoprofile.com/mvp/synopsys/rd
Explore Applications Engineering
Find out what it takes to be an Applications Engineer at Synopsys. If you enjoy working with customer and sharing in their success, this may be a position for you!
Synopsys Inc.
/Community/PublishingImages/videoimages/images6851/Pratima.jpg
http://www.monstervideoprofile.com/mvp/synopsys/ac
A Look Inside Synopsys
Take a look at what it is like to work at Synopsys, our work culture, values, global reach, employee impact and career opportunities.
Synopsys Inc.
/Community/PublishingImages/videoimages/images6851/Synopsys.jpg
http://www.monstervideoprofile.com/mvp/synopsys
VLSI Research: Synopsys’ new custom IC design suite
Finally . . . an integrated EDA tool for custom IC design. It’s a totally new, ground-up, software package. Yet, its user interface is so similar to what you’ve been using that you’ll be surprised as to how familiar it seems.
Ed Lechner
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http://vstream1.vlsiresearch.com/public/ed_lechner_080905/ed_lechner_index.htm
The Birth of the VMM-LP
In this video you will hear how the VMM-LP came to be and how it addresses the challenges of low power verification.
Srikanth Jadcherla, Group R&D Director in the Verification Group
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IC Compiler Customer Successes
In March 2009, SNUG (Synopsys User Group) San Jose drew a large crowd of Synopsys users who gathered to hear from others about their experiences presented in papers, tutorials, and panels. The videos below provide you with a brief overview from customers who presented at San Jose SNUG. Visit the SNUG website for a complete list of IC Compiler papers and presentations. This DAC 2008 event provided an opportunity for members of the electronic design community to learn more about customer design successes with IC Compiler. The event drew a capacity crowd as guest speakers from ARM, Intel, STMicroelectronics, Texas Instruments, and Toshiba shared their experiences from a variety of high-end designs utilizing the latest technology advances in IC Compiler: Concurrent Hierarchical Design, MinChip technology, DFM and IC Compiler’s new Zroute routing technology.
Philip Watson, Implementation Environment Program Manager; Raj Varada, Principal Engineer; Naveen Raina, Technical Specialist & Mutsunori Igarashi, Chief Specialist, Design Methodology Development.
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/Tools/Implementation/PhysicalImplementation/Pages/ICCompiler-Successes.aspx
Latest Features of PrimeTime
George Mekhtarian, Product Marketing Manager in Synopsys’ Implementation Group
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Power-Aware Test
Conventional compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop and overheating.
Tom Williams, Synopsys Fellow
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Eclypse Low Power Solution
Josefina Hobbs introduces the Eclypse Low Power Solution
Joselina Hobbs
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Expert Shootout: Parasitic Extraction
Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys
Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys
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http://chipdesignmag.com/lpd/blog/2010/02/11/the-ins-and-outs-of-parasitic-extraction/
DesignCon 2010: VCS Named DesignVision Award Finalist
Following the annoucement that VCS was honored as a finalist in the 2010 DesignVision Awards, Swami Venkat, Sr. Director of Verification Marketing at Synopsys, discusses the latest innovations within Synopsys' industry-leading functional verification solution at Designcon 2010.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys
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http://www10.edacafe.com/video/display_media.php?link_id_display=30345
An Introduction to The Lynx Design System
Neel Desai, Product Marketing Manager, provides an overview of this unique and comprehensive chip development platform.
Neel Desai, Product Marketing Manager
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http://www.webexlivestream.com/webx001/30112/
VMM User Forum Lunch Event: NVIDIA
Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering
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Tips for Getting the Best PrimeTime Performance
Few easy ways for getting the best PrimeTime performance and achieving faster sign-off analysis.
Karen Linser, staff applications engineer in Synopsys’ Implementation Group
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Small Delay Defects: The Need for Better At-Speed Tests
Manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures. Dr. T.W. Williams introduces technology developed at Synopsys to detect defects creating these delays, thereby increasing the test quality.
Tom Williams, Synopsys Fellow
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IC Compiler Lunch Event: ARM, Ltd.
ARM Cortex-A9 MPCore Multi-core Processor Hierarchical Implementation with IC Compiler Learn how ARM utilized IC Compiler’s concurrent hierarchical design for multi-core implementation, driving better performance as well as better throughput.
Philip Watson, Implementation Environment Program Manager
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IC Compiler Lunch Event: Toshiba Corp
Concurrent Hierarchical Design with IC Compiler, Real Life Application on Mobile Multi-Media Processor IC Compiler offers the industry’s first concurrent hierarchical design system that delivers a high degree of automation combined with high-quality optimization. Learn more about the results Toshiba achieved with the latest advances in IC Compiler.
Mutsunori Igarashi, Chief Specialist, Design Methodology Development
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Perspective: Boost your design productivity
Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule.
Antun Domic, senior vice president and general manager of Synopsys' Implementation Group
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DAC 2010 IC Compiler In-Design Videolog
At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics
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/Tools/Implementation/PhysicalImplementation/Pages/ICC-DAC10Lunch.aspx
In-Design Physical Verification Milestone
In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.
Dr. Aart de Geus, Synopsys Chairman and CEO
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Modern-era Custom Design
Tired of using two-generations-old EDA technology for your next-generation mixed-signal IC? Synopsys’ new custom design solution can quickly bring you into the modern era of custom chip design.
Joe Mastroianni, Synopsys VP of AMS R&D,
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VMM User Forum Lunch Event: ARM, Ltd.
Need for a Low Power Verification Methodology. Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead
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The Unique Challenge of Low Power Verification
With over 30 industry experts contributing to the book, the methodology documented in the VMM-LP is based on real-life design.
Janick Bergeron, Fellow in the Verification Group
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Accelerate Product Ramp with TetraMAX ATPG and Yield Explorer
Girish Patankar discusses diagnostics in TetraMAX ATPG, accuracy improvements with physical diagnostics, and how TetraMAX ATPG and Yield Explorer form a complete solution for volume diagnostics.
Girish Patankar, Sr. R&D Manager
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Synopsys and LeCroy Showcase PCI Express® 3.0 Interoperability at PCI-SIG 2010
This demonstration features LeCroy’s Summit T3-16 Protocol Analyzer, Summit Z3-16 Protocol Exerciser and the Summit Z3-16 Test Platform to test a PCI Express 3.0-based design for compliance to the PCI Express 3.0 specification. The design-under-test (DUT) utilizes the DesignWare® IP for PCI Express 3.0.
Featuring: John Wiedemeier, Product Manager, LeCroy; Scott Knowlton, Product Marketing Manager, Synopsys
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Synopsys and Agilent Enable PCI Express 3.0 Ecosystem at PCI-SIG 2010
Utilizing a DUT that implements the DesignWare IP for PCI Express 3.0, this demonstration features Agilent’s complete test solution for PCI Express 3.0 and the Digital Test Console to check for compliance to the PCI Express 3.0 specification.
Featuring: Yenyi Fu, Product Manager, Agilent; Scott Knowlton, Product Marketing Manager, Synopsys
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Optimized Implementation Methodology for High Performance Low Power Processor Cores at 40nm and Below
Both mobile and tethered devices require increased performance with decreased power consumption. In this tutorial, we present how the optimized methodology for processor cores at 40nm and below address these needs. This tutorial describes results using some of the latest DC Topographical and IC Compiler capabilities together with a highly tuned set of user constraints, delivering impressive performance results. Key techniques covered include: shorten wires for higher clock frequency, methodology to minimize congestion and best convergence with high utilization and high cell density, crosstalk prevention and fixing, clock tree synthesis constraints and methodology, leakage optimization, and signoff optimization. Target audience: Experienced physical designers.
Daniel Biset, Corporate Application Engineer - Synopsys, Inc.
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http://solvnet.synopsys.com/onlinetraining/SNUG_SJ2010_biset/index.html
DAC 2010: Galaxy Implementation Platform Overview
Steve Smith, Sr. Director of Marketing for the Galaxy Platform provides an overview of the many advancements made in the last year to Synopsys' comprehensive RTL-to-GDSII implementation solution, including a tighter connection between synthesis and place-and-route with physical guidance, new In-Design physical verification, enhanced signoff for large designs, improved multicore capabilities, the Lynx Design System and 28nm readiness.
Synopsys
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http://www10.edacafe.com/video/Synopsys-Galaxy-Implementation-Platform-Steve-Smith/32005/media.html
Lynx Design System @ DAC 2010
Neel talks about the Lynx Design System and recent updates since its introduction last year including recent customer successes. At DAC2010 we announced a new multi-year collaboration with ARM and the Common Platform alliance that optimizes the Lynx Design System and its Galaxy™ Implementation Platform-enabled flow for ARM's advanced physical IP and the ARM Cortex™ A9 MPCore processor.
Neel Desai, Product Marketing Manager
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Make it EASY with Synopsys DesignWare DDR HARD PHY IP
By using DDR Hard PHY IP, you achieve: quicker integration, easier timing closure, better performance and less silicon area. With a hard PHY, all the IP is supplied by one IP vendor and includes I/Os. Hard PHYs have lower jitter, better duty cycle, an overall superior clock strategy and use identical circuits for every bit of the parallel DDR interface reducing skew. In addition, hard PHYs implemented in test chips are equivalent to the customer's PHY where as soft PHYs are different GDSII every time.
Synopsys Super Stars
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DesignWare SuperSpeed USB 3.0 xHCI demo
See high-definition video using the DesignWare® SuperSpeed USB 3.0 xHCI Host and Device Controller implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video streaming from a standard PC running on a Linux operating system with a SuperSpeed USB 3.0 xHCI Host Stack, into mass storage device.
Eric Huang, Product Marketing Manager, USB Digital
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Design Compiler 2010 Video
Antun Domic, General Manager, Implementation Group, Synopsys, Inc
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Galaxy Test 2010.03 Introduction
Amy Mitby introduces the latest release and highlights four new powerful features
Amy Mitby, Sr. Test Applications Consultant
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Synopsys Demonstrates SuperSpeed USB 3.0 Interoperability
This demonstration shows proven interoperability of Synopsys' DesignWare USB 3.0 PHY with the DesignWare USB 3.0 host and device controllers implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Gervais Fong Product Marketing Manager, USB PHY IP
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DesignWare DDR3/2 IP Demo at 1600 Mbps
Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Graham Allan, Product Marketing Manager, Memory Interface IP; Vishal Thareja, Test Engineer
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Automotive
Join our FREE Robust Design Webcast Series to discover how Robust Design methodologies coupled with Synopsys Saber simulation and analysis solution can improve your design performance and reliability for Mechatronic Systems.
Mike Jensen, Coporate Applications Engineer, Saber product line, Synopsys Inc.
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http://www.synopsys.com/cgi-bin/saber/webinars/reg1.cgi
DisplayLink Streams Uncompressed HD 1080p Video Using Synopsys’ USB 3.0 IP
DisplayLink demonstrates how it uses DesignWare SuperSpeed USB 3.0 and HDMI IP to show full HD resolution over USB 3.0 by taking video directly out of USB 3.0 on the PC, convert it to HDMI and display it directly to a high-resolution monitor.
Gervais Fong, Product Marketing Manager, USB PHY IP Dennis Crespo, Vice President of Marketing, DisplayLink
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Silicon-proven DesignWare® HDMI TX Controller and PHY IP on Synopsys’ HAPS-51 Platform
Synopsys shows how fixed video and audio patterns are transmitted by the DesignWare HDMI TX controller and PHY. See the image quality improve as resolution of video test pattern is increased from 480p to 720p to 1080p, 60 Hz frame formats. Also see the EDID info collected by TX Controller/PHY Display Data Channel (DDC) from the sink device (DTV) to support negotiation and find the best supported color format and frame rate.
Manmeet Walia, Product Manager for Mixed-Signal PHY IP, Synopsys
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Pin-Limited Test
Current trends are accelerating the need for pin-limited test. Amy Mitby introduces capabilities in DFTMAX compression that allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins.
Amy Mitby, Sr. Test Applications Consultant
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Synopsys and MCCI SuperSpeed Media Player Demonstration
See Synopsys and MCCI demonstrate how music can be synchronized in a matter of seconds in a USB 3.0 media player compared to minutes in a USB 2.0 media player. The demonstration consists of the Synopsys DesignWare® SuperSpeed USB Digital Controller and MCCI SuperSpeed USB Software on an FPGA hardware platform.
Eric Huang Product Marketing Manager, USB Digital Controllers and VIP; Terry Moore CEO, MCCI
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TI Demonstrates USB 3.0 Interoperability at IDF with DesignWare IP
TI demonstrates SuperSpeed USB interoperability and USB 2.0 backward compatibility. The demo showcases TI's TUSB80x0 Hub and TUSB9260 SATA bridge controller with the Synopsys DesignWare SuperSpeed USB 3.0 IP
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI
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DesignWare IP for PCI Express 2.0 Complete Solution Demo
See a live demonstration of the 45-nm DesignWare PHY and controller IP for PCI Express® 2.0 operating in a single-lane configuration at 5 GT/s. The demonstration verifies 5 GT/s operation using the PCI® Tree software and executes Reads and Writes between the demo hardware and a PC to show throughput performance levels.
Scott Knowlton, Sr. Produt Marketing Manager, Synopsys
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See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device
See real SuperSpeed USB 3.0 data transfers of Synopsys' DesignWare® SuperSpeed USB 3.0 xHCI Host, Hub and Device digital controllers in a single demonstration. In this video, Synopsys shows interoperability between the DesignWare SuperSpeed USB 3.0 controllers and a USB 3.0 mass storage device, USB 2.0 flash controller and USB 1.1 mouse.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP
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See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution
See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution, consisting of digital controllers, mixed-signal PHY and Verification IP. This video consists of hardware demonstrations for the DesignWare SATA AHCI Host, Device, PHY and 6 Gb/s IP solutions.
Mat Loikkanen Sr. R&D Engineer, Synopsys; Mick Posner Sr. Product Marketing Manager, Synopsys
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IC Compiler In-Design Technology
At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics
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/Tools/Implementation/PhysicalImplementation/Pages/ICC-DAC10Lunch.aspx
PrimeTime SIG 2009
In July 2009, Synopsys hosted two PrimeTime SIG events in Bangalore, India and San Francisco, CA focused on STA performance and productivity, as well as new timing constraints management technology. Hear what experts from leading companies had to say about taking advantage of the latest PrimeTime features to boost productivity.
T.W. Williams, Synopsys Fellow; Jagan Ayyaswami, Principal Manager, Physical Design Group, Qualcomm; Rajagopal K.A., Technologist, Texas Instruments; Rich Laubhan, Manager of Design Integrity, LSI Corp.; Michio Komoda, Sr. Engineer, DFM & Digital EDA Technology Development, Renesas Corp.
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http://synopsys1.http.internapcdn.net/synopsys1/dac09ptsig/main.htm
How Does the VMM-LP Benefit the Industry?
Hear about some of the potential problems of low power verification and how the VMM-LP helps overcome them.
David Flynn, Fellow at ARM
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See Synopsys and Texas Instruments demonstrate SuperSpeed USB 3.0 Interoperability
Join us in the Synopsys lab to see proven interoperability between the Texas Instrument’s USB 3.0 transceiver and the Synopsys DesignWare USB 3.0 host and device controller implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP; Scott Kim, Business Development Manager, Connectivity Solutions, TI
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See Global Unichip’s SSD Demo Featuring DesignWare® SATA IP
See how Global Unichip (GUC) utilized Synopsys' silicon-proven DesignWare® SATA IP in its Solid State Device (SSD) GP5080 platform to demonstrate a netbook boot-up time of less than half a minute. The hardware platform consists of a high-performance 32-bit ARM7 processor, SATA 3Gb/s interface, SLC/MLC NAND Flash management of up to 4 channels, 8 banks with ECC.
Kurt Huang, Director of Marketing, Global Unichip Corp.
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See an actual USB 3.0 data transfer utilizing the DesignWare SuperSpeed USB Host and Device Controllers implemented in an FPGA
Join Synopsys in our lab to see actual USB 3.0 data transfer utilizing the DesignWare Superspeed USB Host and Device Controllers implemented in an FPGA. This demonstration shows a 1080p, 30 frames per second video, streaming from the device into the host with a measured throughput of 460 MB/s utilizing the Lecroy CATC analyzer.
Eric Huang, Product Marketing Manager, USB Digital Controllers and VIP
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SNUG San Jose Keynote
Aart de Geus, Synopsys CEO, delivers the opening keynote address at SNUG San Jose 2008.
Aart de Geus, Synopsys CEO
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Mike Keating: The Future of Low Power 2008
Mike Keating, Synopsys Fellow, presents a 2008 update to last year's popular SNUG presentation. This talk consists of a leisurely walk through the power management spectrum, with digressions into various interesting side-issues.
Mike Keating
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Perspective: How to Improve Design TTR
John Chilton, senior vice president of Marketing and Business Development at Synopsys, talks about the importance of utilizing today’s widely-available multi-core processor-based compute infrastructures to accelerate design TTR.
John Chilton, senior vice president of Marketing and Business Development at Synopsys
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10X Faster Routing Runtime
Combine advanced routing algorithms with multi-threading technology, and you get a speed increase of >10X on quad-core machines.
Tong Gao, Synopsys Scientist and architect of Zroute,
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VMM User Forum Lunch Event: IBM
"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead
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VMM User Forum Lunch Event: Renesas Technology Corporation
Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer
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IC Compiler Lunch Event: Intel Corp.
IC Compiler: Routing and Design for Manufacturability (DFM) IC Compiler uses concurrent optimization techniques to simultaneously consider the impact of manufacturing rules, timing, and other design goals for high QoR and improved manufacturability.
Raj Varada, Principal Engineer
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IC Compiler Lunch Event: STMicroelectronics
Automatic Block Size Reduction with IC Compiler MinChip Technology IC Compiler reduces runtime and memory while delivering hand-craft-quality macro placement, MinChip die size reduction, clock tree synthesis, skew optimization, clock-gate merging, and more. STMicroelectronics achieved a huge reduction in die-size with a runtime of only 4 to 6 hours!
Naveen Raina, Technical Specialist
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Perspective: SDD Test to the Rescue
Carl Holzwarth, director of Test R&D
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See how we verify the DesignWare IP for DDR2/3 PHY and Controllers
See firsthand the test equipment and custom boards developed and used by Synopsys to verify our DDR IP. Witness full speed write and read data eyes, at speed functionality testing, duty cycle and phase error tests and jitter analysis results.
Graham Allan, Product Marketing Manager, DDR IP
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Godwin Maben: Low Power Trends and Methodology
Godwin Maben
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Join us in the Synopsys lab to see how we verify the DesignWare USB 2.0 NanoPHY IP
The video will take you through our silicon verification board set up, show the unique tunability feature and highlight the extensive characterization process of the USB 2.0 nanoPHY.
Gervais Fong, Product Marketing Manager, USB PHY IP
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See a silicon demo of the DesignWare PHY for PCI Express 2.0
Join Synopsys in our lab to see how we deliver a compliant, robust PCI Express 2.0 PHY and enable visibility into the link performance through unique on-chip diagnostics.
Navraj Nandra, Marketing Director MSIP
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Unifying or Overrated: A System Level Design Strategy
Joachim Kunkel, VP and GM of the Synopsys Solutions Group discusses trends and best practices regarding the development of a system-level design strategy.
Joachim Kunkel
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http://www.iet.tv/dpx_iet_techelx/dpx.php?dpxuser=dpx_iet_techelx&cmd=autoplay&pres=1156&type=solo
SNUG Boston 2008: Galaxy Custom Designer Launch
On September 22 at SNUG Boston 2008, Synopsys unveiled Galaxy Custom Designer™, the modern-era custom AMS implementation solution. On hand to support the launch were representatives from Cray and Priva Technologies who presented their experiences using/supporting Custom Designer.
Aart de Geus, CEO, Synopsys, Inc.; Tom Quan, Design Methodology & Service Marketing; Matt Priest, Hardware Engineer; Jeff Berkman, CTO
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/Tools/Implementation/CustomImplementation/Pages/BostonSNUG08Videos.aspx
FPGA prototyping gains ground
At the Design Automation Conference (DAC) in Anaheim, Calif., Mark LaPedus, semiconductor editor from EE Times, caught up with Andy Haines, vice president of marketing of Synplicity, which was recently acquired by Synopsys. In a video, Smith, Haines discusses the growing importance of FPGA prototyping.
Mark LaPedus and Andy Haines
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http://www.eetimes.com/news/design/showArticle.jhtml?articleID=208403774
Design and Verification of Ultra Low Power SoCs with ARM Cores
This presentation describes the common challenges and solutions in the design and verification of SoCs striving for power and performance efficiency. In particular, we discuss how ARM's IEM technology can control power and performance, focusing on the integration of ARM cores, IEM technology, and the process of architecting and verifying a low power scheme using these components. We also provide guidance in the hardware and software partitioning of low power schemes.
Srikanth Jadcherla, Group Director of R&D, Synopsys -- Prapanna Tiwari, Manager, Corporate Applications Engineer, Synopsys
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Why buy IP from an IP supplier with lots of customers? 01:30
Synopsys Demonstrates DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair 05:21
Synopsys Demonstrates MIPI Camera and Display Prototyping System 03:34
MCCI USB 3.0 Software on Synopsys' HAPS with DesignWare SuperSpeed USB 3.0 Cores & PHYs 04:21
Meet the Prototypers - Introducing the FPMM 49:53
IC Validator 06:47
DisplayLink Demonstrates Video Streaming with Synopsys’ DesignWare® SuperSpeed USB 3.0 and HDMI IP 02:44
DisplayLink Explains Video Compression Over USB 3.0 02:12
Implementing a Audio Video Bridge with DesignWare Ethernet QoS
Mini Demo: SmartDRD Technology 05:33
Mini Demo: High-performance Bus Editing with Bridge and Tunnel 05:43
Mini Demo: SDL Migrate Featuring the SDL Import Command 05:16
Mini Demo: Advances in Schematic Capture Featuring the Custom Designer Schematic Editor 09:20
Mini Demo: Advanced SDL Cloning 05:03
Mini Demo: SDL Interdigitation 06:34
Mini Demo: Layout Commands - Part One 06:54