Newsletter 

September 2011 Monthly Update 
Video Presentation

Litho Process Corner Identification using Test Structures
Dr. Sandip Kundu, University of Massachusetts, Amherst

Lithographic process variations, such as changes in focus, exposure, resist thickness introduce distortions to line shapes on a wafer. Large distortions may lead to line open and bridge faults. Locations of such defects vary with lithographic process corner. Based on lithographic simulation, it is easily verified that for a given layout, changing one or more of the process parameters shifts the defect location. Thus, if the lithographic process corner of a die is known, test patterns can be better targeted for both hard and parametric defects. In this talk, we will present design of control structures such that preliminary testing of these structures can uniquely identify the manufacturing process corner. If the manufacturing process corner is known, we can easily attain highest possible fault coverage for lithography related defects during manufacturing test. Parametric defects such as delay defects are notorious to test because such defects may affect paths that are subcritical under nominal conditions and not ordinarily targeted for test. Adoption of the proposed approach can easily flag such paths for delay tests.


Curriculum

The following new and updated courses are now available. Visit Members Only with your SolvNet ID and password to download.

90nm Digital Design Workshop - Updated!
Modeling and Optimization of VLSI Interconnects- Updated!
Probability Theory and Mathematical Statistics - Updated!
Solar Cell Physics - New!
Sequential Elements - New!


Articles

Advanced Simulations of an MTJ based Magnetoresistive Random Access Memory (MRAM) Cell for Low Power Cell Applications
Mayank Chakraverty, Arun Kumar & Harish M. Kittur


Comparison of Performance Parameters of SRAM Designs in 16nm CMOS and CNTFET Technologies
Anuj Pushkama, Sajna Raghavan & Hamid Mahmoodi


Thermal Estimation for Accurate Estimation of Impact of BTI Aging Effects on Nano-Scale SRAM Circuits
Ankitchandra Shah & Hamid Mahmoodi


Analysis of SRAM Reliability under Combined Effect of NBTI, Process and Temperature Variations in Nano-Scale SMOS
Harwinder Singh & Hamid Mahmoodi


Events

S4D 2011 (System, Software, SoC and Silicon Debug Conference)
October 5-6, 2011
Munich, Germany

ISETC 2011 (International Solar Energy Technology Conference)
October 27, 2011
Santa Clara, CA

ISOCC 2011 (International SoC Design Conference)
November 17-18, 2011
Jeju, Korea

IP-SOC 2011 (IP-Embedded System Conference and Exhibition)
December 7-8, 2011
Grenoble, France

ISDRS 2011 (International Semiconductor Device Research Symposium
December 7-9, 2011
College Park, Maryland


Call for Papers

ISPD 2011
Due By: October 2, 2011

ASEE 2011
Due By: October 7, 2011

ISCAS 2011
Due By: October 7, 2011

IEDEC 2011
Due By: October 12, 2011

EWME 2012
Due By: January 15, 2012


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