November 2013 Monthly Update 

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DesignWare ARC 600 Academic Core & Curriculum – Download Them Today!

Are you creating designs optimized for embedded applications and DSP tasks where high performance and low power consumption is required? If so the “IC Synthesis Based on DesignWare ARC 600 Core” short course is for you. This course covers the digital design flow steps and use of the DesignWare ARC 600 Academic Core. It includes details of integrating the ARC processor into a full chip, preparation of required RTL descriptions, library and Synopsys EDA tools setup. The course contains lectures and lab works for design implementation and verification of an ARC processor core together with the Synopsys 32/28nm Generic Library. Download the course and the core today!

Latin American Symposium on Circuits and Systems (LASCAS) 2014
Call for Papers Extended to November 15, 2013
February 25-28, 2014 - Santiago, Chile

Call for Papers Extended to November 15, 2013
February 25-28, 2014 - Santiago, Chile

For more information or to submit a paper for either of these events visit:


The following new and updated courses are now available. Visit Members Only with your SolvNet ID and password to download.

Featured Conversation Central Show

Conversation Central Sheela Pillai
A Chip in Your Brain?
Jan Rabaey
Donald O. Pederson Distinguished Professor, UC Berkeley

UC Berkeley Professor, Jan Rabaey, talks about a fascinating technology that he is developing, one that will significantly change health, medicine and technology. Professor Rabaey discusses the idea of placing microchips in people’s brains. Only being tested on animals currently, this use of a microchip is hoped to help in various brain degeneration problems, which could potentially include ALS disease and epilepsy.

Find similar podcasts by visiting the Education category on the show website


University of Computing with Novel Floating-Gate Devices
North Carolina State University: Daniel Schinke, Neil Di Spigna, Mihir Shiveshwarkar, Paul Franzon
 UniversityMixed-Mode Simulation of Nanowire Ge/GaAs Heterojunction Tunneling Field-Effect Transistor for Circuit Applications
Seoul National University: Various Authors
Universidad Validation of Channel Decoding ASIPs - A Case Study
University of Kaiserslautern: Christian Brehm, Norbert Wehn, Sacha Loitz, Wolfgang Kunz
 Atomistic Simulation of Phonon-Assisted Tunneling in Bulk-like Esaki Diodes
ETH Zurich: Reto Rhyner, Mathieu Luisier, Andreas Schenk

Upcoming Events

ReConFigurable Computing 2013International Conference on Sustainability, Technology and Education
November 29 - December 1, 2013
Kuala Lumpur, Malaysia
ReConFigurable Computing 2013ReConFigurable Computing 2013
December 9 - 11, 2013
Cancun, Mexico
International Conference on Electronics, Circuits & SystemsInternational Conference on Electronics, Circuits & Systems
November 6 - 7, 2013
Grenoble, France

Call for Papers