Articles 

Synopsys Tools Fuel Advances in Green Electronics 
Various Authors
Purdue University

Purdue professors report that Synopsys tools have facilitated the design of energy efficient electronic devices both for high voltage power switching electronics and for low power DSP applications.

At the December 2009 IEEE Electron Devices Meeting (IEDM) Prof. James Cooper and co-authors presented a theoretical framework and experimental results for the comparison and optimization of silicon carbide (SiC) semiconductors for high voltage power switching applications. SiC devices have a much higher tolerance for high electric fields than silicon, thus permitting the creation of higher performance and higher efficiency power electronics. However, SiC devices have previously been difficult to optimize and evaluate for particular applications. Through the use of the Medici ™ device simulation tool, researchers were able to optimize the blocking voltage for a variety of SiC devices including MOSFETs, IGBTs, and Thyristors, and then assess the switching characteristics of each. These results will help power electronics designers to design more efficient high performance electric power control systems than previously possible [7]. Prior work on SiC devices, also using Medici, has been reported in IEEE Transactions on Electron Devices [8-11].

In August 2009, a team led by Prof. Kaushik Roy reported results in IEEE Transactions on CAD [22] that demonstrate the use of graceful degradation techniques to achieve substantially greater power savings in DSP applications than would otherwise be possible. In the cited paper, researchers were able to achieve a power savings of 40% on a reference design for color-interpolation filtering of image data while allowing for extreme process variations. By analyzing the sensitivity of peak signal to noise ratio (SNR) of individual calculations, they were able to design the system to allow errors to occur in the least sensitive calculations. In the presence of reduced voltages and slow process parametric delay, the design could still meet throughput requirements and achieve an acceptable SNR. Design Compiler™ was used to produce the gate level design and HSPICE™ was used to evaluate the power consumption and performance of the design. Similar techniques have been used by these researchers to evaluate the use of graceful degradation techniques for a variety of other DSP applications [20, 21, 37].

In addition to work energy efficient devices, Purdue researchers continue to use Synopsys tools to advance research in a variety of fields including nanoscale device modeling [1-5, 14, 31, 40-46], bio-sensors [6, 12], interconnect optimization [13, 15], yield improvement of SRAM designs [23, 25, 27], SOC test/verification [16-18, 26, 33], and SOC architectural and circuit optimizations [19, 24, 28-30, 34-36, 38, 39].

References

1. Theory of Breakdown Position Determination by Voltage- and Current-Ratio Methods,
Alam, M.A.; Varghese, D.; Kaczer, B., Electron Devices, IEEE Transactions on, Nov. 2008.

2. A comprehensive analysis of off-state stress in drain extended PMOS transistors: Theory and characterization of parametric degradation and dielectric failure,
Varghese, D.; Reddy, V.; Shichijo, H.; Mosher, D.; Krishnan, S.; Alam, M.A., Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, Dec. 2008.

3. Multi-probe interface characterization of In0.65Ga0.35As/Al2O3 MOSFET,
Varghese, D.; Xuan, Y.; Wu, Y.Q.; Shen, T.; Ye, P.D.; Alam, M.A., Electron Devices Meeting, 2008. IEDM 2008. IEEE International, Dec. 2008.

4. Physics and mechanisms of dielectric trap profiling by Multi-frequency Charge Pumping (MFCP) method,
Masuduzzaman, M.; Islam, A.E.; Alam, M.A., Reliability Physics Symposium, 2009 IEEE International, Dec. 2009.

5. Bipolar Mode Operation and Scalability of Double-Gate Capacitorless 1T-DRAM Cells,
Giusi, G.; Alam, M. A.; Crupi, F.; Pierro, S., Electron Devices, IEEE Transactions on, Accepted for publication, 2010.

6. Electrical detection of the biological interaction of a charged peptide via gallium arsenide junction-field-effect transistors,
Lee, K.; Nair, P. R.; Alam, M. A.; Janes, D. B.; Wampler, H. P.; Zemlyanov, D. Y.; Ivanisevic, A., Journal of Applied Physics, June 2008.

7. Optimization of on-State and Switching Performances for 15–20-kV 4H-SiC IGBTs,
Tamaki, T.; Walden, G.G.; Yang Sui; Cooper, J.A., Electron Devices, IEEE Transactions on, Aug. 2008.

8. Demonstration and Characterization of Bipolar Monolithic Integrated Circuits in 4H-SiC,
Lee, J.Y.; Singh, S.; Cooper, J.A., Electron Devices, IEEE Transactions on, Aug. 2008.

9. Numerical Study of the Turnoff Behavior of High-Voltage 4H-SiC IGBTs,
Tamaki, T.; Walden, G.G.; Yang Sui; Cooper, J.A., Electron Devices, IEEE Transactions on, Aug. 2008.

10. Power MOSFETs, IGBTs, and Thyristors in SiC: Optimization, Experimental Results, and Theoretical Performance,
Cooper, J.A.; Tamaki, T.; Walden, G.G.; Sui, Y.; Wang, S.R.; Wang, X., Electron Devices Meeting (IEDM), 2009 IEEE International, Dec. 2009.

11. High-Voltage n-Channel IGBTs on Free-Standing 4H-SiC Epilayers,
Wang X.; Cooper, J.A., Electron Devices, IEEE Transactions on, Feb. 2010.

12. Device considerations for development of conductance-based biosensors,
Lee, K.; Nair, P. R.; Scott, A.; Alam, M. A.; Janes, D. B., Journal of Applied Physics, May 2009.

13. A Fast Band Matching Technique for Impedance Extraction,
Jain, J.; Li, H.; Koh, C.K.; Balakrishnan, V., Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, May 2008.

14. Modeling of Nanoscale Devices,
Anantram, M.P.; Lundstrom, M.S.; Nikonov, D.E., Proceedings of the IEEE, Sep. 2008.

15. Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication,
Sekar, K.; Lahiri, K.; Raghunathan, A.; Dey, S., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Oct. 2008.

16. Tutorial: SoC Power Management Verification and Testing Issues,
Kapoor, B.; Edwards, J.M.; Hemmady, S.; Verma, S.; Roy, K., Ninth International Workshop on Microprocessor Test and Verification, Dec. 2008.

17. Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique,
Bhunia, S.; Mahmoodi, H.; Raychowdhury, A.; Roy, K., Journal of Electronic Testing, Dec. 2008.

18. Impact of SoC power management techniques on verification and testing,
Kapoor, B.; Hemmady, S.; Verma, S.; Roy, K.; D'Abreu, M.A., Quality of Electronic Design, 2009. ISQED 2009, Mar. 2009.

19. Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering,
Wang, Y.; Mahmoodi, H.; Chiou L.Y.; Choo, H.; Park, J.; Jeong, W.; Roy, K., Journal of Signal Processing Systems, Feb. 2010.

20. Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and its Application to Digital Signal Processing Systems,
Banerjee, N.; Augustine, C.; Roy, K., IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, Oct. 2008.

21. Significance Driven Computation: A Voltage-Scalable, Variation-Aware, Quality-Tuning Motion Estimator,
Mohapatra, D.; Karakonstantis, G.; Roy, K., Proceedings of International Symposium on Low Power Electronics and Design, 2009, Feb. 2009.

22. Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering,
Banerjee, N.; Karakonstantis, G.; Choi, J. H.; Chakrabarti, C.; Roy, K., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Aug. 2009.

23. Nano-scaled SRAM Thermal Stability Analysis Using Hierarchical Compact Thermal Models,
Kulkarni, J.; Meterelliyoz, M.; Roy, K.; Murthy, J., Thermal and Thermomechanical Phenomena in Electronic Systems, 2008, May 2008.

24. Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput,
Ndai, P.; Bhunia, S.; Agarwal, A.; Roy, K., IEEE Transactions on Computers, July 2008.

25. A 135mV 0.13μW Process Tolerant 6T Subthreshold DTMOS SRAM in 90nm Technology,
Hwang, M-E; Roy, K., Custom Integrated Circuits Conference, 2008, Sep. 2008.

26. Design for Burn-In Test: A Technique for Burn-In Thermal Stability Under Die-to-Die Parameter Variations,
Meterelliyoz, M.; Roy, K., Design Automation Conference, 2009. ASP-DAC 2009, Jan. 2009.

27. REad/Access-Preferred (REAP) SRAM – Architecture-Aware Bit Cell Design for Improved Yield and Lower VMIN,
Goel, A.; Ndai, P.; Kulkarni, J.; Roy, K., Custom Integrated Circuits Conference, 2009, Sep. 2009.

28. Reliability Implications of Bias Temperature Instability in Digital ICs,
Park S.P.; Kang, K.; Roy, K., IEEE Design and Test of Computers, Nov. 2009.

29. Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths,
Ndai, P.; Rafique, N.; Thottethodi, M.; Ghosh, Swaroop; Bhunia, S.; Roy, K., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Jan. 2010.

30. Efficient Power Conversion for Ultra Low Voltage Micro Scale Energy Transducers,
Lu, C.; Park, S.P.; Raghunathan, V.; Roy, K., Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, Mar. 2010.

31. PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices,
Augustine, C.; Raychowdhury, A.; Yunfei Gao; Lundstrom, M.; Roy, K., Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, Mar. 2009.

32. Profit Aware Circuit Design Under Process Variations Considering Speed Binning,
Datta, A.; Bhunia, S.; Jung Hwan Choi; Mukhopadhyay, S.; Roy, K., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, July 2008.

33. Timed input pattern generation for an accurate delay calculation under multiple input switching,
Choi, S.H.; Kang, K.; Dartu, F.; Roy, K., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Mar. 2010.

34. A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption,
Park, J.; Roy, K., Journal of Signal Processing Systems, Dec. 2008.

35. Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters,
Choi, J.H.; Banerjee, N.; Roy, K., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Dec. 2008.

36. Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance,
Chen, Y.; Li, H.; Koh, C.-K.; Sun, G.; Li, J.; Xie, Y.; Roy, K., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Aug. 2009.

37. System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning,
Karakonstantis, G.; Mohapatra, D.; Roy, K., Signal Processing Systems, 2009. SiPS 2009. IEEE Workshop on, Nov. 2009.

38. Improved clock-gating control scheme for transparent pipeline,
Jung H.C.; Kim, B.G.; Dasgupta, A.; Roy, K., Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, Feb. 2010.

39. Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking,
Ghosh, S.; Mohapatra, D.; Karakonstantis, G.; Roy, K., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Accepted for publication, 2009.

40. Optimal Dual-VT Design in Sub-100-nm PD/SOI and Double-Gate Technologies,
Bansal, A.; Kim, J-J; Kim, K.; Mukhopadhyay S.; Chuang, C-T; Roy, K., Electron Devices, IEEE Transactions on, May 2008.

41. Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications,
Li, J.; Kang, K.; Roy, K., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Jan. 2009.

42. Device/circuit interactions at 22nm technology node,
Roy, K.; Kulkarni, J.P.; Gupta, S.K., Design Automation Conference, 2009. DAC '09. 46th, July 2009.

43. Metal-oxide-semiconductor field-effect transistors on GaAs (111) A surface with atomic-layer-deposited Al2O3 as gate dielectrics,
Xu, M.; Wu, Y. Q.; Koybasi, O.; Shen, T.; Ye, P. D., Applied Physics Letters, May 2009.

44. New insight into Fermi-level unpinning on GaAs: Impact of different surface orientations,
Xu, M.; Xu, K.; Contreras, R.; Milojevic, M.; Shen, T.; Koybasi, O.; Wu, Y.Q.; Wallace, R.M.; Ye, P.D., Electron Devices Meeting (IEDM), 2009 IEEE International, Dec. 2009.

45. Two-Dimensional Tunneling Effects on the Leakage Current of MOSFETs With Single Dielectric and High-K Gate Stacks,
Luisier, M.; Schenk, A., Electron Devices, IEEE Transactions on, June 2008.

46. 2D simulation of gate currents in MOSFETs: Comparison between S-Device and the quantum mechanical simulator GreenSolver,
Schenk, A.; Luisier, M.M., Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on, Sep. 2008.


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