Researchers at IIT Bombay have used Synopsys tools to facilitate research in Nanoelectronics, leading to publications in reputed international journals and conferences in recent years. The following areas are under active investigation:

• Study of Tunnel FETs using Sentaurus Medici.
• Study of FinFETs (underlap FinFETs, Bulk FinFETs, IDDG FinFETs) using SProcess and SDevice.
• Study of Novel devices for ESD protection, Device failure analysis using Monte Carlo simulation in Sentaurus.
• Study of SONOS Flash using Sentaurus TCAD.
• Study of organic semiconductor using Sentaurus TCAD.
• Study of Novel Si/SiGe Hetero structure using SProcess and SDevice.
• I/O device optimization for sub 32nm node CMOS technology using SProcess and SDevice.
• Study of compound semiconductors using SProcess and SDevice.
• Variability aware design using SProcess and SDevice.

2009

A CAD-Compatible Closed-form Approximation for the Inversion Charge Areal Density in Double-Gate MOSFETs
Venkatnarayan Hariharan, Juzer Vasi and V. Ramgopal Rao, Solid State Electronics (Elsevier), Vol 53, issue 2, pp. 218-224, Feb 2009.

A New Physical Insight and 3D Device Modeling of STI Type DENMOS Device Failure under ESD Conditions
Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, Accepted, 2009 IEEE International Reliability Physics Symposium (IRPS), April 26 - 30, 2009, Montreal, Quebec, Canada.

A Novel Table Based Approach for Design of FinFET Circuits
R. A. Thakker, C. Sathe, A. B. Sachid, M. S. Baghini, V. Ramgopal Rao, M. B. Patil, IEEE Transactions on CAD, pp. 1061-1070, July 2009.

An Improvement to the Numerical Robustness of the Surface Potential Approximation for Double-Gate MOSFETs
Venkatnarayan Hariharan, Juzer Vasi and V. Ramgopal Rao, IEEE Transactions on Electron Devices, Vol. 56, No.3, pp. 529-532, March 2009.

Automated Design and Optimization of Circuits in Emerging Technologies
Rajesh A. Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil, Proceedings of the 14th Asia and South Pacific Design Automation Conference” (ASP-DAC 2009), Jan. 19-22 2009, Yokohama, Japan.

DC & Transient Circuit Simulation Methodologies for Organic Electronics
Ramesh R. Navan, Rajesh A. Thakker, S. P. Tiwari, M. Shojaei Baghini, M. B. Patil, S. G. Mhaisalkar, and V. Ramgopal Rao, Accepted, IEEE International Workshop on Electron Devices & Semiconductor Technology, June 1-2, 2009, Mumbai, India.

Drain Current Model for Nanoscale Double-Gate MOSFETs
V. Hariharan, R. Thakker, K. Singh, A. B. Sachid, M. B. Patil, J. Vasi and V. Ramgopal Rao, To appear in Solid State Electronics (Elsevier), 2009.

Highly resistive body STI: n-DEMOS: An optimized DEMOS device to achieve moving current filaments for robust ESD protection
Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, Accepted, 2009 IEEE International Reliability Physics Symposium (IRPS), April 26 - 30, 2009, Montreal, Quebec, Canada.

Highly Robust Nanoscale Planar Double-Gate MOSFET Device and SRAM Cell Immune to Gate-Misalignment and Process Variations
Angada B. Sachid, Giri S. Kulkarni, Maryam S. Baghini, Dinesh K. Sharma, V. Ramgopal Rao, Accepted, IEEE International Workshop on Electron Devices & Semiconductor Technology, June 1-2, 2009, Mumbai, India.

IGBT Plugged in SCR Device for ESD Protection in Advanced CMOS Technology
Mayank Shrivastava, Jens Schneider, Ruchil Jain, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, 31st IEEE Annual International EOS/ESD Symposium, August 30-September 4, 2009, Anaheim, CA, USA.

Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs
Hasanali G. Virani, Rama Bhadra Rao, Vishwanath Nikam and Anil Kottantharayil, submitted to the 39th European Solid State Device Research Conference (ESSDERC 2009).

Optimization of Hetero Junction n-channel Tunnel FET with High-k Spacers
Hasanali G. Virani and Anil Kottantharayil, accepted for the 2nd International Workshop on Electron Devices and Semiconductor Technology (IEDST 2009).

Optimum Body Bias Constraints for Leakage Reduction in High–K CMOS Circuits
Pradeep Kumar Chawda, Bulusu Anand, and V. Ramgopal Rao, Japanese Journal of Applied Physics, May 2009.

Understanding and Optimization of Hot Carrier Reliability in Germanium-on-Silicon pMOSFETs
D. Maji, F. Crupi, E. Amat, E. Simoen, B. De Jaeger, D. P. Brunco, C. R. Manoj, V. Ramgopal Rao, P. Magnone, G. Giusi, C. Pace, L. Pantisano, J. Mitard, R. Rodriguez, M. Nafrìa, IEEE Transactions on Electron Devices, Vol. 56, No. 5, pp. 1063-1069, May 2009.

2008

A Novel and Robust Approach for Common Mode Feedback using IDDG FinFET
Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, IEEE Transactions on Electron Devices, Vol. 55, No 11, pp 3274-3282, November 2008.

Analysis of Threshold Voltage Variations of FinFETs Relating to Short Channel Effects
Y. Kobayashi, A. B. Sachid, K. Tsutsui, K. Kakushima, P. Ahmet, V. Ramgopal Rao and H. Iwai, Accepted, 214 the Meeting of The Electrochemical Society, October 12-17, 2008, Hawaii, USA.

Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field-dependent Mobility and Body Doping
V. Hariharan, R. Thakker, M. B. Patil, J. Vasi and V. Ramgopal Rao, Accepted, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A.

Device Design & Optimization Considerations for Bulk FinFETs
C. R. Manoj, Meenakshi N, Dhanya V. and V. Ramgopal Rao, IEEE Transactions on Electron Devices, Vol. 55, No.2, pp. 609-615, February 2008.

Drain Current Model Including Velocity Saturation for Symmetric Double-Gate MOSFETs
Venkatnarayan Hariharan, Juzer Vasi, V. Ramgopal Rao, IEEE Transactions on Electron Devices, Volume 55, Issue 8, Page(s):2173 - 2180, Aug. 2008.

Gate Fringe Induced Barrier Lowering in Underlap FinFET Structures and its Optimization
Angada B. Sachid, Manoj C. R., Dinesh K. Sharma, V. Ramgopal Rao, IEEE Electron Device Letters, Vol. 29, Issue 1, pp.128-130, January 2008.

Optimization of n-channel tunnel FET for the sub-22nm gate length regime
Viswanath Nikam, Krishna Bhuwalka and Anil Kottantharayil, accepted for presentation at Device Research Conference, UCSB, CA, June 23-25, 2008.

Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?
Angada B. Sachid, Roswald Francis, M. S. Baghini, D.K. Sharma, Karl-Heinz Bach, R. Mahnkopf, V. Ramgopal Rao, Proceedings of the International Electron Devices Meeting (IEDM), San Francisco, CA, December 15-17, 2008.

Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies
A. B. Sachid, M. Srivastava, R. A. Thakker, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, Intel Asia Academic Forum 2008, 20-22 Oct 2008, Taipei, Taiwan.

2007

Circuit Performance Improvement Using PDSOI DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics
Bulusu Anand, V. Ramgopal Rao, M. P. Desai, Proceedings of the 2007 International Symposium on VLSI Design, Automation & Test (VLSI-DAT) Hsinchu, Taiwan, April 25-27, 2007.

Development of a 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation
A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, presented, International Electron Devices Meeting (IEDM), Washington DC, USA, Dec 2007.

Device optimization of bulk FinFETs and its comparison with SOI FinFETs
C.R. Manoj, Meenakshi. N, Dhanya V. and V. Ramgopal Rao, Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, Mumbai, December 16-20, 2007.

Drain Current Model for Undoped Symmetric Double-Gate FETs using a Velocity Saturation Model with Exponent n=2
V. Hariharan, Juzer Vasi, and V. Ramgopal Rao, Proceedings of the 2007 International Semiconductor Device Research Symposium (ISDRS), Dec 12-14, 2007,Universit of Maryland, College Park, USA.

Dual-bit/Cell SONOS Flash EEPROMs: Impact of Channel Engineering on Programming Speed and Bit Coupling Effect
Datta, P. Bharath Kumar and S. Mahapatra, IEEE Electron Dev. Lett., p.446, v.28, 2007.

Improving the DC performance of Bulk FinFETs by Optimum Body Doping
C. R. Manoj, N. Meenekshi, V. Ramgopal Rao, Proceedings of the 14th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 11-13 July 2007, Bangalore, India.

Investigation of drain disturb in SONOS Flash EEPROMs
P. Bharath Kumar, R. Sharma, P. R. Nair and S. Mahapatra, IEEE Trans. Electron Devices, v.54, p.98, 2007.

Parasitic Effects Depending on Shape of Spacer Region on FinFETs
Y. Kobayashi, K. Tsutsui, K. Kakushima, V. Hariharan, V. Ramgopal Rao, P. Ahmet and H. Iwai, Proceedings of the 211th Meeting of the Electrochemical Society, Hilton Chicago, Chicago, Illinois, May 6-10, 2007.

Parasitic effects in multi-gate MOSFETs
Yusuke Kobayashi, C. Raghunathan Manoj, Kazuo Tsutsui, Venkanarayan Hariharan, Kuniyuki Kakushima, V. Ramgopal Rao, Parhat Ahmet, and Hiroshi Iwai, IEICE Transactions on Electronics (Japan), Vol. E90-C, No.10, October 2007.

2006

Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies
K. Narasimhulu, V. Ramgopal Rao, Proceedings of the 19th International Conference on VLSI Design, January 3 - 7, 2006, Hyderabad, India.

Analog Device and Circuit Performance Degradation under Substrate Enhanced Hot Carrier Stress Conditions
K. Narasimhulu and V. Ramgopal Rao, 44th Annual International Reliability Physics Symposium (IRPS), March 26-30, 2006, San Jose, California, USA.

Lateral profiling of trapped charge in SONOS Flash EEPROMs programmed using channel hot electron injection
P. Bharath Kumar, P. R. Nair, R. Sharma, S. Kamohara and S. Mahapatra, IEEE Trans. Electron Devices, v.53, p.698, 2006.

Parasitic Effects in Multi-gate MOSFETs
Manoj C.R, Abhinav Mangal, V. Ramgopal Rao, Hiroshi Iwai, International Workshop on Nano CMOS, Jan 30- Feb 1, 2006, Mishima, Shizuoka prefecture, Japan (Invited).

The Effect of Single Halo Doping on the Low-Frequency Noise Performance of Deep Sub-micron MOSFETs
K. Narasimhulu, I. Venkata Suryam Setty, V. Ramgopal Rao, IEEE Electron Device Letters, Volume 27,Issue 12, Pages:995-997, December 2006.

2005

A New Oxide Trap Assisted NBTI Degradation Model
Neeraj K. Jha, V. Ramgopal Rao, IEEE Electron Device Letters, Volume: 26, Issue: 9, September 2005, pp.687-689.

Controlling Injected Electron and Hole Profiles for Better Reliability of Split Gate SONOS
K. Sridhar, P. Bharath Kumar, S. Mahapatra, E. Murakami , and S. Kamohara, International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, p.190, 2005.

Deep Sub-micron Device and Analog Circuit Parameter Sensitivity to Process Variations with Halo Doping and Its Effect on Circuit Linearity
K. Narasimhulu, V. Ramgopal Rao, Japanese Journal of Applied Physics, April, 2005.

Design of 0.1 um single halo (SH) thin film silicon-on insulator (SOI) MOSFETs for analog applications
Najeeb-ud-din, V. Ramgopal Rao, J. Vasi, Semiconductor Science and Technology, Vol. 20, p.895-902, 2005 (IOP Publishing Ltd, UK).

Effect of Compensation Implant in SONOS Flash EEPROMs
P. Bharath Kumar, Ravinder Sharma, E. Murakami , S. Kamohara, and S. Mahapatra, International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, p.644, 2005.

Evaluation of the Impact of Layout on Device and Analog Circuit Performance with Lateral Asymmetric Channel MOSFETs
D. V. Kumar, K. Narasimhulu, P. S. Reddy, M. Shojaei, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, IEEE Transactions on Electron Devices, Volume 52, Issue 7, July 2005 Pages:1603 – 1609.

Forward Body-biased Single Halo MOS Devices for Low Voltage Analog Circuits
K. Narasimhulu, V. Ramgopal Rao, Proceedings of the 2005 International Conference on Simulation of Semiconductor Processes and Devices, September 1-3, 2005, Tokyo, Japan.

Hole energy dependent interface trap generation in MOSFET Si/SiO2 interface
D. Varghese, S. Mahapatra and M. A. Alam, IEEE Electron Devices Lett., v.26, p.572, Aug. 2005.

Mechanism of drain disturb in SONOS Flash EEPROMs
P. Bharath Kumar, Ravinder Sharma, Pradeep R. Nair, Deleep R. Nair, S. Kamohara, S. Mahapatra, and J. Vasi, Int. Reliability Phys. Symp (IRPS), San Jose, USA, p.186, 2005.

Multigate FETs for sub 65nm CMOS Technologies- Implications for Circuit Design
M. V. Rammohan Reddy, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, 13th International Workshop on The Physics of Semiconductor Devices (IWPSD), December 13-17, 2005, New Delhi (Invited).

NBTI Degradation and its Impact for Analog Circuit Reliability
Neeraj K. Jha, P. Sahajananda Reddy, D.K. Sharma and V. Ramgopal Rao, IEEE Transactions on Electron Devices, pp. 2609-2615, December 2005.

Optimization of Sub-100 nm Gamma-gate Si-MOSFETs for RF Applications
Mayank Gupta, V. Vidya, V. Ramgopal Rao, Kun H. To, J.C.S. Woo, Wireless Design and Development magazine (Featured Technology Article), December 2005 (Invited).

Optimum Body Bias Constraints for Leakage Reduction in High–K CMOS Circuits
Pradeep Kumar Chawda, Bulusu Anand, and V. Ramgopal Rao, Japanese Journal of Applied Physics, April, 2005.

Performance of Channel Engineered SDODEL MOSFET for Mixed Signal Applications
Partha Sarkar, A. Mallik, C. K. Sarkar, V. Ramgopal Rao, Proceedings of the 2005 IEEE International Conference on Electron Devices and Solid-State Circuits, Hong Kong, December 19-21, 2005

Power-Area Evaluation of Various Double-Gate RF Mixer Topologies
M. V. Rammohan Reddy, D. K. Sharma, M.B.Patil and V. Ramgopal Rao, IEEE Electron Device Letters, Volume: 26, Issue: 9, June 2005, pp.664 – 666.

Superior Hot Carrier Reliability of Single Halo (SH) Silicon-on-Insulator (SOI) nMOSFET in Analog Applications
Najeeb-ud-din, V. Ramgopal Rao, J. Vasi, and J. C. S. Woo, IEEE Transactions on Device and Materials Reliability, Volume 5, Issue 1, Pages: 127 – 132.