Effects of process-induced strain on the performance enhancement of Omega (O)-FinFETs have been investigated using Sentaurus process and device simulation tools. The capability of technology CAD (TCAD) for FinFET process development with strained silicon (strained-Si) as channel material is the main focus of our study.

The 2006 ITRS Update indicates that the gate length for conventional CMOS technology should be scaled below 10nm before 2015. In recent years, non-classical MOS devices such as FinFETs have received considerable attention owing to their capability of suppression of short channel effects, reduced drain-induced barrier lowering and excellent scalability. Strained-Si technology is beneficial for enhancing carrier mobilities to boost Ion. Both electron and hole mobilities can be improved by applying stress to induce appropriate strain in the channel, e.g., tensile strain for n-channel MOSFETs and compressive strain for p-channel MOSFETs [1]. Implementation of strain in FinFET structures will further enhance the transistor performance.

FinFETs are promising candidates for downscaling into the nanoscale regime and the manufacturability (Yield and process variability) of omega FinFET structures is still a big issue for device manufacturing companies. Many different methods have been proposed to fabricate FinFET devices but most of them suffer from technical challenges mainly due to the process complexity. In this work, Synopsys TCAD tools are used for the FinFET process development and device performance predictions [2]. Figures 1-2 show some process simulated results for 25 nm gate length FinFETs. Silicon-Fin is fabricated on buried-oxide (BOX) and consecutively capped with nitride (Si3N4). A tensile process induced strain has been evolved in the Fin, during thermal process. The effect of Nitride cap layer on electrical performance of an Omega FinFET has been shown in figure 3 and 4.

[1] C. K. Maiti, S. Chattopadhyay, and L. K. Bera, Strained-Si Heterostructure Field Effect Devices, CRC Press, Boca Raton, 2007.

[2] Sentaurus Technology Templates: 25nm Omega FinFet-3D process and Device Simulation http://www.synopsys.com/Tools/TCAD/Pages/pmos.aspx