Various Authors
Department of Electrical Engineering
University of Washington

Faculty in the Electrical Engineering Department at the University of Washington use several Synopsys tools for studies on reconfigurable systems. Design Compiler has been used to create hardware blocks [1]. Pathmill has been used for extracting timing information, testing several layout generation methods and final analysis of the results [2-5].

[1] S. Phillips, A. Sharma, S. Hauck, “Layout Generation for Domain-Specific FPGAs”, submitted to IEEE Transactions on VLSI Systems.
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[2] S. Phillips, Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip, Ph.D. Thesis, University of Washington, Dept. of EE, 2004.
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[3] S. Phillips, S. Hauck, “Automatic Layout of Domain-Specific Reconfigurable Subsystems for System-on-a-Chip”, ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pp. 165-173, 2002.
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[4] S. Phillips, A. Sharma, S. Hauck, “Automating the Layout of Reconfigurable Subsystems Via Template Reduction”, International Conference on Field Programmable Logic and Applications, pp. 857-861, 2004.
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[5] S. Phillips, A. Sharma, S. Hauck, “Automating the Layout of Reconfigurable Subsytems Via Template Reduction”, IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 340-341, 2004.
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