Newsletter 

ISPD 2013 Discrete Gate Sizing Contest
Registration Deadline: December 14th, 2012
March 24-27, 2013 - Lake Tahoe, CA

During the past few years, ISPD has been hosting placement, routing, and clock network synthesis with challenging industrial benchmarks. These contests have significantly advanced the quality of algorithms for physical design. Last year, ISPD hosted the 1st discrete gate sizing contest, in which it exposed some of the physical synthesis challenges to the academic community, while keeping the problem complexity still manageable. In 2013, ISPD will continue the tradition and host an updated contest for simultaneous gate sizing and Vt assignment to optimize performance and power. Contest results will be announced at the ISPD event in March 2013.

Synopsys Joins PACE Global Partnership

Synopsys has recently joined the Partners for the Advancement of Collaborative Engineering Education (PACE) program. Through the PACE program, Synopsys' Saber product line for the modeling and simulation of power, physical and multi-domain automotive systems will be provided to all 57 PACE institutions worldwide.

PACE is an initiative by GM, Autodesk, HP, Oracle, and Siemens PLM Software to support strategically selected academic institutions through the contribution of computer-based engineering tools. The goal of PACE is to integrate essential automotive-related applications into 57 select institutions worldwide in order to develop the automotive product lifecycle management team of the future. Through PACE, engineering students develop practical skills in the core applications and processes they will use in high-technology careers in industry. Synopsys and 16 other companies support PACE in this effort and are proud to be involved in this program.

Curriculum

The following new and updated courses are now available. Visit Members Only with your SolvNet ID and password to download.

• Introduction to RF Communication - Updated!
• Design of Programming Languages - New!

Featured Webinar

View our online webinars and learn from technology experts on a variety of topics:

• Accelerate Time-to-Tapeout with IC Compiler Co-Design
  Learn how using IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage development.

Articles

	Physics-Based Three-Dimensional Analytical Model for RDF-Induced Threshold Voltage Variations Purdue University: Georgios Panagopoulos and Kaushik Roy
	Elastic-Buffer Flow Control for On-Chip Networks Stanford University: George Michelogiannakis, James Balfour and William J. Dally
	Silicon-Die Thermal Monitoring Using Embedded Sensor Cells Unit Universite du Quebec en Outaouais: Various Authors
	Cryogenic Operation of Junctionless Nanowire Transistors Centro Universitario da FEI: Various Authors

Upcoming Events

	International SOC Conference 2012 (ISOCC) November 4-7, 2012 Jeju, Korea
	Fifth International Workshop on Network on Chip Architectures (NoArc 2013) November 4-7, 2012 Vancouver, BC, Canada
	IP-Embedded System Conference & Exhibition (IP-SOC 2012) December 4-5, 2012 Grenoble, France
	DesignCon 2013 January 28-31, 2013 Santa Clara, CA

Call for Papers

• LASCAS 2013
  Due By: November 3, 2012

• CSEDU 2013
  Due By: November 13, 2012

• GLSVLSI 2013
  Due By: December 15, 2012

• MSE 2013
  Due By: January 15, 2013