Process induced transistor variability has emerged as an important issue in Nano CMOS technologies. For the sub-65nm technology nodes, variability aware device technology development and modeling thereof is the key to enable robust and manufacturable circuit designs. Several groups have attempted to address this problem either in technology domain (Technology CAD) or in the circuit design domain (Design CAD). However, for the first time we have been able bridge the gap between these two domains by predicting the delay variability in a digital circuit (4x4 Wallace tree multiplier) as function of variability in underlying process parameters. Synopsys TCAD tools were used extensively in this work.

We have used process simulation and device simulation approach to design 65nm gate length transistors and characterize the impact of variation in gate length, oxide thickness, halo implant dose and tilt angle, super steep retrograde implant dose, source/drain anneal temperature. A NAND gate library for delay variation is constructed using mixed mode simulations. An analytical model based on response surface methodology is developed and is then instantiated during the circuit simulation. Monte Carlo simulations are performed to predict the distribution in circuit delay as a function of a given variation in process parameters. The usefulness of this technique in statistical design methodology is demonstrated.

For more information on this work, please refer to our IEEE paper:
http://ieeexplore.ieee.org/iel5/43/4100744/04100752.pdf?tp=&isnumber=&arnumber=4100752