IPL (Interoperable PCell Libraries) is an industry alliance, publicly announced in April 2007, to collaborate on the creation and distribution of open-source interoperable PCell libraries (IPL) that supports the OpenAccess database from the Silicon Integration Initiative (Si2). The five founding members of the IPL initiative are Applied Wave Research (AWR), Ciranova, Silicon Canvas, Silicon Navigator and Synopsys. Since then membership has grown to include Helic, JEDAT, Magma Design Automation and Virage Logic. Mentor Graphics and Pulsic are the supporting members. Each member has signed an agreement stating that they will support the interoperable PCell libraries as defined by the IPL initiative.

PCells (parameterized cells for basic analog elements such as transistor, diodes, capacitors and resistors) are the fundamental building blocks for analog physical design. Analog designers have been using PCells to help accelerate the layout process for almost 20 years. In that time there have been few if any significant advancements in productivity for analog flows.

An IPL has many advantages to semiconductor companies, foundries and EDA vendors. Semiconductor companies will be able to use one common PCell library providing advanced functionality across multiple processes and reducing development and support costs while increasing layout flexibility. Foundries will be able to reduce their PDK development costs while dramatically expanding the number of tools they support. EDA vendors will also be able to reduce PDK development costs, while supporting a wider range of foundry partners.

Since its inception, IPL group has released a high-quality proof-of-concept PCell library using a generic 0.13um process. This library demonstrates that the IPL mechanism works, and provides a starting point for other companies to start building their own interoperable libraries. The proof-of-concept library is available for free download at www.iplnow.com

IPL members understand the importance of interoperability and have taken steps to ensure that an ecosystem (see figure 1 at end of article) was created to validate and demonstrate that the interoperable PCells released by the group worked with all members' tools.

Most recently in October 2007, IPL announced the formation of three technical working groups, namely PCells, Properties and Parameters, and Constraints. These three areas have been identified as providing the most benefits when standards are applied. With this announcement the IPL initiative has expanded its charter to address broader interoperability issues with foundry process design kits (PDK) and design flows.

In addition to the efforts from the EDA community, there is an on-going "FreePDK" project led by professors from North Carolina State University and Oklahoma State University. The objective of the project is to create an open-source, variation-aware 45nm PDK for use in VLSI education and small-businesses. For more information about the "FreePDK" project, please visit its Wiki page at http://www.eda.ncsu.edu/wiki/FreePDK.

Standardization of PDKs and design flows benefits analog and custom IC designers by removing bottlenecks in multiple-vendor flows. The industry needs a standardized approach to defining the basic building blocks of analog design. The digital work has enjoyed this for years, and productivity has soared. It's time for analog design automation to start showing some progress in improving productivity.

The IPL initiative is actively looking for knowledgeable individuals to participate and contribute to the standards. For more information about IPL or to join the program, please visit the official IPLNow website.