The following papers, authored and co-authored by Synopsys engineers, were presented at the 2009 International Symposium on Quality Electronic Design (ISQED). These papers focus on the research, development, and application of design techniques & methods, design processes, and EDA design methodologies and tools that address issues which impact the quality of the realization of designs into physical integrated circuits.

A General Piece-wise Nonlinear Library Modeling Format and Size Reduction Technique for Gate-level Timing, SI, Power, and Variation Analysis
Xin Wang, Alireza Kasnavi and Harold Levy
Synopsys Inc.

Analysis of Performance and Reliability Trade-Off in Dummy Pattern Design for 32-nm Technology
A.P. Karmarkar, Xiaopeng Xu, V. Moroz, G. Rollins and Xiao Lin
Synopsys Inc.

Automatic Register Banking for Low-Power Clock Trees
Wenting Hou, Dick Lui and Pei-Hsin Ho
Synopsys Inc.

Leakage Optimization Using Transistor-Level Dual Threshold Voltage Cell Library
Chandra S. Nagarajan, Lin Yuan, Gang Qu and Barbara G. Stamps
Cisco Systems Inc., Synopsys Inc., Univ. of Maryland, Atmel Corp.

Phenomenological Model for Gate Length Bias Dependent Inverter Delay Change with Emphasis on Library Characterization
Qian Ying Tang, Qiang Chen, Niloy Chatterjee, Vedank Tripathi, Natarajan Nandagopalan and Sridhar Tirumala
UC Berkeley, Synopsys Inc.

Proactive Management of X’s in Scan Chains for Compression
A. Chandra, Y. Kanzawa and R. Kapur
Synopsys Inc.

Validating Physical Access Layer of WiMAX Using System Verilog
Albert Chiang, Wei-Hua Han and Bhanu Kapoor
Synopsys Inc., Mimasic