Parastoo Nikaeen and Boris Murmann
Department of Electrical Engineering
Stanford University

Modern CMOS technologies provide digital signal processing capabilities at high integration density and low energy per operation. Hence, expending digital signal processing to enhance the performance analog building blocks has become an active research topic. In this work, we present a digital technique for the compensation of dynamic nonlinearities at the front-end of high-speed, high-resolution A/D converters. The complexity of the digital post-processing scheme is minimized using judicious modeling of the relevant analog circuit nonidealities. Applying the method in lab experiments to a 14-bit, 155-MS/s ADC showed a linearity performance of SFDR > 83 dB up to input frequencies of 470 MHz. In order to ensure practicality of the proposed scheme, we used logic synthesis tools to estimate its complexity in hardware. Using a 90-nm standard CMOS library, we found that the block will consume 52 mW and occupy approximately 0.54 mm².

The authors would like to acknowledge Synopsys for educational licenses of Design Compiler and VCS used in this work.

For more information on this work, please refer to the work presented at the 2008 IEEE Custom Integrated Circuits Conference (http://www.ieee-cicc.org). The full paper is available at the IEEE website.