Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson and Mark Horowitz
Department of Electrical Engineering
Stanford University

Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to validate memory system implementation. Having a memory scoreboard, a high-level model of the memory, greatly aids simulation-based validation, but accurate scoreboards are complex to create since often they depend not only on the memory and consistency model but also on its specific implementation. This paper describes a methodology of using a relaxed scoreboard, which greatly reduces the complexity of creating these memory models.

In general, almost the entire Smart Memories verification environment was written using OpenVera, and was compiled and simulated using VCS. In particular, the relaxed scoreboard itself is implemented as a couple of classes written in OpenVera.

Full article

.