Manoj C. R., V. Hariharan, Angada B. Sachid, Rajesh Thakker, Dhanya Varghese, Meenakshi Nagpal, Roswald Francis, Maryam Shojaei Baghini, Mahesh B. Patil, V. Ramgopal Rao, Dinesh K. Sharma, and J. Vasi
Department of Electrical Engineering
IIT Bombay, India

Planar MOSFET devices have been the back bone of the semiconductor industry for many decades now. Scaling has not only resulted in smaller and faster transistors. At the same time, single-gate MOSFET devices do not have adequate gate control over the channel resulting in degradation in the short-channel performance and leakage current of the scaled transistors. A large number of multiple-gate MOSFET devices are proposed in literature in which the gate control over the channel is increased by using multiple gates. In extremely scaled transistors process variations arising from lithography, implantation, annealing etc affect circuit and system performance. FinFET, a 3D quasi-planar multiple-gate MOSFET device is the most promising among the emerging alternative device structures to continue scaling due to its excellent short-channel performance, manufacturability, and lower random-dopant fluctuation due to undoped channel.

We look at device optimization of bulk and SOI FinFET devices [1], [2], effect of process variations [3] and compact modeling of FinFET devices [4], [5] .We have used a combination of Sentaurus TCAD-based process simulation, structure editor, device simulation as the platform for our studies. Simulations were performed after calibrating the simulation models with experimental data.

• Device Design & Optimization Considerations for Bulk FinFETs.
  C.R.Manoj, Meenakshi N, Dhanya V. and V. Ramgopal Rao, IEEE Transactions on Electron Devices, Vol. 55, No.2, p. 609-615, February 2008.
• Gate Fringe Induced Barrier Lowering in Underlap FinFET Structures and its Optimization.
  Angada B. Sachid, Manoj C. R., Dinesh K. Sharma, and V. Ramgopal Rao, IEEE Electron Device Letters, Vol. 29, Issue 1, pp.128-130, January 2008.
• Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field-dependent Mobility and Body Doping.
  V.Hariharan, R. Thakker, M. B. Patil, J. Vasi and V. Ramgopal Rao, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A.
• Drain Current Model Including Velocity Saturation for Symmetric Double-Gate MOSFETs.
  Venkatnarayan Hariharan, Juzer Vasi, and V. Ramgopal Rao, IEEE Transactions on Electron Devices, Vol. 55, No. 8, pp. 2173-2180, August 2008.