The Synopsys 32/28nm Generic Library is designed for use in teaching microelectronic design. When used with the latest Synopsys EDA tools it enables students to use a more complete design flow and to master today's advanced design methods, such as low power.
|32/28nm Generic Library Basics |
- Optimized for low power design
- Optimized for use with Synopsys EDA software tools
- Requires Synopsys university EULA and license addendum
- Not designed for fabrication
32/28nm Generic Library Content
The Technology Kit includes a schematic symbols, HSPICE simulation models, DRC and LVS runsets for Synopsys IC Validator and Hercules , HSPICE netlists, C/RC extraction files for Synopsys StarRC, technology files.
Digital Standard Cell Library
The Digital Standard Cell Library consists of 350 cells to optimize the IC design. The library includes typical miscellaneous combinational and sequential logic cells for different drive strengths. It has all the required deliverables for low power design including support for IC designs with different core voltages to minimize dynamic and leakage power. The library is designed for 1.05V operation with a process technology of 1P9M 1.05V/2.5V and an operating frequency of 300 MHz.
I/O Standard Cell Library
The I/O Standard Cell Library consists of 42 standard and 3 special I/O cells: digital, analog, power/ground pads for different loads and miscellaneous cells. The library is provided in two versions: wire-bond and flip-chip.
Memories include 35 medium-sized RAMs (SRAMs). They are synchronous dual and single-port with write enable, output enable, and chip select on each port. They have the same architecture and vary in size. The set also includes Low Power SRAMs with leakage saving modes
Phase Locked Loop (PLL)
The Phase Locked Loop (PLL) clock multiplier circuit can generate a stable, high-speed clock from a slower clock signal. It has 3 operating modes: normal, external feedback and bypass.
The 32/28nm Generic Library contains two sample designs: Orca and ChipTop. Further addition of reference designs is anticipated (such as OpenSPARC T1 and Leon3 processors). It also includes sample of flip-chip and wire bond designs with all required setup information.
ChipTop is a processor architecture that features the Unified Power Format (UPF) for advanced low power designs. This reference, with included memory blocks, can be used with the 32/28nm Generic Library and design tools to understand the implementation of low power design methodologies and design for low power. The Orca design contains one functional block of the Orca processor. This reference can be used with the 32/28nm Generic Library to understand the basic design steps when using logical (DC) and physical (ICC) design tools.
The 32/28nm Generic Library is now available in Members Only for Synopsys University Program members to download. You must have a valid SolvNet ID and password to access. To request support for the 32/28nm Generic Library, contact us.
"...The EDK and Synopsys tools have greatly helped our research by enabling us to quickly translate our design from Verilog code into IC layouts and subsequently evaluating circuit performance."
— Haibo Wang, Professor of Electrical Engineering, Southern Illinois University, Carbondale
"The libraries were successfully used to perform model checking-based verification with Formality; and also the schematic version was successfully used to perform synthesis for different combinational and sequential designs. They will be very valuable for research as well as teaching."
— Ehat Ercanli, Assistant Professor of Electrical Engineering & Computer Science, Syracuse University
"I have been using the Synopsys 32/28nm library for the past two years in my thesis research. The 32/28nm library itself provides a vast number of components along with parameter data that allow a lot of options when designing circuits. When I combine the 32/nm library, Hercules, Design Compiler and IC Compiler, I have a quick way of producing layout designs from Verilog code. The 32/28nm library and Design Vision together give me a means of easily integrating SDF data and post-layout-extracted RTL to run simulations. Utilizing the 32/28nm library with PrimeTime gives me access to power and timing data that is crucial for my thesis paper and related journal article."
— Ron Eaton, Graduate Student, Southern Illinois University, Carbondale