SNUG Taiwan Abstracts  

Tuesday, September 10, 2013
9:10 AM - 10:00 AM
Welcome and Synopsys Keynote
Accelerating Innovation in the Era of Exponentials
Manoj Gandhi, Senior Vice President & General Manager, Verification Group - Synopsys
Mobile and Compute convergence is exponentially driving chip complexity and leading to new SoC design methodologies that will advance the future of our industry. There is extreme time-to-market pressure, growing software content, need for low power, rising cost of design and overall growth in complexity, driven by the integration of more and more IP in today’s SoCs. As a result, the verification challenge is growing exponentially. Manoj’s presentation will provide insights into Synopsys’ strategy and technical vision for driving industry innovation to the next level as we address the next generation of SoC verification.


Tuesday, September 10, 2013
1:30 PM - 3:00 PM
TA1 - HPC Implementation and Panel
Proving the 20nm Implementation Ecosystem Using an ARM Mali GPU with a Full Galaxy Tool Flow
Tim Whitfield - ARM
ARM and Synopsys collaborated to implement an ARM Mali GPU-based SoC in 20nm technology with ARM physical IP as a silicon test vehicle to prove out a full DPT-compliant Synopsys Galaxy implementation flow. We'll begin the presentation by outlining the differences between implementing an ARM GPU compared to a traditional ARM CPU core. We will then cover the challenges introduced by complex process rules at 20nm, including double pattering, and how they were addressed. To help prepare designers for the challenges at 20nm and beyond, we'll also share the best practices learned through this collaboration.

Synopsys Products:
Full Galaxy Implementation flow for 20 and below.

Target audience:
implementation engineers, especially those interested in 20nm and below, as well as those interested in GPU implementation.

HPC Panel - Achieving Optimum Results on High-Performance Processor Cores
Moderator: Erik Olson, Synopsys, Panelists: Tomoyasu Kitaura, - Fujitsu Krishna, Kant Verma - Qualcomm, Naveen Raina - ST, Joe Walston - Synopsys
In this interactive two-part session, designers with hands-on experience implementing high performance processor cores will share insights and best practices for achieving optimum performance and power. Each panelist will highlight a design challenge and solution in the implementation process – from synthesis to placement, CTS, routing and signoff STA closure - featuring techniques and technologies available with the Galaxy Implementation Platform. The second part of the session will be an interactive "ask the experts" panel discussion where audience members can dig deeper into the insights and best practices shared. For example, have you wondered when to use mesh and when to use traditional CTS on your high performance design? Or, whether and where to use structured placement to get better results? Don’t miss the opportunity to hear responses to these and other challenges and experience what your peers and Synopsys experts have to say about optimizing high performance cores.

Target audience:
High performance core designers, back-end and front-end implementation users.


TA2 - Test/IP
Era of IP
Dan Kochpatcharin, TSMC
With the increasing pressure to bring new design to market quickly and the need for "right the first time", designers are using more and more 3rd party IP in their design. We will discuss how to select IP, and how to make money in IP in this new era.

Port Limit Solution - JTAG Base Test Mode Decoder
Chingtze Kao, Faraday
As SoC designs become more popular, the concept of the reusable IP has been widely adopted. To integrate an IP into a SoC design, the designer needs to correctly connect the function pins of the IP to the SoC to ensure the quality of the design functions. In addition to concentrating on the normal functions, the IP testing should be taken into consideration at the design stage. , A proper test mode of an IP and the test ports of the IP should be properly connected to the SoC boundary. Faraday have developed a series utility to perform the chip test integration, UTDR (User Test Data Register) for test mode select, preamble test pattern generation and IP test signal connection check. In this session, we will demonstrate how to work with BSD Compiler and our in house tool.

Synopsys Tools Used:
BSD Compiler

Target Audience:
Designers, DFT Engineers, Test Engineers

DFTMAX with Serializer Architecture for I/O Limit
Liu Jia Ping, Phison
In some PAD limit designs, DFT compress performance is impacted causing a reduction in fault coverage. To get higher fault coverage, the amount of test pattern is increased, which impacts testing cost. Synopsys's DFTMAX provides a new way to solve this problem. DFTMAX's serializer architecture, adds control circuitry to control I/O signals with little area and timing overhead, achieving a good result. Based on such methodology and framework, we will reveal the benefit on a practical case.

Synopsys Tools Used:
DFTMAX

Target Audience:
Designers, DFT Engineers, Test Engineers

Memory Repair Solution With Synopsys SMS
Karl Chang, GUC
Synopsys Tools Used:
DesignWare STAR Memory System

Target Audience:
Designers, DFT Engineers, Test Engineers, Product Engineers and Foundry Engineers who are, or will be, designing or characterizing the SoCs. The tutorial will provide introductory as well as advanced content.


TA3 - Circuit Simulation
CustomSim Native IR/EM Solution
Isabel Wang, TSMC
Last year SNPS-CSIM just offered hybrid methodology and TSMC was looking for a better methodology for EM/IR. During these months SNPS has improved the CSIM EM/IR accuracy of the TMI and PODE back-annotation solution testing and also finished the correlation and qualification experiment with HSPICE.

Synopsys Tools Used:
CustomSim, HSPICE

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers

Experience Sharing on Improving Simulation Time With Power Generator Circuit
Yu-Sheng Yang, Winbond
With the growth of IC complexity, the full chip simulation becomes much more time consuming. For DRAM design, most of the IPs in the power management block are analog circuits, so the simulation accuracy is also important. With higher accuracy comes longer simulation time. For instance, it takes a couple days to complete the simulation of "analog relative circuit" with HSIM. But with some special features in FINESIM, the simulation time reduce more than 50% with only 1% accuracy difference compared to the previous simulator (HSIM). So FINESIM really improves the trade-off between simulation time and accuracy.

Synopsys Tools Used:
FineSim

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers

Mixed-Signal Design Verification Using Co-simulation With VCS-XA
Bruce Chiu, KeyAsic
This paper introduces the mixed-signal design functional verification methodology, it's very helpful using the co-simulation to verify the complex mixed-signal design behavior. Compared with the traditional verification ways, co-simulation reduced the testbench build up complexity and increased the circuit simulation time. Paper will discuss some tips to fix the setting issue of the VCS-XA co-simulation environment, to get the expected simulation results. Finally will de-scribes some design examples using the VCS-XA co-simulation flow.

Synopsys Tools Used:
VCS-XA

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers

A Practical Look at Current Analysis in FastSpice
Joe Huang, Synopsys
With smaller process geometries, detailed Current Analysis has become more crucial, highlighting the challenges of obtaining reliable Current results through circuit simulation. This presentation will be a practical discussion of these challenges and how they are handled in FastSpice, including analysis of real examples. We will examine how simulator accuracy, measurement methodology and circuit state can impact the reliability of Current Analysis results in FastSpice. Additional topics include methods to improve the user’s confidence in their Current Analysis results and available XA features to further improve Current Analysis results.

Synopsys Tools Used:
CustomSim/XA

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers


TA4 - Verification
A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests
Richard Tseng, Qualcomm
A SOC design in a company usually would have been evolved for many product generations. There are many software tests recognized as "golden" regression suites that have been used for signing off the tape out. While the design verification community is moving toward the UVM, engineers have been facing a big challenge to reuse or import those golden C tests in a UVM testbench. In this paper, a generic UVM testbench architecture that overcomes this challenge will be demonstrated. The testbench allows engineers to reuse high-level verification components, and C and UVM test sequences for future design generations. It also allows users to run multiple C and UVM mixed test sequences concurrently. Test writers can use those existing API tasks and UVM reporting macros, such as 'uvm_info and 'uvm_error in C and UVM interchangeably. The integration of the UVM register layer will be addressed. The target audience would be intermediate/advanced UVM users.

Synopsys Tools Used:
VCS

Target Audience:
Intermediate/advanced UVM users

Does Power State Table Matter in Low Power Verification?
Shang-Wei Tu, MediaTek
With the growing low power complexity of SOCs, designers tend to define fine grant power domains for saving power. However, the legal power modes of the PST grow exponentially with the number of domains. In practice, designers often give an incomplete PST, but this is a bad RTL UPF input for the low power verification and even the implementation. For the static low power checking tool MVRC, it assumes that the given PST is complete, and then it can do complete checks. For the dynamic power-aware simulation tool MVSIM NLP, it can generate the coverage from the PST described in UPF for the verification team to consider it as a goal. Therefore, there is a gap between what does the tool assumes and what do the designers provide. In this paper, we propose a methodology to generate complete PSTs to eliminate the gap. In addition, we also demonstrate how to generate PSTs for the dynamic simulation as a coverage goal.

Synopsys Tools Used:
VCS, NLP, MVRC

Target Audience:
Verification Engineers and RTL Designers

Macro Power Aware Simulation Dilemma: UPF or DB
Kaowen Liu, MediaTek
Macro blocks exist in different parts of SOC design and it is a common practice to use behavioral models and technology libraries in simulation and implementation respectively. However, with low power verification, it becomes a challenge to handle such macros while making sure that the power intent of the macro is captured accurately. Therefore, it is mandatory to devise a power aware design paradigm that can represent the macro block's power specification through the design cycle. In this paper, we discuss the power specification capabilities and limitations of the Unified Power Format and Liberty library syntax for macro blocks. In addition, we propose a power aware design paradigm which can best suit Synopsys's verification tools (MVSIM NLP and MVRC).

Synopsys Tools Used:
VCS, MVSIM, NLP, MVRC

Target Audience:
Verification Engineers

VCS for Best Performance
Alvin Chen, Synopsys
VCS Core Technologies for Best Performance


Tuesday, September 10, 2013
4:00 PM - 6:00 PM
TB1 - HPC Implementation
Rectilinear Shape Floorplan and High Density Mali 400 Design with TSMC 28nm HPM process
Webber Tseng, Novatek
Mali 400 implementation with rectilinear shape floorplan. It still can meet the target frequency (450MHz). Each core in Mali 400 is high density (utilization is almost 90%).

Synopsys Products:
Galaxy Implementation flow

Target audience:
implementation engineers, especially those interested in GPU implementation

Part 1: Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor
Craig Tou - ARM, Dale Lomelino - Synopsys
Learn how to optimize the Quad-Core ARM® Cortex™-A7 MPCore™ processor for the best power efficiency targeted for entry mobile and other power-sensitive products. This tutorial will highlight the latest technologies in Design Compiler Graphical and IC Compiler that can be used to achieve challenging power/performance targets. Shared best practices leverage Synopsys' high-performance core (HPC) methodology, including optimizations for power as a primary requirement to be managed at each step in the flow; from synthesis, placement, clock and routing, to post-route timing closure. Low power capabilities introduced here are augmented with aggressive power management of library VT classes and timing targets. The power-centric high-performance core methodology will be illustrated through a reference implementation of a quad core Cortex-A7 processor with ARM POP™ technology for core-hardening acceleration on TSMC 28HPM process. The final product is a strong starting point for designing the 'LITTLE' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for cost-sensitive markets.

Part 2: Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor
Craig Tou - ARM, Joe Walston - Synopsys
Learn how to optimize the Quad-Core ARM® Cortex™-A7 MPCore™ processor for the best power efficiency targeted for entry mobile and other power-sensitive products. This tutorial will highlight the latest technologies in Design Compiler Graphical and IC Compiler that can be used to achieve challenging power/performance targets. Shared best practices leverage Synopsys' high-performance core (HPC) methodology, including optimizations for power as a primary requirement to be managed at each step in the flow; from synthesis, placement, clock and routing, to post-route timing closure. Low power capabilities introduced here are augmented with aggressive power management of library VT classes and timing targets. The power-centric high-performance core methodology will be illustrated through a reference implementation of a quad core Cortex-A7 processor with ARM POP™ technology for core-hardening acceleration on TSMC 28HPM process. The final product is a strong starting point for designing the 'LITTLE' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for cost-sensitive markets.

Part 3: Engineering Trade-Offs in the Implementation of a High Performance Dual Core ARM® Cortex™-A15 Processor
Craig Tou - ARM, Joe Walston - Synopsys
Learn about the engineering trade-offs and flow development process to balance gigahertz+ performance and low power on a dual-core Cortex-A15 MPCore™ processor implementation. This tutorial will highlight best practices and technologies from the Galaxy Implementation Platform to meet challenging performance targets, while minimizing leakage power. Synopsys's high-performance core (HPC) methodology will be demonstrated through a reference implementation of a dual-core ARM Cortex-A15 processor with ARM POP™ technology for core-hardening acceleration on TSMC 28HPM process. Technologies featured include physical guidance for a predictable implementation flow, transparent interface optimization for faster top-level closure, and final-stage leakage recovery for reduced leakage power. The final product is a strong starting point for designing the 'big' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for high-end mobile markets.

Synopsys Products:
Galaxy Implementation Flow

Target audience:
implementation engineers, especially those interested in A15 implementation


TB2 - Static Timing Analysis
IDEA: Innovative AOCV Design Flow with Efficiency and Accuracy
Lancer Chen, Faraday
Process variation becomes particularly important at smaller process nodes as the variation leads to a larger percentage of the full length or width of the device. Traditional on-chip-variation has been introduced by adding the single derating value on all timing paths to model process variation but it is too pessimistic for increasing process variation. Compared with traditional OCV, advanced-OCV gives different derating values on different timing paths. In this way, it can dramatically alleviate the over-pessimism of derating and reduce over-design and timing closure cycles.

In this presentation, we introduce an AOCV flow which includes AOCV table generation, implementation and sign-off. In AOCV table generation, we focus on how to select design-oriented process variation parameters. Implementation-oriented AOCV table can lead to faster TAT, and EDA timing fixing tools can support the AOCV table. In sign-off stage, we compared results of Synopsys primetime AOCV-PBA against those of Synopsys HSPICE, and the experiment results show that the mismatches are less than 1%.

Synopsys Products:
PrimeTime

Target audience:
Design Engineer, STA Engineer

Achieving Timing Closure on Hundred Million Gates SoC Design with ETM & ILM
Chi-Chia Yu - Faraday
Nowadays, processes have shrunk to nm scale and more components have moved on-die. While the chip size is getting larger, million gate SoC design will become a normal size in the future. How to achieve timing closure for this kind of huge design is a challenge for SoC engineers. A general method is to partition the SoC design into several sub-blocks. Every sub-block implements independently and integrates in the top level. This means the timing model will play an important role for timing analysis and integration in both the pre-layout and post-layout stage. Synopsys provides several useful timing models to use in different design stages. We used ETM and ILM to achieve timing closure on a million gate SoC design and these two models helped us to reduce the EDA tool's run time, keep design accuracy and save memory usage of the machine. We will compare the accuracy and advantages of ETM and ILM and share our experience in this paper.

Synopsys Products:
PrimeTime

Target audience:
Design Engineer, STA Engineer

Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction
Brad Lee - Synopsys
PrimeTime's 2012.12 release builds on Synopsys' Galaxy low power flow and adds signoff based leakage recovery to existing ECO guidance capabilities. This tutorial will review PrimeTime’s latest enhancements to final stage ECO timing closure and how to use these capabilities together effectively. You will learn how PrimeTime's ECO flow compliments IC Compiler’s new Minimal Physical Impact (MPI) capability to achieve fast, convergent ECOs.

Synopsys Products:
PrimeTime

Target audience:
Design Engineer, STA Engineer

Using Mode-Merging to Reduce Scenarios Required for Timing Closure and Signoff
Brad Lee - Synopsys
Learn how PrimeTime mode merging reduces scenarios for timing analysis and implementation to improve turn-around-time and resource requirements. This tutorial will focus on using PrimeTime mode merging to reduce multiple mode constraints into a smaller set of merged constraints, while reducing run time and memory, and maintaining signoff QoR. Topics will include PrimeTime mode merging – a technical overview and Using PrimeTime mode merging to reduce scenarios for ECO and signoff.

Synopsys Products:
PrimeTime

Target audience:
Design Engineer, STA Engineer


TB3 - IP and Ecosystem
UMC Advanced IP - SOC Design
Ted Kao, UMC
Synopsys Tools Used:
DesignWare IP

Target Audience:
Validation Engineer, Design Engineers, System Engineer

HDMI 2.0 & MHL 2.0: The Future of Multimedia Connectivity
Manmeet Walia - Synopsys
As consumer electronic devices become more multimedia intensive, connectivity protocols such as HDMI and Mobile High-Definition Link (MHL) will play a key role in transferring audio/video data to and from these devices. MHL is the new “mobile-to-TV” protocol that allows content on mobile devices to be displayed on high-definition televisions and displays, while simultaneously charging the device. This tutorial explains the technical features of the MHL interface and how it can be integrated into an SoC to enable linking of mobile devices to HD displays through a single cable, utilizing existing connections. In addition, we will discuss how the latest enhancements to the HDMI specification address the need for increased bandwidth to accommodate higher resolutions and broader video timing support.

Synopsys Tools Used:
DesignWare IP

Target Audience:
Validation Engineer, Design Engineers, System Engineer

Considerations for Timing Budgets for DDR4 Interfaces
William Chen - Synopsys
Introduction for DDR interfaces, review of SI and timing budgets, and Synopsys Signal Integrity Report Service

Synopsys Tools Used:
DesignWare IP

Target Audience:
Validation Engineer, Design Engineers, System Engineer


TB4 - VIP/Verification
Migrate from DWVIP to Discovery VIP
Debra Lin - MediaTek
With the increase in design complexity, the bus fabric is also getting more and more complicated. To meet industry-standard specifications and shorten the time-to-market, VIP (Verification IP) selection is important. Currently, Mediatek's bus fabric verification environments are developed using VMM including DW VIP (DesignWare VIP), which provides good stability, and has been successfully used in more than 10 projects for more than 3 years.. In 2012 Synopsys announced a new generation Discovery VIP written entirely in SystemVerilog and fully supporting UVM. This new generation VIP provides features for easier debugging, more configuration flexibility, better coverage collection and better performance. In VIP selection stability and performance are both important for verification. Minimizing the side impact in the migration from DW VIP to Discovery VIP is a major concern. The paper addresses the approach on how to migrate, the benefit analysis and the spending effort throughout the transition.

Synopsys Tools Used:
DesignWare VIP, VCS

Target Audience:
Verification Engineer, Design Engineer

HW/SW Verification and Debug with VCS and Verdi3
Alex Wakefield - Synopsys
Synopsys Tools Used:
DesignWare VIP, VCS, Verdi

Target Audience:
Verification Engineer, Design Engineer

Achieving Performance Verification of ARM Processor-based SoCs Optimizing and Validating the Performance of Your AMBA® based Interconnect
Tom Lin - Synopsys
Synopsys Tools Used:
DesignWare VIP, VCS

Target Audience:
Verification Engineer, Design Engineer


Wednesday, September 11, 2013
9:10 AM - 10:00 AM
Welcome and Synopsys Keynote
Accelerating Innovation in Electronics That Impact Everything, Everyone, Everywhere
Paul Lo, Senior Vice President & General Manager, Analog/Mixed Signal Group, Synopsys
Technical innovation is increasingly impacting everyone, everything, everywhere. Today’s SoCs are transforming the electronics industry by integrating a staggering amount of functionality into extremely cost-effective, high-performance, low-power, single-chip implementations. In the ongoing quest to maximize functionality and feature sets, these SoCs contain a significant amount of high speed SRAMs, I/O subsystems and analog blocks. The combination of increased Analog Mixed-Signal content and nanometer process technologies require new innovations in AMS design and verification. Paul’s presentation will provide insights on how to accelerate innovation in the era of electronics that are increasingly impacting everyone, everything, everywhere.


Wednesday, September 11, 2013
1:30 PM - 3:00 PM
WA1 - HPC and Advanced Technology
Implementation Experience Sharing with UMC 28HLP
Ko Wen Wu - UMC
Target audience:
High performance core designers, back-end and front-end implementation users

Preparing for the Next Decade
Henry Sheng - Synopsys
Even though IC designers around the world have made IC Compiler the clear leader for place-and-route, user feedback tells us there is still more we could do to ease the burden of the Physical Design engineer. Perpetually increasing chip complexity, shrinking market-introduction windows and ever-increasing demands on performance make Physical Design one of the most challenging tasks for an IC design house. This session will present the Synopsys vision for what it is going to take to meet these challenges.

Synopsys Tools Used:
IC Compiler

Target Audience:
Physical Implementation Engineer


WA2 - Synthesis
Fast And Reliable PPA (Power/Performance/Area) Exploration by DC Explorer
Der-Hua Meng - Realtek
It is not easy to define the design specification. There are many uncertainties to be considered, including market competitiveness and product profitability. Sometimes designers have to make an important decision about how to select a right technology library when they initialize a new project. The key factors of their decision involve the performance and cost of the technology library.

If we can get the design information of Power/Performance/Area using a new technology library early in the design cycle, then we can finalize the design specification and implement the design as soon as possible.

With the use of DC Explorer, the necessary information can be derived in a shorter period of time, which in turns accelerates the acquisition of an accurate specification and the desired library.

Synopsys Tools Used:
Design Compiler

Target Audience:
Implementation Engineer

DC-Explore Experience Sharing
Cheng Kai Huang - Ali
With the improvement in process technology, the number of cell on ICs has increase dramatically making the run time of implementation and verification a critical issue.

We cannot check multiple versions of the RTL design and the effect of modifying timing constraint setting in the time available. Large scale design implementation also results in the increased iteration time from synthesis to floorplan. DC-E is used to improve the flexibility in design early stage, and to shorten the design cycle.

In the session, we will discuss the change of the flow, and the correlation of timing/area compared to DC-Ultra

Synopsys Tools Used:
Design Compiler

Target Audience:
Implementation Engineer

Formality-Ultra
Richard Su - Synopsys
Synopsys Tools Used:
Formality, Design Compiler, IC Compiler

Target Audience:
Implementation Engineer. Design Compiler, IC Compiler and Formality Users


WA3 - System
Experiences on System Integration with the CoStart for VDKs
Louis Huang - ITRI
The integration of increasingly complex hardware and software is significantly challenging, and traditional methods of step-by-step development often fail to meet tight schedules. To improve the productivity of system-level design, advanced Electronic System-Level (ESL) methodology provides solutions.

Memory and GPU are two key IPs on modern systems, which are critical to the performance. When integrating Transaction-Level Modeling (TLM) IPs with the Synopsys CoStart platform, there are several issues to be dealt with, including IP TLM interfaces design, and software porting (e.g., graphics library). In this presentation we will address these issues with two case studies.

Synopsys Tools Used:
ESL Solution

Target Audience:
System Engineer

The Design of Embedded Vision Systems
Jiff Kuo, Synopsys
In this session we will introduce the Embedded Vision Development System (EVDS), an integrated solution that accelerates the design of custom processors for embedded vision applications. EVDS is based on the Processor Designer tool set and HAPS FPGA-based prototyping system from Synopsys.

Synopsys Tools Used:
Embedded Vision Development System (EVDS)

Target Audience:
System Engineer


WA4 - Custom Design Using Laker
TSMC iPDK Update
CW Wei - TSMC
Row based digital design with straight routing style and tracing hierarchical are the characters in DRAM layout. Due to the limitation of routing layers and shrinking die size, physical design always faces a schedule conflict. Laker CDPR now plays a role in our layout schedule, helping to reduce our DRAM design time.

CDPR has been successful in routing a digital hierarchical block and reducing our schedule from 3 months/3 people to 3 months/1 person. In this session, Nanya will share how we speed up the layout and control CDPR to meet our specifications.

Synopsys Tools Used:
Laker

Target Audience:
Custom Design Engineer

Advanced-Node Layout Requirements
Lucas Chen - Synopsys

Laker CDPR (Custom Design Place and Route) on DRAM
Frank Yu - NTC
Synopsys Tools Used:
Laker

Target Audience:
Custom Design Engineer

LakerBlitz - Chip Level Layout Editor
Hsin-Po Wang - Synopsys
Synopsys Tools Used:
Laker

Target Audience:
Custom Design Engineer


WA5 - Debugging with Verdi
Create Power Intent and Verify Power Policy by Verdi3
Chunyi Lin, MediaTek
To minimize power consumption, designers usually plan several power domains and define control sequences for tuning the behaviors of the power domains. Especially when process technology goes to the nanometer level, the leakage current worsens the power consumption problem. However, low power verification requires a UPF file as a reference. Manually adding power instances without the UPF file is adds complexity to verification. Being able to quickly create the UPF file and check power policy is helpful and improves the efficiency of designers. In this paper, we demonstrate how to automatically generate the power intent UPF file by using Synopsys Verdi3(VIA) as well as how to check the missing or mismatched power policy which might cause functions to fail or unexpected power consumption by using Verdi3(powerMap). With Verdi3, we can decrease manual efforts by automatically creating the UPF file, checking Power policy and increase overall verification efficiency and confidence.

Synopsys Tools Used:
Verdi

Target Audience:
Design Engineer, Verification Engineer

How do you Debug Power Related Issues? – A Methodology for Low Power Debug
Archie Feng - Synopsys
Synopsys Tools Used:
Verdi

Target Audience:
Design Engineer, Verification Engineer

Realize Your Own Ideas with Rich APPs Inside Verdi's VIA Toolbox
Rich Chang - Synopsys
Synopsys Tools Used:
Verdi

Target Audience:
Design Engineer, Verification Engineer


Wednesday, September 11, 2013
3:30 PM - 5:30 PM
WB1 - Physical Implementation
Time-to-Result Using Lynx on ARM Cortex A9-based SoC Design with UMC40LP
Synopsys Tools Used:
IC Compiler

Target Audience:
Physical Implementation Engineer

Design with Non-Planar CMOS and Double-Patterning
Synopsys
In this tutorial you will learn what transaction-level verification means in general and specifically how it applies to the ZeBu-Server emulation platform. Transactors offer a unique combination of performance, accessibility, flexibility and scalability, while providing a realistic system-level test environment for the DUT. Transactors allow you to quickly build a high-speed system-level Virtual Platform by surrounding your emulated DUT with Virtual Components that interact with its various interfaces.

The tutorial will describe the inner workings of a transactor with emphasis on the advantages and tradeoffs compared to alternative approaches, including the traditional in-circuit emulation (ICE) approach. Step-by-step instructions for creating a transactor will be provided, including an introduction to a high-level SystemVerilog behavioral language/compiler, called ZEMI3, conceived for automating the generation of a transactor. Closing the session, a practical application in the wireless space will be described in detail including steps to compile a design into the ZeBu-Server.

Synopsys Tools Used:
ZeBu-Server, ZEMI3

Target Audience:
Design Verification Leads and Managers

Routing a Synopsys DDR PHY’s Matched Pair Signals Using Galaxy Custom Router and ICC (with Co-Design), Within Lynx
Synopsys Tools Used:
IC Compiler

Target Audience:
Physical Implementation Engineer


WB3 - Emulation and FPGA-Based Prototyping
Emulator Virtual Platform Design Methodology
Josh Hsu - MediaTek
SoC architecture is becoming more and more complex, including multi-core, high quality multimedia and 4G. It’d be a critical issue about how to identify our performance SPEC at an early stage. We setup a methodology of combining Zebu with Platform Architect and would give you a sharing.

Synopsys Tools Used:
ZeBu-Server

Target Audience:
Design Verification Leads and Managers

Complex SoC Prototyping Using Xilinx Virtex 7 Based HAPS-70 Systems
Michael Posner, Jay Chiang - Synopsys
The challenge of Implementing complex mobile multi-media SOCs onto FPGA based platforms for prototyping and S/W development activities has been assisted with the introduction of the latest multi-die Xilinx Virtex 7 FPGAs which extend the individual device capacities to around the 12M ASIC gate mark while which improving I/O and Core performance. This presentation originally developed by Paul Robertson of Broadcom outlines the process of preparing such a complex SOC for Implementation on the latest Virtex 7 based HAPS-70 Prototyping Systems from Synopsys, handling new challenges related to making best use of the multiple-die FPGAs and then bringing-up the Prototyping Systems to be functional whilst ensuring Optimal System Performance.

Synopsys Tools Used:
HAPS

Target Audience:
Design Verification Leads and Managers

Quick FPGA Prototype Platform Bring-up and Design Debug
Freddy Lin - Synopsys
Synopsys Tools Used:
HAPS

Target Audience:
Design Verification Leads and Managers


WB4 - Custom Design Using Laker
Laker FPD Application on e-Paper Design
Chun-Wei Chang - Eink
Synopsys Tools Used:
Laker

Target Audience:
Custom Design Engineer

iPDKs: A Thriving PDK Standard
Jingwen Yuan - Synopsys
Synopsys Tools Used:
Laker

Target Audience:
Custom Design Engineer

UMC iPDK Program: Development and Validation
Anderson Huang - UMC
Synopsys Tools Used:
Laker

Target Audience:
Custom Design Engineer

Powerful and Comprehensive Devices in Laker
Lucas Chen - Synopsys
Synopsys Tools Used:
Laker

Target Audience:
Custom Design Engineer


WB5 - Debugging with Verdi
Exploring Protolink: Effective Debugging from Firmware to Hardware
Owen Chang - Sonix
Traditional FPGA debugging is very time-consuming with plenty of limitations including probe number, signal frequency and capture length. As digital design and firmware are getting more complex, it is increasingly difficult to identify whether a problem arises in the firmware or the hardware or even to locate the waveform for analysis. This paper reviews the key benefits of adopting ProtoLink during development of a USB3.0 project. ProtoLink has been proven to be an effective debugging tool for both firmware and hardware. More importantly, the information it provides allows engineers to further analyze problems at the early stage of debugging and shorten the development cycle. We will first describe how to use ProtoLink to trace firmware flow. Then we will demonstrate how to combine other debug tools ( Protocal Anaylzer) with ProtoLink for co-verification. Finally, we will describe how it has been used for analyzing PIPE 125MHz interface.

Synopsys Tools Used:
ProtoLink

Target Audience:
Design Engineer, Verification Engineer

Customer Case Study: Validation of ARM Systems using FPGAs and ProtoLink
Howard Mao - Synopsys
Synopsys Tools Used:
ProtoLink

Target Audience:
Design Engineer, Verification Engineer

Verdi Transaction Based Debugging for SoC Designs
Rich Chang - Synopsys
Debugging the hardware of an SoC design is a challenging task by itself and it's made even more difficult when the designer needs to correlate the software "events" with the hardware "transactions" to debug a problem. A simple command from the software program can turn into hundreds of transactions in hardware making it a nightmare to manage and browse. In addition, these transactions can be zero delay, overlap one another, and be interleaved, which are difficult to view using a traditional waveform viewer. In this tutorial, you'll learn how to maximize your productivity by using Verdi's Transaction Based Debugging technology to correlate and visualize the software "events" with the corresponding hardware “transactions" and browse, trace, and debug transactions. You’ll learn how the tool's vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.

Synopsys Tools Used:
Verdi3

Target Audience:
RTL Verification Engineers, Logic Design Engineers, SoC Engineers

Functional Signoff: A Process for Measuring and Improving Verification Quality to Ensure Bug-Free Designs
Alex Wakefield - Synopsys
Verification engineers continually struggle with questions related to verification effectiveness. Do my test scenarios exercise the functionality sufficiently? Is my checker and assertion infrastructure complete? Traditional coverage techniques only determine if you've executed all lines of code or whether you've exercised all important functionality that you have defined. This analysis may not be sufficient and there is no objective measure of "completeness". This session will explain how Certitude Functional Qualification augments traditional coverage to provide unique insight into the quality of simulation and formal verification environments. Certitude's proprietary mutation-based process inserts "artificial bugs" or faults into the design and measures the ability of the verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality and identify specific holes and weaknesses that can allow RTL bugs to slip through the process.

Synopsys Tools Used:
Certitude Functional Qualification Solution

Target Audience:
Verification Engineers and Managers interested in a functional signoff capability