SNUG Silicon Valley 2014 Proceedings


User Papers and Presentations
MA-03 Low-Power Implementation
Low-Power Design in the FinFET Technology
Author(s): Benjamin Mbouombouo - LSI Corporation
PaperPresentation

Low-Power Implementation of Complex MIPS Cores
Author(s): Maya Mohan, Nagesh Sakhamuru - Imagination Technologies
PaperPresentation

MA-04 Circuit Simulation
CustomSim-Based Comprehensive EM/IR Analysis, Visualization, and Violation Correction
Author(s): Gaurang Chaudhari, Sateesh Chandramohan, Prashant Lokeshwar - ARM; Danny Cheng, Darren Hsu - Synopsys, Inc.
PaperPresentation

MA-07 Signoff - Physically Aware ECO Flow
An Investigation of the Efficacy of PT-ADV in a Non-Synopsys PnR Flow
Author(s): Jim Fong - Rambus; Po Leung - Synopsys, Inc.
PaperPresentationSession Recording

MB-03 Physical Implementation
Cloning DDR4 RDL Routing With Galaxy Custom Router (GCR) Editing Environment
Author(s): Jiankang Wang, Young Koog - Samsung; Denis Goinard, Amit Patel, Nabil Yazdani - Synopsys, Inc.
PaperPresentation

Implementation of Multi-Source Clock Tree Synthesis
Author(s): Yina Tang, Tian Yang - NVIDIA; Yashpal Bhola - Synopsys, Inc.
PaperPresentation

MB-04 Circuit Simulation
Extracting Impulse Responses in HSPICE
Author(s): David Banas - Altera Corporation
PaperPresentationSession Recording

Verification Methodology for Array-Based Memories
Author(s):
PaperPresentation

MB-05 Verification IP
Accelerated Verification of ARM-Based SoCs Using Highly Reconfigurable VIP and Custom Scoreboard
Author(s): Bharti Verma, Neel Sonara - Broadcom Corporation; Frank Gerbig, Amir Nilipour - Synopsys, Inc.
PaperPresentation

MB-06 Advanced System Verilog Constraints
Interchangeable SystemVerilog Random Constraints
Author(s): Jeremy Ridgeway - LSI Corporation
PaperPresentation

Reverse Gear: Re-Imagining Randomization Using the VCS Constraint Solver (1st Place - Best Paper, Technical Committee Award)
Author(s): Bryan Morris, Paul Marriott - Verilab Canada Inc.; Jonathan Bromley - Verilab UK Ltd.
PaperPresentation

MB-07 Leakage Recovery & ECO
Signoff Leakage Recovery
Author(s): Helen Liang, Subash Sukumaran - Toshiba America Electronic Components, Inc.
PaperPresentationSession Recording

Utilizing Signoff Based Multi Scenario ECO to Solve Unique Design Challenges
Author(s):
PaperPresentation

MB-09 HAPS
Achieving Maximum System Performance on Multi-FPGA designs using HAPS-70 System
Author(s): Kiran Vedanabhatla, Xin Zhao, Padma Nagaraja - SanDisk; Maitrey Makim - Synopsys, Inc.
PaperPresentation

MC-06 Verification Methodology & Productivity
The "X" Factor: Address It in RTL Simulations
Author(s): Imtiyaz Ron, Hari Sharma - Broadcom Corporation; Karim Ameziane - Synopsys, Inc.
PaperPresentation

UVM Transactions: Definitions, Methods, and Usage (3rd Place - Best Paper, Technical Committee Award)
Author(s): Clifford E. Cummings - Sunburst Design, Inc.
PaperPresentation

MC-07 Advanced Signoff and Design
Synchronization and Metastability (1st Place Best Presentation)
Author(s): Steve Golson - Trilobyte Systems
PaperPresentationSession Recording

TA-01 Physical Implementation - Data Flow Analysis
Accelerating Floorplan Creation Using DFA in ICC/DE
Author(s): Charles Tang, Krishna Kumar Gundavarapu - Cisco Systems
PaperPresentation

TA-05 UVM Methodology
A Register Layer Gallimaufry
Author(s): Tim Corcoran - Willamette HDL Inc.
PaperPresentation

How UVM-1.1d Makes the Case for Unit Testing
Author(s): Neil Johnson, Jean-Marc Tremblay - XtremeEDA Corporation
PaperPresentation

TA-06 UVM Methodology
Layering Protocol Verification: A Pragmatic Approach Using UVM
Author(s): Mehul Kumar, Rahul Chauhan, Gurpreet Kaire - Broadcom Corporation; Ravindra Ganti, Subhranil Deb - Synopsys, Inc.
PaperPresentation

Methodology for Command Line Control of Configurations and Sequences Using Synopsys Discovery I2C VIP
Author(s): Mohammad Rizwan - Broadcom Corporation; Gaurav Chugh, Amir Nilipour – Synopsys, Inc.
PaperPresentation

TA-11 Design Compiler Lunch and Learn
Shrinking Design Area and Schedules for Established and Emerging Nodes
Author(s):
Presentation

TA-12 Verification Lunch and Learn
Addressing the Challenges of SoC Verification
Author(s):

TB-01 High-Performance Core Implementation
Performance-Focused Implementation of a Dual-Core ARM Cortex-A57 Processor at the 20nm and 16nm Process Technology Nodes
Author(s): Saran Kumar Seethapathi, Joshua Garrett, Fang Wang - Broadcom Corporation
Presentation

TB-02 Low-Power Design
Full-Chip Low-Power Static Verification using Verdi Signoff-LP (2nd Place Best Presentation)
Author(s): Debajani Majhi, Leah Clark - Broadcom Corporation
PaperPresentation

TB-03 Test
Achieving Extreme Compression for GPU System on Chip Designs
Author(s): Jon Colburn - NVIDIA
PaperPresentation

Deploying DFTMAX Ultra: Usability is Paramount
Author(s): Renee Logan, Vladimir Kovalev, Anil Moolchandani - SanDisk
PaperPresentation

Implementing Hierarchical DFT Architecture for Ultra Large Designs Using DFTMAX Core Wrapping and Test Scheduling
Author(s): Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Raghavedra Rao - LSI Corporation; Vikas Pissay - Synopsys, Inc.
PaperPresentation

TB-04 Circuit Simulation
Single Executable FineSim Technology for Analog and Full-Chip Simulations, Analyzing Performance, Statistical Variation and Design Violations' Checks
Author(s): Raed H Sabbah - Micron Technology, Inc.
PaperPresentationSession Recording

TB-07 Library Modeling for STA: POCV Variation and Library Cell Validation
Advanced Node Random Device Variability Modeling and Margining in Characterization and STA (2nd Place - Best Paper, Technical Committee Award)
Author(s): Tamer Ragheb, Steven Chan, Ning Jin, Richard Trihy - GLOBALFOUNDRIES
PaperPresentationSession Recording

TB-10 Systems
Application of Virtual Prototypes, Current and Future
Author(s): Robert Kaye - ARM
PaperPresentation

TC-05 Verification Coverage Closure
Full-Chip Application of an Automated Code Coverage Closure Methodology (3rd Place Best Presentation)
Author(s): Syed Suhaib, Keegan Brown, Prosenjit Chatterjee - NVIDIA; Ashvin Dsouza, Abhishek Muchandikar - Synopsys, Inc.
PaperPresentationSession Recording

Functional Coverage Database Using UCAPI
Author(s): Robert Goldman - NVIDIA
PaperPresentation

TC-06 Power Estimation and Coverage
Auto Line and Conditional Functional Coverage for DV Code
Author(s): Gaurav Vaidya - Cisco Systems
PaperPresentation

Early Vector Based Dynamic Power Estimation
Author(s): Eshwar Parigi - Broadcom Corporation; Ravi Chopra - Synopsys
PaperPresentation

TC-07 Timing Closure & Characterization for Macros
20nm Timing Characterization and Signoff of Advanced FPGA Custom Circuits Using NanoTime
Author(s): Gurdarshan Kalra, Fu-Hing Ho - Xilinx, Inc.; Sahil Bargal - Synopsys, Inc.
PaperPresentation

Technology Keynote
Innovation - The Thrill and Thorns of Navigating Through Uncharted Territories
Author(s): Dr. Sebastian Thrun, Founder and CEO of Udacity, VP and Research Fellow at Google, and Professor of Computer Science at Stanford University

WA-03 Formal Verification and Functional Qualification
Formal Verification of GPU Level of Detail Datapath Block
Author(s): Kesava R. Talupuru - Qualcomm
PaperPresentation

Integration of Certitude Coverage Collection
Author(s): Keegan Brown - NVIDIA
PaperPresentationSession Recording

WA-07 Lynx Design System Lunch and Learn
Using Lynx Design System Automation to Accelerate Design Processes - SoC Flow, Custom Design Correlation and Regression Throughput
Author(s): Steve Cline - Altera Corporation; Eduardo Flores, Lydia Lee, Terry O'Brien - Synopsys, Inc.

WC-08 Verdi Interoperable Apps (VIA) Developers Forum
WC-08 Verdi Interoperable Apps (VIA) Developers Forum
Author(s): (1:45 pm – 6:00 pm)

Publication Only
Publish Only
Ease of Transition and Evaluation of ICC for Established Nodes
Author(s): Kai Chiou - Integrated Device Technology; Krishna Devineni - Synopys
Paper

Faster Timing Closure with PrimeTime Physically-Aware ECO on 20nm Technology Multi-Scenario Designs
Author(s): Shelly Xia - Altera Corporation; Harry Yu - Synopsys, Inc.
Paper

Handling Design Variability During Timing Signoff
Author(s): Alexander Tetelbaum - Abelite Design Automation
Paper

Tutorials
MA-01 ICC Update
IC Compiler 2013.12 Release Highlights
Author(s): Mohan Aswathnarayan - Synopsys, Inc.
TutorialVideo

MA-02 Physical Implementation
Routing DDR PHY Matched Length Signals Using Galaxy Custom Router
Author(s): Maged Attia - Synopsys, Inc.
TutorialVideo

MA-04 Circuit Simulation
Low-Power and Simulation Performance in Mixed-Signal
Author(s): Dave Cronauer - Synopsys, Inc.
Tutorial

MA-07 Signoff - Physically Aware ECO Flow
PrimeTime ECO - Now Physically Aware
Author(s): Troy Epperly - Synopsys, Inc.
TutorialVideo

MA-08 DDR4 and LPDDR4 IP
Faster DRAM: What You Need to Know About LPDDR4-3200, DDR4-3200, and Next-Generation DRAM
Author(s): Graham Allan, Mark Greenberg - Synopsys, Inc.

MA-09 HAPS
Automating SoC RTL to Operational Prototype
Author(s): Ajay Jagtiani, Joseph Marceno - Synopsys, Inc.
Tutorial

MB-01 DC Update
Design Compiler 2013.12 Release Highlights
Author(s): Jim Argraves - Synopsys, Inc.
TutorialVideo

MB-02 Custom Physical Implementation
Best Practices for Custom Layout Productivity: How Laker Users Have Cut Layout Time in Half
Author(s): Neel Gopalan - Synopsys, Inc.
Tutorial

MB-09 HAPS
High-Speed Reliable Interconnects on HAPS-70 Systems
Author(s): Srikanth Annangi - Synopsys, Inc.
Tutorial

MC-01 Advanced Physical Implementation
Innovative Technologies in Physical Implementation for Building Leading Edge SoCs
Author(s): Saleem Haider, Neeraj Kaul - Synopsys, Inc.

MC-03 Frontend Implementation
ECO Implementation Assistance and Advanced Debugging Using Formality Ultra
Author(s): David Low - Synopsys, Inc.
TutorialVideo

MC-04 Circuit Simulation
Custom WaveView for Advanced Analysis, Debugging and Measurement Automation
Author(s): Manu V Pillai - Synopsys, Inc.
Video

Signal Integrity Analysis of High-Speed Serial Links Using HSPICE
Author(s): Tetsuhisa Mido - Synopsys, Inc.
TutorialVideo

MC-05 Verification IP
Advanced Verification Techniques Applied to an ARM AMBA 5 Protocol-Based SoC
Author(s): Tushar Mattu - Synopsys, Inc.
TutorialVideo

MC-07 Advanced Signoff and Design
PrimeTime Advanced Waveform Propagation
Author(s): Carol Scemanenco - Synopsys, Inc.
TutorialVideo

MC-08 PCI Express IP
Yes! You Can Use PCI Express for Mobile and Enterprise SoCs
Author(s): Scott Knowlton, Richard Solomon - Synopsys, Inc.

MC-09 HAPS
Putting IP and Subsystem Prototyping on the Fast Track
Author(s): Mick Posner, Antonio Costa - Synopsys, Inc.
Tutorial

TA-01 Physical Implementation - Data Flow Analysis
Using Data Flow Analysis for Floorplanning
Author(s): Rajiv Dave - Synopsys, Inc.
Tutorial

TA-02 In-Design Physical Implementation/Verification
Managing Metal Fill and Its Impact on Your Design
Author(s): Dan Marolda - Synopsys, Inc.
Tutorial

TA-03 Test
Low DPPM and Low Cost Testing for All Process Nodes and FinFETs
Author(s): Adam Cron - Synopsys, Inc.
Tutorial

TA-04 Circuit Simulation
Circuit Simulator Release Update: The Solution for Tomorrow's Challenge
Author(s): Tom Hsieh - Synopsys, Inc.
TutorialVideo

TA-09 USB 3.1 IP
Integrating USB 3.1 in Your Next SoC Design
Author(s): Morten Christiansen - Synopsys, Inc.

TA-10 Systems
Performance Analysis for the Synopsys DesignWare Universal DDR Memory Controller Using Synopsys Platform Architect MCO
Author(s): Asheesh Khare - Synopsys, Inc.
TutorialVideo

Using Platform Architect MCO to Optimize Your Micro-Server SoC Architecture for Performance and Power
Author(s): Gururaj Rao - Synopsys, Inc.
TutorialVideo

TB-02 Low-Power Design
Verdi Signoff-LP: Next-Generation Low-Power Static Verification
Author(s): Narayana Koduri - Synopsys, Inc.
TutorialVideo

TB-04 Circuit Simulation
A Framework for Automating Circuit Simulations
Author(s): Sandeep Dechu - Synopsys, Inc.
TutorialVideo

TB-05 Simulation Acceleration with ZeBu
Verification of SoC Designs with ZeBu HW Emulator
Author(s): Gwyneth Sauceda - Synopsys, Inc.
Tutorial

TB-06 Advanced Verification Debug with Verdi
Going Beyond the Waveform: Advanced Debug Techniques in Verdi
Author(s): Bindesh Patel, Archie Feng, Alex Wakefield - Synopsys, Inc.
Tutorial

TB-07 Library Modeling for STA: POCV Variation and Library Cell Validation
Automating PrimeTime vs. HSPICE Validations
Author(s): Eduardo Flores, Krishnakumar Ramakrishnan - Synopsys, Inc.
TutorialVideo

TB-08 Custom and Advanced Node Parasitic Extraction
Solving Extraction Challenges at 10nm
Author(s): Bari Biswas - Synopsys, Inc.

TB-09 High Speed PHY IP
Addressing the Challenges of Multi-Protocol High Speed PHY Design
Author(s): Rita Horner, Paul Hua - Synopsys, Inc.

TB-10 Systems
Using Synopsys VDKs for Developing UEFI and Linux Drivers for Synopsys DesignWare IP Interfaces and ARMv8 Processors
Author(s): Mojin Kottarathil - Synopsys, Inc.
Tutorial

TC-04 Circuit Simulation
Transistor Level Static Circuit Analysis, an ERC Solution for Deep Sub-Micron Low-Power Custom Digital, Memory and Analog IP Designs
Author(s): Jason Hwan - Synopsys, Inc.
TutorialVideo

TC-07 Timing Closure & Characterization for Macros
Differential Clock and Topology Handling in NanoTime
Author(s): Norb Heindl - Synopsys, Inc.
TutorialVideo

TC-09 Compound Floating Point Units
Designing Compound Floating Point Units with an Efficient Pre-Validated IP Based Approach
Author(s): Alexandre Tenca - Synopsys, Inc.

TC-10 Coverity
Introduction to Coverity
Author(s): Dr. Andreas Kuehlmann - Coverity; John Chilton - Synopsys, Inc.

WA-01 Advanced Physical Implemenation
Emerging Node Design with IC Compiler
Author(s): Neil Moore - Synopsys, Inc.
Tutorial

WA-04 Verification Closure
Verification Closure Flow
Author(s): Michael Horn - Synopsys, Inc.
Tutorial

WA-05 FPGA Synthesis
Effortless Xilinx Vivado IP Flows
Author(s): David Lopez, Jon Nagareda - Synopsys, Inc.
TutorialVideo

WB-01 Low-Power Implementation
Low-Power Design Implementation
Author(s): Gloria Chen, Jeffrey Lee - Synopsys, Inc.
Tutorial

WB-02 Test
Automated Volume Diagnostics for Accelerated Yield Learning in Advanced Nodes
Author(s): John Kim, John Kirkland - Synopsys, Inc.
Video

WB-04 Verification Environment Qualification
Certitude Functional Qualification: Applications in the C/C++ Domain
Author(s): Marty Rowe - Synopsys, Inc.
TutorialVideo

WB-05 VCS Update
VCS 2014.03 Release Highlights
Author(s): Rohit Narkar, Latha Venkatachari - Synopsys, Inc.
Tutorial

WB-06 FPGA Synthesis
Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goals
Author(s): Paul Owens, Shankey Srinivasan - Synopsys, Inc.
TutorialVideo

WC-01 High Level Synthesis
Using Synphony C Compiler to Speed Implementation of Image Processing IP
Author(s): Craig Gleason - Synopsys, Inc.
Tutorial

WC-02 Test
SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Author(s): Arun Kumar - Synopsys, Inc.
Video

WC-04 Static Low-Power Verification
Increase Low-Power Verification Productivity
Author(s): Ajay Thiriveedhi - Synopsys, Inc.
TutorialVideo

WC-06 FPGA Synthesis
Analyze and Report on Your FPGA Design with Ease Using Tcl
Author(s): Maitrey Makim - Synopsys, Inc.
TutorialVideo

WC-07 Storage and OS Impact on EDA Tools
OS Roadmap for EDA Design
Author(s): Richard Paw - Synopsys, Inc.
TutorialVideo

Panel Presentation
TA-07 Signoff- FinFET & Process Variation Panel
The "Real World" Weighs in on FinFET and Process Variation Impact
Author(s): Brian Cline - ARM; Glen McDonnell - Broadcom; Tom Quan - TSMC; Susan Wu – Xilinx; Jacob Avidan, Bari Biswas - Synopsys, Inc.
Presentation

TC-01 Advanced Physical Implementation
R&D Panel: Get the Inside Track in Physical Implementation
Author(s): Michael Jackson, Mark Bales, Pei-Hsin Ho, Aiqun Cao, Thomas Andersen - Synopsys, Inc.

Lunch and Learn Presentations
MA-10 Implementation Lunch and Learn
Winning the Productivity Challenge - Tapeout Success at the Leading Edge of IC Design
Author(s):
Video

MA-11 IP Lunch and Learn
Physical IP Development on FinFET - There's Nothing Planar About It!
Author(s): Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Embedded Memories and Logic Libraries at Synopsys

User Presentation
MB-05 Verification IP
UVM Verification Using Verification IP
Author(s): Thomas Bodmer, Karl Whiting - AMD; Vijay Akkaraju - Synopsys, Inc.

MB-08 Embedded Memories and Logic Libraries
Hardening DSPs for Performance and Power with DesignWare Logic Libraries and Embedded Memories
Author(s): Ran Snir - CEVA

TA-02 In-Design Physical Implementation/Verification
In-Design Flows for Faster Tapeouts
Author(s): Anand Patil - Aquantia
Presentation

TB-01 High-Performance Core Implementation
AMD Shares Highlights from Their Successful Tapeout of an ARM Cortex-A57 MPCore Processor
Author(s): Samit Chakraborty, Satyavathi Akella, Sam Huynh, Manoj Rehani, Phillip Young - AMD
Presentation

Speed, Power, and Complexity Exploitation and Exploration for Mobile GPU
Author(s): Alex Chang - MediaTek
Presentation

TB-05 Simulation Acceleration with ZeBu
Deploying ZeBu Transaction-Based Verification on Imagination GPUs
Author(s): Colin McKellar - Imagination Technologies; Fabian Delguste - Synopsys, Inc.

TB-07 Library Modeling for STA: POCV Variation and Library Cell Validation
Parametric OCV (POCV): A Viable and Recommended Alternative to AOCV for Variation Aware Static Timing Analysis
Author(s): Khaled Heloue - AMD
PresentationVideo

TB-08 Custom and Advanced Node Parasitic Extraction
GLOBALFOUNDRIES PDK Development and Tool Qualification
Author(s): Venkat Ramasubramanian - GLOBALFOUNDRIES

NVIDIA's Advanced Node Custom Design Experience with StarRC
Author(s): Sudhir Agarwal - NVIDIA

TC-08 Signoff Physical Verification
High-Performance Physical Verification of Advanced Designs at NVIDIA
Author(s): Sudhir Agarwal - NVIDIA

LVS Ease of Use and Debugging
Author(s): Dwight Ly - Altera Corporation
Presentation

WA-02 Test
Accelerate SoC Testing Using Synopsys' DesignWare STAR Hierarchical System and DesignWare STAR Memory System
Author(s): Arnaud Wenzel - ST
Video

WA-06 High Performance Computing for Silicon Design
High-Performance Computing for Silicon Design
Author(s):
Presentation

WB-07 Compute Farm Resource Selection and Management
CPU Choice, Server Architecture, and BIOS Settings for EDA Tool Performance
Author(s): Kamran Casim - HP; Manish Neema, Glenn Newell - Synopsys, Inc.
Presentation

Fair Sharing of Compute Resources in a Complex Enterprise Environment
Author(s): Omar Hassaine - Univa; Joe Fu - Synopsys, Inc.
Presentation

WC-07 Storage and OS Impact on EDA Tools
Accelerating VCS Verification for Faster Time-to-Market (TTM) Through Scalable Parallel Infrastructure
Author(s): Bikash-Roy Choudhury - NetApp
Presentation