SNUG Silicon Valley 2013 Proceedings

Speeches
Keynote Address 1
Massive Innovation and Collaboration into the "GigaScale" Age!
Author(s): Aart de Geus, Chairman and co-CEO, - Synopsys, Inc.
Video

Keynote Address 2
“From Crystal Ball to Reality – The impact of Silicon IP on SoC Design”
Author(s): Sir Hossein Yassaie, PhD, Chief Executive Officer, Imagination Technologies Group
Video

Keynote Address 3
Collaborate to Innovate – A Foundry's Perspective on Ecosystem
Author(s): Dr. Cliff Hou, Vice President, Research & Development, TSMC

User Papers and Presentations
MA02 - Challenges and Strategies for Advanced Designs
High Performance SoCs: Effective Strategies for achieving Optimal Performance, Power & Faster Design Closure
Author(s): Santhosh Pillai, Sarita Baswant, Ashwani Gupta, Prasanth Koduri, Vi Nguyen, Sowjanya Mukka - Samsung Semiconductors
PaperPresentation

Routing at 20nm - It is Challenging but Achievable
Author(s): Chad Hale - ARM
Presentation

MA04 - Verification with OVM/UVM Methodologies
OVM/UVM Scoreboards - Fundamental Architectures
Author(s): Cliff Cummings - Sunburst Design, Inc.
PaperPresentation

Reset Testing Made Simple with UVM Phases
Author(s): Ben Chen, Brian Hunter - Cavium, Rebecca Lipon - Synopsys
PaperPresentation

MA06
MA06-A "No Man's Land" - Constraining Async Clock Domain Crossings (3rd Place - Best Paper, Technical Committee Award)
Author(s): Paul Zimmer - Zimmer Design Services
PaperPresentation

MA06-B
MA06-B Efficient Timing Constraint Analysis and Debug using PrimeTime-GCA (Technical Committee Award Honorable Mention)
Author(s): Peter Lindberg - LSI Corp.
PaperPresentation

MA08 AMS for FinFET and 3DIC
A New SPICE Simulation Approach for 3D IC Integration
Author(s): Susan Wu, Jianlin Wei - Xilinx; Horace Lam - Synopsys
PaperPresentation

Planar MOSFET to FinFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3
Author(s): Tom Mahatdejkul, Ling Chien, Sreenivas Aluru - ARM
PaperPresentation

MB01 ARM GPU Implementation at 20nm
Proving the 20nm Implementation Ecosystem Using an ARM Mali GPU with a Full Galaxy Tool Flow
Author(s): Shawn Hung - ARM
Presentation

MB02 Advanced CTS Methodologies
Holistic Clocking Methodology that Supports Low-Skew (<20ps) and High-Speed (>1.5GHz) Clocking with Low Power for 28nm Designs
Author(s): Anand Iyer, Kedar Kulkarni, Tim Kasper, Abhishek Kumar - Advanced Micro Devices, Inc.; Denise Powell, Chirakala Chinavenkata - Synopsys
PaperPresentation

Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler
Author(s): Can Sitik, Baris Taskin - Drexel University
PaperPresentation

MB06 Optimizing Extraction Performance and Accuracy
Optimizing Extraction Performance: Samsung Success with StarRC Simultaneous Multi-Corner Extraction
Author(s): Santhosh Pillai - Samsung
Presentation

MB08
MB8-A Using IBIS-AMI Models in HSPICE
Author(s): David Banas - Altera
PaperPresentation

MB08-B
MB8-B Top-Down Post Full-Chip Verification for SRAM Boundary Simulation with FinesimPro
Author(s): Garry Tse - SPANSION Inc.; Danny Cheng, Synopsys
PaperPresentation

MC02
MC2-A Floorplanning and Layout Feasibility with Multi-Instance Partitions
Author(s): Sanjay Balasubramanian, Priya Joshi, Pratik Lunavat - Intel Corp.
PaperPresentation

MC02-B
MC2-B Achieving Predictable Timing in ASIC Flow using Design Compiler Graphical/IC Compiler for High Performance Designs
Author(s): Venkataraman Srinivasagam - Cisco Systems Inc.
PaperPresentation

MC03
MC3-A Hardware Redundancy and Design Fault Tolerance and their Applicability to Chip Design
Author(s): Kurt Baty - WSFDB Consulting
PaperPresentation

MC03-B
MC3-B Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification (1st Place - Best Paper)
Author(s): Don Mills - Microchip Technology; Stuart Sutherland - Sutherland HDL, Inc.
PaperPresentation

MC04
MC4-A VISA: A State-Based, Hierarchical, Architecture-Independent Random Test Generation Environment for High-Performance Multiprocessors
Author(s): Neil McKenzie, Michael Sedmak, Adam Snay, Chris Weller - Advanced Micro Devices, Inc.
PaperPresentation

MC04-B
MC4-B Random Stability in SystemVerilog
Author(s): Doug Smith - Doulos, Inc.
PaperPresentation

MC06 Extraction for New Transistor Nodes and Technologies
Double Patterning Aware Extraction Flows For Digital Design Sign-Off in 20/14nm (2nd Place - Best Paper)
Author(s): Adrian Au Yeung, Steven Chan, Hendrik Mau, Rick Monga, Tamer Ragheb, Venkat Ramasubramanian, Richard Trihy - GLOBALFOUNDRIES
PaperPresentation

Planar MOSFET to FINFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3
Author(s): Tom Mahatdejkul, Ling Chien, Sreenivas Aluru- ARM
PaperPresentation

TA04
TA4-A Transaction Based Assertion for Transaction Level Coverage, Property and Protocol Checking
Author(s): Sakar Jain, Thinh Ngo - Freescale Semiconductor, Inc.
PaperPresentation

TA04-B
TA4-B Sub-cycle Functional Timing Verification using SystemVerilog Assertions
Author(s): Anders Nordstrom - Verilab
PaperPresentation

TB04
TB4-A Challenges with Design and Verification of State Retention in a Complex Low-Power SoC
Author(s): Yushi Tian - Broadcom Corp.; Amir Nilipour, Ajay Thiriveedhi - Synopsys
PaperPresentation

TB04-B
TB4-B Formal Verification of Floating-Point Arithmetic Datapath Block
Author(s): Leonard Rarick - Imagination Technologies, Inc. Ajit Limaye - Synopsys
PaperPresentation

TB04-C
TB4-C A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests
Author(s): Richard Tseng - Qualcomm
PaperPresentation

TB06 Leakage Recovery with PrimeTime
Leakage Recovery across Multiple Timing Scenarios
Author(s):
Paper

TB07 SoC Architecture Optimization
SoC Architecture Analysis and Optimization Using Synopsys Platform Architect MCO
Author(s): Tom Ajamian - Analog Devices, Inc.
PaperPresentation

TC01
TC1-A Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High Performance Mobile SoCs - Technical Committee Award, Honorable Mention (Technical Committee Award Honorable Mention)
Author(s): John Biggs, David Flynn, James Myers - ARM
PaperPresentation

TC02 Design Environments using Lynx
Standardized Design Environment and Methodologies Enable Simultaneous Implementation of 28nm Designs on a Single Flow
Author(s): Cyrille Thomas - Bull SAS
PaperPresentation

Using the Lynx Design System to Lower the Cost of Bringing up a New Flow on a New Node
Author(s): Simone Borri, Christian Eichrodt, Pierre-Marie Signe - Abilis Systems; Riccardo Giordani - Synopsys
PaperPresentation

TC03 Small Delay Defect Model and Advanced Debugging Test
Advanced TetraMAX Debugging Techniques for AMD's High-Performance Cores
Author(s): Martin Amodeo, Thomas Clouqueur, Jan Ness - Advanced Micro Devices, Inc.; Tim Ayres, Lori Schramm, Tim Yuan - Synopsys
PaperPresentation

Improving At-Speed Test Quality with the Small Delay Defect Model
Author(s): Jon Colburn, Dheepakkumaran Jayaraman, Bala Tarun Nelapatla, Arvind Vinod - NVIDIA
PaperPresentation

TC06 Mode-Merging using PrimeTime
Automated Mode Merging of Timing Constraints using PrimeTime
Author(s): Harish Aepala, Nick Oleksinski, Bruce Zahn - LSI Corp.
PaperPresentation

TC09 Increasing ARC Performance and Reducing Power
Increasing Performance and Reducing Power through Memory Request Optimization
Author(s): Gregg Recupero - Performance-IP
Presentation

WA05 High Performance Computing
High Performance Computing for Silicon Design
Author(s):
Paper

WA06 Noise Analysis
Digital->Analog Noise Detection (DANDy)
Author(s): Jason Rziha, Vardhini Muralidaran - Microchip Technology
PaperPresentation

Transistor-Level Timing and Noise Analysis of Peripheral Logic of High Speed Memory Design
Author(s): Johnie Au, Sunilkumar Koduru, Jun Li - Cypress Semiconductor; Sahil Bargal - Synopsys
PaperPresentation

WB05 Managing and Optimizing Compute Infrastructure
Advanced Load Balancing and Resource Sharing Solutions
Author(s): Robert Veltman, Vikash Tyagi - SanDisk
PaperPresentation

HP’s Common Engineering Environment for VLSI design
Author(s): Jeff Quigley - Hewlett Packard
Paper

WB06 Characterization Solutions
SiliconSmart Flow for Characterization Production Runs
Author(s): Beibei Ren - NVIDIA; Manjunath B Thimmachary - Synopsys
PaperPresentation

WC05 Storage Optimization
VCS Acceleration Enabled by Storage Optimization
Author(s): Ravi Poddar/ Bikash Roy Choudhury - NetApp
Paper

Publication Only
Clock Path ECO with PrimeTime DMSA fix_eco_timing
Author(s): Anne Yue, Rajeev Srivastava, - Synapse Design
Publish Only

Could Simulation Run Faster and Faster?
Author(s): Roman Wang & Karl Whiting - Advanced Micro Drvices, Inc
Publish Only

Exploiting Parallelism in Serial DFT Simulations
Author(s): Ivor Ting, Saghir Shaikh, - Broadcom Corporation, Amir Nilipour, Ajay Thiriveedhi, - Synopsys
Publish Only

Optimum Design Planning with DC-Graphical and ICC-DP
Author(s): Gan Chong Gim - Altera
Publish Only

Partition-based Scan Compression Approach for Large Pin Limited Designs
Author(s): Bhagavathi Mula, - Juniper, Richard Lee, - Synopsys, Jim Hulings, - Avago
Publish Only

Tutorials
MA01 - IC Compiler 2013
IC Compiler 2013.03 Release Highlights
Author(s): Synopsys
Tutorial

MA03 - IC Compiler Custom Co-Design
IC Compiler Custom Co-Design
Author(s): Synopsys
Tutorial

MA07 FPGA-Based Prototyping
My BFF FPGA-Based Prototyping Solution: Better, Faster, and Flexible
Author(s): Synopsys
Tutorial

MB03 Design Compiler Update
Galaxy RTL: Design Compiler Family 2013.03 Update
Author(s): Synopsys
Tutorial

MB04 Debugging with Verdi
Verdi Transaction Based Debugging for SoC Designs
Author(s): Synopsys
Tutorial

MB05 Measuring and Improving Verification Quality
Functional Signoff: A Process for Measuring and Improving Verification Quality to Ensure Bug-Free Designs
Author(s): Synopsys
Tutorial

MB06 Optimizing Extraction Performance and Accuracy
Fast Extraction and Accuracy for Advanced 20nm and 14nm Designs
Author(s): Synopsys
Tutorial

StarRC Transistor-level Extraction: Optimizing Accuracy and Performance for Custom AMS Flows
Author(s): Synopsys
Tutorial

MB07 Bringup and Debug of FPGA based Prototypes
Pest Control, Hunt Down Bugs Like the Experts
Author(s): Synopsys
Tutorial

MC05 UVM Best Practices
UVM Best Practices
Author(s): Synopsys
Tutorial

MC07 Hybrid Prototyping
Hybrid Prototyping 101
Author(s): Synopsys
Tutorial

MC08 Circuit Simulation Release Update
Getting ready for the next technology node
Author(s): Synopsys
Tutorial

TA06 Maximizing Signoff Productivity
PrimeTime HyperScale - Hierarchical STA
Author(s): Synopsys
Tutorial

Simultaneous Multi-Voltage Analysis for Faster Timing Signoff
Author(s): Synopsys
Tutorial

TA07 Network Software Development using Virtual Prototypes
Ease Debug and Control of Network Software Using Virtual Prototypes to Do Full System Simulation
Author(s): Robert Kaye - ARM, Tom De Schutter - Synopsys
Tutorial

TA08 Verification using Verilog-AMS
Analog and Mixed-signal Verification Methodology Using Verilog-AMS
Author(s): Synopsys
Tutorial

TB01 - Implementation Flows for ARM Cortex-A7 and Cortex-A15 cores
Engineering Trade-Offs in the Implementation of a High Performance Dual Core ARM® Cortex™-A15 Processor
Author(s): ARM and Synopsys
Tutorial

Power-Centric Timing Optimization of an ARM® Quad Core Cortex™-A7 Processor
Author(s): ARM and Synopsys
Tutorial

TB02 Physical Verification of a Production FinFET SoC with IC Validator
Advancements in Density Management at 20nm and below with IC Validator
Author(s): Synopsys
Tutorial

TB03 Meeting Test Quality Goals
Meeting Quality Goals for Gigascale Designs: Trends and Solutions
Author(s): Synopsys
Tutorial

TB05 Integrating Virtual Platforms into Hardware Accelerated RTL
Introduction to Integration of Virtual Platform Technologies with Hardware Accelerated RTL
Author(s): Synopsys
Tutorial

TB06 Leakage Recovery with PrimeTime
Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction
Author(s): Synopsys
Tutorial

TB07 SoC Architecture Optimization
Low Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs
Author(s): Synopsys
Tutorial

TB08
TB8-A A Practical Look at Current Analysis in FastSpice
Author(s): Synopsys
Tutorial

TB08-B
TB8-B Transistor Level Static Circuit Analysis to Tackle ERC & ESD Challenges
Author(s): Synopsys
Tutorial

TC04 Transaction-level Verification with ZeBu-Server
Transaction-level Verification with ZeBu-Server - What, When, How
Author(s): Synopsys
Tutorial

TC05 Low Power Verification Debug
Can You Tell Your ISO from LS? – A Methodology for Low Power Debug
Author(s): Synopsys
Tutorial

TC06 Mode-Merging using PrimeTime
Using Mode-Merging to Reduce Scenarios Required for Timing Closure and Signoff
Author(s): Synopsys
Tutorial

TC07 Power Management Software Development using Virtual Prototypes
Using Virtual Prototypes for the Early Bring-Up and Test of Power Management Software
Author(s): Synopsys
Tutorial

WA01 Advanced CTS Features and Methodologies
Achieving Higher Frequencies for Your Design with Early Clockgating Optimization and Comprehensive Useful Skew
Author(s): Synopsys
Tutorial

WA02 Custom Design Using Laker
Laker 3 Custom Layout System - “An advanced process node custom layout tutorial”
Author(s): Synopsys
Tutorial

WA03 STAR Memory System
Embedded Memory Test, Repair & Diagnostics: DesignWare STAR Memory System Updates
Author(s): Synopsys
Tutorial

WA07 Designing with Xilinx 7 Series FPGAs
The Essentials for an Integrated Synplify-Vivado Design Flow Targeting Xilinx 7 Series FPGAs
Author(s): Synopsys
Tutorial

WB01 Multi-Bit Banking Solution
Introduction of Multi-Bit Banking Solution
Author(s): Synopsys
Tutorial

WB03 Multi-Die Memory Test for 2.5D Interposer
Multi-Die Memory Test in a 2.5D Silicon Interposer-Based Design
Author(s): Synopsys
Tutorial

WB04 VCS for Best Debug
VCS Technologies for Best Debug and Analysis
Author(s): Synopsys
Tutorial

WB06 Characterization Solutions
CCS Noise Characterization Solution
Author(s): Synopsys
Tutorial

WB07 Maximizing Productivity on Large FPGA Designs
Methodologies and Techniques for Maximizing Productivity on Large FPGA Designs
Author(s): Synopsys
Tutorial

WC01 Compiler ECO Flows
IC Compiler ECO Flows for Minimal Physical Impact
Author(s): Synopsys
Tutorial

WC03 Physical Failure and Yield Analysis
Successful Volume Diagnostics in a Fabless/Foundry Ecosystem
Author(s): Synopsys
Tutorial

WC06 Memory and Custom Digital Block Analysis and Charaterization
Analysis and Characterization of Memories and Custom Digital Blocks using NanoTime
Author(s): Synopsys
Tutorial

WC07 Synthesis Methods for FPGA-Based Prototyping
Synthesis Methods for FPGA-Based Prototyping
Author(s): Synopsys
Tutorial

Panel Presentation
TC01-B
TC1-B Panel – Achieving Optimum Results on High Performance Processor Cores
Author(s): Broadcom, MediaTek, Samsung and STMicroelectronics
Panel

Lunch and Learn Presentations
MA10 Lunch and Learn
Designing IP for FinFET Technology: The Opportunities and Challenges
Author(s): Jamil Kawa, R&D Director - Synopsys
Lunch and Learn

TA10 Lunch and Learn
Design Compiler Overcoming the Challenges of Shrinking Design Schedules vs. Increasing Complexity
Author(s):
Lunch and Learn

TA11 Lunch and Learn
TA11 - Lunch and Learn: Optimization exploration of ARM® Cortex™ Processor-based Designs with the Lynx Design System
Author(s):
Lunch and Learn