SNUG France 2014 Proceedings

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Complete Proceedings


User Papers and Presentations
A1 - Early RTL Exploration and Synthesis
Exploration on CPU/GPU Designs with DC Explorer (Technical Committee Award Honorable Mention)
Author(s): Choukri Saidi, Sébastien Peurichard - STMicroelectronics
PaperPresentation

A2 - Testbench Qualification
Certitude Advanced Tips
Author(s): Jean-François Vizier - Dialog Semiconductor
PaperPresentation

Qualification of Complex Systems Multi-Purpose Processor Array
Author(s): Jehan-Philippe Barbiero - Kalray
PaperPresentation

Verification Quality Improvement Using Synopsys Certitude C/C++
Author(s): Mikaël Genay - STMicroelectronics, Ali Abbara, Florian Letombe, Julien Torrès - Synopsys
PaperPresentation

A3 - Physical Design Implementation
Engineering Change Order (3rd Place - Best Paper)
Author(s): Didier Gueze, Jyoti Kumar, Sandesh Jain, Swati Narang - STMicroelectronics
PaperPresentation

Optimizing Standard Cell Pin Accessibility in 14nmFDSOI with Synopsys Pin Access Checker
Author(s): Olivier Aupoix, Somya Agarwal, Nour Ben Salem - STMicroelectronics, Alain Boyer - Synopsys
PaperPresentation

A4 - Design for Test and ATPG
Configurable On Chip Clocking Controller Clock Bit Chain Length to Minimize Test Compression OCC Dedicated Scan Access at SOC Level
Author(s): Christophe Eychenne - STMicroelectronics
PaperPresentation

Generating Pattern to Debug Chain Segments in DFTMAX X-tolerant Mode
Author(s): Matthieu Sautier – STMicroelectronics, Salvatore Talluto - Synopsys
PaperPresentation

A6 - Mixed-Signal Verification I
Simulating Voltage Scaling For Real Applications
Author(s): Franck Gardic, Robin Wilson, Anne Lombardot - STMicroelectronics, Philippe Brahic - Synopsys
PaperPresentation

B1 - Advanced Synthesis and Formal Verification Techniques
Implementation of a Wireless DSP in 40nm Using DC Graphical
Author(s): Peter Debacker, Veerle Derudder, Ilse Vos, Andy Dewilde, Antoine Dejonghe - IMEC
PaperPresentation

Using Synopsys Physical Guidance Flow with Design Compiler Graphical and IC Compiler for Achieving Maximum Performance and Minimum Leakage Goals for LEON3 Core-based Designs
Author(s): Alexander Korolkov, Igor Orlovsky, Andrey Veitsel - Topcon Positioning Systems, Russia, Jan Andersson - Aeroflex Gaisler, Feodor Merkelov, Dmitry Radchenko - Synopsys
PaperPresentation

B2 - Adopting UVM Methodology and Next Generation VIPs
Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption
Author(s): John Aynsley, Dr. Christoph Sühnel and Dr. David Long - Doulos
PaperPresentation

Using Synopsys CSI2 VIP for IP-Level Verification
Author(s): Jose Mangione, Noreddine Ben El Kardadi, Zineb Sakout Andaloussi - STMicroelectronics, Xavier Mathes - Synopsys
PaperPresentation

B3 - In-design Physical Closure and Signoff Accuracy
Improving STA Productivity at 32nm/28nmFDSOI and Below (1st Place - Best Paper)
Author(s): Sébastien Marchal - STMicroelectronics
PaperPresentation

In-Design Automatic DRC Repair Flow Using IC Compiler and IC Validator
Author(s): Stephane Pautou - STMicroelectronics, Alain Boyer - Synopsys
PaperPresentation

B4 - Improving Test Quality and Yield
Better Faster Stronger Diagnostic Approach with Synopsys’ Yield Explorer
Author(s): Jean-Marc Denollet, Thomas Droniou - STMicroelectronics, Christophe Suzor - Synopsys
PaperPresentation

Physical Data Loading to Improve Diagnosis Accuracy (2nd Place - Best Paper)
Author(s): Nelly Feldman, Vincent Robert – STMicroelectronics, Christophe Suzor, Salvatore Talluto - Synopsys
PaperPresentation

R&D Q&A Session - Volume Diagnostics for Accelerated Yield Learning in Advanced Technology Nodes
Author(s): Christophe Suzor - Synopsys
Tutorial

B6 - Custom Design Methodology and Signal Integrity
Adding a Metal Fringe Capacitance to an iPDK
Author(s): Alain Vigne - Blinksight
PaperPresentation

New Advanced Methodology for Parasitic Extraction Aimed at Post Layout Analysis in BCD Technologies
Author(s): Davide Cavalli, Luciana Paciaroni - STMicroelectronics, Claudio Rallo - Synopsys
PaperPresentation

B7 - Galaxy Custom Router
Hands-on Galaxy Custom Router Workshop with Competition and Prize Draw
Author(s): Fouad Bissane - Synopsys
Tutorial

C1 - Low-Power Static Checking
New Generation of Low-power Static Checker
Author(s): Irène Serre, Pascal Blanc - STMicroelectronics
PaperPresentation

C2 - Hardware-based Verification
Accelerating the Validation of a Secure ROM with ZeBu
Author(s): Gherardo Gorni, Simone Borri – Abilis Systems
PaperPresentation

C3 - IC Compiler II
IC Compiler II: A Fast Methodology to a Good Hierarchical Floorplan
Author(s): Pascal Teissier – STMicroelectronics, Gaspard Thaller - Synopsys
PaperPresentation

New Breakthrough in Physical Design Productivity
Author(s): Claire Mauduit, Johann Meleard - STMicroelectronics, Hervé Raffard - Synopsys
PaperPresentation

C4 - SMS & SHS Technologies for IEEE 1500 SoC
STAR Hierarchical System (SHS) Architecture Implementation in Full IEEE1500 SoC (1st Place - Best Paper, Technical Committee Award)
Author(s): Cédric Escallier - STMicroelectronics
PaperPresentation

C6 - Mixed-Signal Verification II
Analog-on-top AMS Verification - a Practical Approach
Author(s): Jonathan Bradford, Gernot Koch - Micronas
PaperPresentation

Keynote
Designing Change Through Innovation and Collaboration
Author(s): John Chilton, Senior Vice President and General Manager, Coverity, Synopsys Inc.

Tutorials
A1 - Early RTL Exploration and Synthesis
Design Compiler 2013.12 Release Highlights
Author(s): Eric Bouet - Synopsys
Tutorial

A3 - Physical Design Implementation
ICC 2013.12 Release Highlight
Author(s): Ludovic Pinon - Synopsys
Tutorial

A4 - Design for Test and ATPG
DFTMAX Ultra for Squeezing Out More Test Compression with Fewer Pins
Author(s): Jean-Pierre Popieul - Synopsys
Tutorial

A5 - Accelerate FPGA-based Prototypes
Automating SoC RTL to Operational Prototype
Author(s): Laurent Sol - Synopsys
Tutorial

Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goal
Author(s): Paul Owens - Synopsys
Tutorial

A6 - Mixed-Signal Verification I
Advanced CustomSim-VCS Multi Core Usage
Author(s): Philippe Brahic - Synopsys
Tutorial

Enrich your Mixed-Signal Verification with UPF Simulation
Author(s): Pierre-Yves Alla - Synopsys
Tutorial

B1 - Advanced Synthesis and Formal Verification Techniques
ECO Implementation Assistance Using Formality Ultra
Author(s): Eric Zann - Synopsys
Tutorial

B2 - Adopting UVM Methodology and Next Generation VIPs
Debugging System Verilog Testbench with Verdi3
Author(s): Jérôme Peillat - Synopsys
Tutorial

B3 - In-design Physical Closure and Signoff Accuracy
PrimeTime ECO - Now Physically Aware
Author(s): Emmanuel Pluchart - Synopsys
Tutorial

B5 - Complex IP and SoC Prototyping
Emulation and Prototyping of Imagination GPUs using ZeBu and HAPS
Author(s): Colin McKellar - Imagination Technologies, Andy Jolley - Synopsys Inc.
Presentation

Putting IP Prototyping on the Fast Track using HAPS Developer eXpress
Author(s): Angela Sutton - Synopsys
Tutorial

B6 - Custom Design Methodology and Signal Integrity
Signal Integrity Analysis of High-Speed Serial Links Using HSPICE
Author(s): David Cartalade, Synopsys
Tutorial

C1 - Low-Power Static Checking
Verdi Signoff-LP: Next-Generation Low-Power Static Verification
Author(s): Stephanie Varela - Synopsys
Tutorial

C2 - Hardware-based Verification
Verification of SoC Designs with ZeBu HW Emulator
Author(s): Fabien Delguste - Synopsys
Tutorial

C3 - IC Compiler II
IC Compiler II and the Power of 10x: A Product Walk-through
Author(s): Michel Douillard - Synopsys

C4 - SMS & SHS Technologies for IEEE 1500 SoC
Accelerate SoC Testing Using Synopsys' DesignWare STAR Hierarchical System and DesignWare STAR Memory System
Author(s): Arnaud Wenzel - STMicroelectronics
Presentation

C5 - Coverity
Introduction to Coverity
Author(s): Scott Tolley - Coverity
Tutorial

C6 - Mixed-Signal Verification II
When Bandgaps Regress: Solving the Challenges of AMS Verification
Author(s): Paul Chapman - Synopsys
Tutorial

Workshop
A7 - Galaxy Custom Router
Hands-on Galaxy Custom Router Workshop with Competition and Prize Draw
Author(s): Guillaume Thomas - Synopsys
Tutorial