SNUG Austin 2013 Proceedings

20142013201220112010
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Complete Proceedings


User Papers and Presentations
FA1 User & Tutorial Session: Advanced PT and 2013.03 Galaxy Update
Methods for Timing Source Synchronous Interfaces and Skew Sensitive Buses
Author(s): Anil Jain - Broadcom
PaperPresentation

Using PrimeTime's New Signoff-Driven Leakage Recovery Feature (2nd Place - Best Paper)
Author(s): Hyon Han, Shen Ge, Dean Marvin, Ashish Nayak , Francis Skowronski - Samsung
PaperPresentation

FA2 User & Tutorial Session: ECO Solutions and Tool Correlation for Design Closure
Calibrating IC Compiler, StarRC, and PrimeTime for Parasitic and Timing Correlation
Author(s): Harish Dangat - Samsung
PaperPresentation

How We Saved Over a Half Million Dollars in Mask Costs Using the Power of IC Compiler’s Z-route
Author(s): Kyle Peavy, Robert Sussman - Texas Instruments, Inc., David Stringfellow - Synopsys
PaperPresentation

FA3 User & Tutorial Session: X-Propagation, Static LP Checking and Random Stability
A Practical Approach to Implementing Synopsys X-Prop Technology on a Complex SoC
Author(s): Sounder Kumar, Amol Bhinge - Freescale Semiconductor, Tareq Altakrouri - Synopsys
PaperPresentation

Random Stability in SystemVerilog
Author(s): Doug Smith - Doulos
PaperPresentation

FA4 User Session: FinFET’s Impact on the AMS Flow; NanoTime
Accurate Transistor-level STA Methodology for 20nm Custom SRAM Macro Using NanoTime (3rd Place - Best Paper)
Author(s): Shahnaz Nagle, Mandeep Singh - Samsung, Charles Jiang - Synopsys
PaperPresentation

Planar MOSFET to FinFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3
Author(s): Tom Mahatdejkul - ARM®
PaperPresentation

Static Timing Analysis Pessimism Reduction through Clock Shaping
Author(s): Yaping Zhan, Timothy Correia, Stephen Lim, David Newmark, Meghna Singhal - AMD, Norb Heindl, Maureen Ladd - Synopsys
PaperPresentation

FB1 User & Tutorial Session: DC-Graphical and UPF
High-Speed and Complex IP Design Exploration Utilizing Recent QoR Improvement Features in Design Compiler Graphical and IC Compiler
Author(s): Hao Luan - Huawei Technologies USA; Mike Adams, Stewart Shankel, III - Synopsys
PaperPresentation

FB2 User & Tutorial Session: FinFET, Emerging Node and High-Speed Clock Mesh Solutions
IC Compiler-based Holistic Clock Methodology
Author(s): Anand Iyer, Tim Kasper, Abhishek Kumar - Advanced Micro Devices; Denise Powell - Synopsys
PaperPresentation

FB3 User & Tutorial Session: Verification Quality, Low Power, and Verification IP
Challenges and Implications of Verifying Low-Power Features in a Complex SoC
Author(s): Aditya Musunuri, Amol Bhinge - Freescale
PaperPresentation

FB4 User Session: ATPG and Defect Diagnosis
In Situ Defect Diagnosis using IEEE 1149.1 and P1687
Author(s): John Potter, Alfred Crouch - ASSET InterTech, Inc., Adam Cron - Synopsys, Inc.
PaperPresentation

Placement-Based Analysis of Scan Test ATPG Switching Activity
Author(s): Kelvin Ge - Samsung, Glenn Boyer - Synopsys
PaperPresentation

FC1 User & Tutorial Session: Structured Placement, Constraints, and Formality
A Fine-Grained Hybrid Approach to Structured Placement and Synthesis
Author(s): Cory Krug - Oracle Labs
PaperPresentation

Diagnosis of Vulnerable Constraints Using PrimeTime GCA for Hierarchical Design
Author(s): Hyun-Chul Do - Samsung Electronics Co., Ltd.
PaperPresentation

FC2 User & Tutorial Session: Advanced CTS Methodology, Crossbar Implementation and 14nm Challenges
Intro to FinFET: Challenges for 14nm and Beyond
Author(s): Mothi Ande
PaperPresentation

Optimizing 1024x1024 Cross Bar Design Employing Relative Placement, Pre-routes and Buffer Pre-placement Flow
Author(s): Tung Pham, Paul Bassett - Qualcomm Technologies Inc., Frank Gover - Synopsys
PaperPresentation

FC3 User & Tutorial Session: UVM and Advanced SoC debug
Considerations for Development and Support of Exportable UVM IP
Author(s): Thomas Loftus - Advanced Micro Devices
PaperPresentation

FC4 User & Tutorial Session: Recommended DFT Methodologies
ATPG for Multi-Fault Model, Multi-Testmode, Multi-Frequency, Pin Limited Deep Submicron Devices using On Chip Clock Control
Author(s): Tejan Thakore - Maxim Integrated
PaperPresentation

DFT Architecture and Implementation of a Quad-core ARM® Cortex™ Processor Targeted for Low-Power, High Performance Applications (1st Place - Best Paper)
Author(s): Kelvin Ge, Shaishav Parikh - Samsung, Glenn Boyer - Synopsys
PaperPresentation

Publication Only
Applications of Custom UVM Report Servers
Author(s): Gordon McGregor - Verilab, Inc.
Paper

Scan Stitching of Different Flop Groups with DFT Compiler
Author(s): Umesh Chandra Chejara, Abhishek Kumar, Brian Walters, Michael Quimby - Advanced Micro Devices
Paper

Tutorials
FA1 User & Tutorial Session: Advanced PT and 2013.03 Galaxy Update
Galaxy RTL: Design Compiler Family 2013.03 Update
Author(s): Synopsys
Tutorial

FA2 User & Tutorial Session: ECO Solutions and Tool Correlation for Design Closure
IC Compiler ECO Flows for Minimal Physical Impact
Author(s): Bill Sicaras - Synopsys
Tutorial

FA3 User & Tutorial Session: X-Propagation, Static LP Checking and Random Stability
Next-Generation Low-Power Static Checking with Verdi Signoff-LP
Author(s): David Lee - Synopsys
Tutorial

FB1 User & Tutorial Session: DC-Graphical and UPF
Visualization and Debug of UPF with Design Vision GUI
Author(s): Josefina Hobbs - Synopsys
Tutorial

FB2 User & Tutorial Session: FinFET, Emerging Node and High-Speed Clock Mesh Solutions
Emerging Node Challenges and Opportunities
Author(s): JC Lin - Synopsys

FB3 User & Tutorial Session: Verification Quality, Low Power, and Verification IP
Functional Signoff: A Process for Measuring and Improving Verification Quality to Ensure Bug-Free Designs
Author(s): Robert Booth, Freescale; Jay Dutt, Synopsys
Tutorial

FC1 User & Tutorial Session: Structured Placement, Constraints, and Formality
Speeding ECO Implementation and Verification with Formality Ultra
Author(s): Steve Lamb - Synopsys
Tutorial

FC2 User & Tutorial Session: Advanced CTS Methodology, Crossbar Implementation and 14nm Challenges
IC Compiler Advanced CTS Features and Methodologies
Author(s): Imad Zaccak - Synopsys
Tutorial

FC3 User & Tutorial Session: UVM and Advanced SoC debug
Debug for Advanced SoC Verification and Verdi Road Map
Author(s): Brian Schneider - Synopsys
Tutorial

Practical Applications with UVM Sequences – Body Building 201
Author(s): Kevin Geiger, Synopsys
Tutorial Code Example

FC4 User & Tutorial Session: Recommended DFT Methodologies
Meeting Quality Goals for Gigascale Designs: Trends and Solutions
Author(s): Adam Cron - Synopsys
Tutorial