|Wednesday, May 01, 2013|
1:30 PM - 3:00 PM
|B1 - FPGA Implementation and FPGA-based Prototyping II|
|FPGA Prototyping Visibility with Protolink|
Peter Gibbons - ARM
With the increased complexity of systems and their components the need for FPGA prototyping to improve the validation processes has become a fundamental requirement within ARM. Having a large number of FPGA boards able to run validation cycles quickly is only the beginning of the challenge. Once we have found a failure the time taken to understand the root cause can be long and labour intensive. Using ProtoLink and Full Visibility reduces the time and effort required to determine if it is a real bug or some feature of the validation environment and close out these failures quickly. ARM was an integral part of the ProtoLink and Full Visibility development driving requirements and testing of the product throughout its development.
FPGA Based Prototypers with need for effective Debug Visibility
|Thursday, May 16, 2013|
10:45 AM - 12:15 PM
|A1 - FPGA Implementation and FPGA-based Prototyping I|
|Effective Implementation of Xilinx 7 Series FPGAs – Methodologies and Techniques for Maximizing Productivity|
Andy Jolley, Frank McMillan - Synopsys Ltd.
The recent Introduction of the Xilinx 7 series of FPGAs (Virtex-7, Kintex-7, Artix-7 and Zynq) has necessitated the adoption of new Implementation flows and tools along with the latest Synthesis Techniques to provide effective and timely first time Implementations along with manageable iterations. This tutorial is aimed at users of these latest FPGA technologies and provides practical guidance for maximising productivity through efficient RTL, IP and constraint set-up along with early analysis through enhanced synthesis reports and TCL scripting. The use of latest synthesis tool features to assist with design analysis, debug and run-time reduction is also discussed. The tutorial also covers practical advice for those using the latest FPGA for Prototyping an ASIC or SoC along with recommendations for getting the design into the prototype quickly whilst maximising the capabilities of the latest FPGAs .
FPGA Designers looking for practical knowledge to gain maximum efficiency and quality of results targeting 7 Series designs
|A2 - Low Power Implementation I|
|A Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor|
Dale Lomelino - Synopsys Inc., Stuart Riches - ARM
Learn how to optimize the Quad-Core ARM® Cortex™-A7 MPCore™ processor for the best power efficiency targeted for entry mobile and other power-sensitive products. This tutorial will highlight the latest technologies in Design Compiler Graphical and IC Compiler that can be used to achieve challenging power/performance targets. Shared best practices leverage Synopsys' high-performance core (HPC) methodology, including optimizations for power as a primary requirement to be managed at each step in the flow; from synthesis, placement, clock and routing, to post-route timing closure. Low power capabilities introduced here are augmented with aggressive power management of library VT classes and timing targets. The power-centric high-performance core methodology will be illustrated through a reference implementation of a quad core Cortex-A7 processor with ARM POP(TM) technology for core-hardening acceleration on TSMC 28HPM process. The final product is a strong starting point for designing the 'LITTLE' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for cost-sensitive markets.
This tutorial is for Managers and Designers with responsibility for creating power efficient SoCs for power-sensitive products
|A3 - High-Performance Implementation I|
|Achieving Higher Frequencies for Your Design with Early Clock-gating Optimization and Comprehensive Useful Skew|
Jonathan Dawes - Synopsys Ltd.
This tutorial introduces new ICC features targeting higher frequencies and improved ease of use. We’ll describe enhancements to the placement and optimization of the clock-gating elements prior to CTS, which deliver improved timing and convergence of the flow. The new features use improved clock-gate restructuring and CTS latency estimation for more accurate clock-gate placement and clock-enable path timing optimization. The session will also cover new skew features in IC Compiler which use techniques including multi-stage slack borrowing and on-the-fly clock tree adjustment. These features will enable you to meet frequency goals using a simple flow, without resorting to complex multi-pass approaches.
IC Compiler Users targeting high frequency solutions
|Introduction of Multi-Bit Banking Solution|
Lee Keep - Synopsys Ltd.
Optimization for power is one of the most important objectives in nanometer IC design. Reducing power consumption in chips enables better, cheaper products to be designed and power-related chip failures to be minimized. Clock trees are one of the biggest contributors to power consumption. By keeping the actual length of the clock tree short, we can immediately reduce the overall power consumption. This session will describe how IC Compiler was used to reduce the clock tree length by grouping registers together in banks of registers (the so-called multi-bit banks). By ensuring that several registers are inside one macro, the length of the clock net is reduced, resulting in power savings.
IC Compiler and DC Compiler Users who are considering usage of multi-bit registers
|A4 - Verification I|
|VCS Technologies for Best Debug and Analysis|
Yassine Eben Amine - Synopsys Ltd.
This tutorial will focus on several technologies recently added to VCS that dramatically improve debug productivity. Checkpoint and interactive rewind enable the user to quickly step back in simulation time without having to restart and rerun the simulation. Dumping and browsing of dynamic / testbench objects is now possible using the DVE Object browser which allows complex object relationships to be displayed. Recent improvements to the DVE Constraint GUI allow graphical constraint debug, what-if analysis and distribution-debug to be performed. Finally UVM and VMM specific debug topics will be covered.
Verification Engineers and RTL Designers who want to debug SystemVerilog testbenches more effectively using the latest tools, tips and techniques.
|Certitude - Achieving Faster Verification Closure Using Design Mutation Analysis|
Yogish Sekhar - Dialog Semiconductors
Shrinking transistor sizes means more complex design is squeezed into the same area that used a product generation earlier. The world is aware of Moore's law for design; but it's more applicable to the verification space today as verification complexity has increased exponentially. There are multitudes of tools (i.e. simulators, methodologies) that tell us how we need to verify our designs and various different metrics that tell us what we have verified.
In a world where “only the paranoid survive," can we really say that every possible scenario has been covered and verified? NO. We only can understand the risks we are taking and solutions to mitigate those risks. Any framework that helps in identifying these risks early on in the verification cycle, will have a huge impact on the design/product either becoming a revenue generator or being assigned to the dump!
|A5 - Analog Mixed-Signal/Full Custom Design I|
|A Comparison of Dynamic and Static Approaches for the Creation of Liberty Models for Mixed-Signal Macros|
Oliver King - Moortec Semiconductor, Damian Roberts, Andy Milne - Synopsys Ltd.
As geometries shrink, available timing margins are diminished and mask sets become more expensive, an accurate representation of mixed signal macros in a Liberty model is a requirement for successful integration into a digital design flow.
This presents numerous challenges; Mixed-signal IP blocks can be complex, with multiple IOs which may be difficult to model within the Liberty framework. In addition, transistor-level analysis of large analog blocks can be time consuming and may require many different scenarios to be explored.
This presentation will describe the exploration of the various methods of generation of Liberty models of mixed-signal macros, using both dynamic and static transistor analysis techniques. A methodology that has been adopted by Moortec for automatic and timely model generation is presented. The usage of this methodology has enabled Moortec to enhance the ease of deployment of their IP into numerous customer designs.
Custom Digital and Mixed-signal Macro Designers, IP providers
|CCS Noise Characterization Solution|
Damian Roberts (Synopsys Ltd.)
As technology nodes shrink, the effects of noise are getting more pronounced and an accurate representation in the Liberty model is crucial for static noise analysis. Designers can characterize and add accurate noise models to their Liberty libraries using SiliconSmart’s built-in noise characterization solution with fast turn-around time. SiliconSmart is a comprehensive characterization solution for standard cells, I/O and memory. It generates accurate model libraries tightly correlated with Synopsys' digital implementation tools. This presentation will focus of how to use SiliconSmart to quickly generate CCS noise models for standard cells, IO's and memories.
Library Characterization Teams, IP providers
|A6 - Signoff-Driven Optimisation I|
|PrimeTime 2012.12 Productivity Features: Mode Merging and Leakage Recovery|
Simon Bloyce - Synopsys Ltd.
PrimeTime's 2012.12 release sees the introduction of two new and powerful productivity features, Mode Merging and leakage recovery ECO. This tutorial will introduce each of these valuable additions. You will learn how Mode Merging can reduce the number of scenarios required for timing analysis to improve turnaround time and resource requirements, and we will discuss the latest enhancements to the suite of ECO capabilities now available in the PrimeTime Suite and how to deploy these capabilities together effectively.
This tutorial is for Managers and Designers with responsibility for multi-scenario SoC and ASIC design closure and signoff.
|Leakage Power Recovery across Multiple Timing Scenarios|
Russell Vickers - Intel
This paper discusses a methodology for leakage recovery across multiple timing scenarios. Concurrent fixing across all modes and corners has become increasingly demanding as process technology advances towards 12/14nm, and with these more complex technologies leakage power can be very significant and also needs to be addressed in the context of all the signoff scenarios. We will assess how leakage recovery capabilities can be used to reduce the leakage power of a design, see how it fits into a signoff flow, and examine the impact leakage recovery has on silicon performance.
|Thursday, May 16, 2013|
1:30 PM - 3:00 PM
|B1 - FPGA Implementation and FPGA-based Prototyping II|
|Introduction to Transaction-Based Verification and Hybrid Prototyping|
Frank McMillan - Synopsys Ltd.
This tutorial provides practical advice and techniques for the integration of virtual and FPGA-based prototypes. You will learn how high-performance data exchange is made possible through new AMBA transactors and Synopsys’ low-latency UMRBus physical link. Hybrid prototyping (which integrates virtual prototypes and HAPS® FPGA-based prototypes into a single environment) is demonstrated using an ARM Cortex-based SoC with integrated SoC block. It is shown how this can allow designers to accelerate system bring-up, improve debug visibility and start software development much earlier in the design cycle. Attendees will leave with a good understanding of how hybrid prototypes can benefit development schedules and how they can be deployed.
Engineers and Engineering Managers responsible for ASIC/SoC verification, emulation, and prototyping who are seeking ways to make high-performance prototypes available sooner in the development process and learn about the latest technology to link the TLM to RTL model domains
|B2 - Low Power Implementation II|
|Power Intent Specification: Successful Integration of Hard Macros|
Conor Byrne - Intel
UPF is a comprehensive but complex language which captures power intent in a structured and standardised format. But for a new user it can be difficult to know precisely how to apply it to a real-world design. In this paper we explore some of its fundamental concepts. In particular, through a number of scenarios, we consider how to integrate complex hard macros into a multi-voltage design. We elucidate a number of general principles which can help to ease the subsequent multi-voltage implementation.
|IEEE1801 (UPF2.0): Automated and Flexible Approach to Power Management Insertion|
Conor Byrne - Intel
Advanced Low Power designs can be challenging, even more so with aggressive timescales. In this paper the author will discuss the use of IEEE Std 1801-2009 (UPF2.0) to reduce significant project risk and expedite a smoother path to tape out with a comprehensive UPF-driven low power flow solution.
The paper will describe the tool flow starting from Intel's legacy libraries through to Physical Implementation, including a novel way to produce your UPF with a rapidly-evolving power architecture. The paper will touch on the subtleties of UPF when implementing your design hierarchically, capturing issues encountered along the way and techniques used to resolve them.
|B3 - High-Performance Implementation II|
|Deploying a Reference Flow for High-Performance GPU Implementation|
John Herbert - Imagination Technologies Ltd., Ian Craigen - Synopsys Ltd.
Achieving a balance between high performance, area and low power in the soft GPU market is challenging. In this session you will discover how using Synopsys' High Performance Core reference flow as a baseline we were able to develop our reference flow using Synopsys library IP for the benefit of our mutual customers. The results will show that IP selection and adopting a good flow is important when delivering a low power and low area implementation.
Design Implementation Engineers working on high performance cores
|Achieving Performance Improvements with Design Compiler Block Abstracts|
Ben Kerr - Broadcom, Martin Phipps - Synopsys Ltd.
Synopsys' Design Compiler product recently introduced a block abstraction flow as a replacement for Interface Logic Models. This paper presents a study of the run-time improvements obtained when using block abstracts in a very large RTL design along with some of the practical considerations needed when adopting a Block Abstract based flow.
|B4 - Verification II|
|Making the Most of SystemVerilog and UVM: Hints and Tips for New Users|
David Long - Doulos
In the two years since UVM 1.0 was released, Doulos has seen a big increase in customers wanting to learn SystemVerilog: UVM has become the standard verification environment for many companies. However, engineers often find that the size and complexity of the SystemVerilog language and the UVM class library make it hard to learn and make effective use of many features. This paper is intended to give guidance about useful features of both SystemVerilog and UVM that are often overlooked, used incorrectly or simply avoided because they are perceived as being "too hard." The first part identifies the most common novice-user mistakes and sets out rules to avoid them. The second part discusses useful enhancements to verification capabilities that can be obtained from deeper understanding of a few SystemVerilog and UVM features. It provides simple examples and guidelines to show how each enhancement can be achieved.
|Going from Custom Methodology to UVM? Do it with a Hybrid.|
Eric Ohana - ARM Ltd.
Migrating from a proprietary verification methodology to the standard Universal Verification Methodology (UVM) can carry risks. To mitigate such risks, we propose here a hybrid approach where proven legacy test bench components can co-exist along with newly developed UVM com-ponents. In this context, this paper describes a co-simulation framework that enables such a pro-gressive migration to UVM. The paper addresses phase synchronization between the two envi-ronments, how information can be exchanged, and finally the reporting and messaging mechanisms.
|B5 - Analog Mixed-signal/Full Custom Design II|
|Advanced Process Node Custom Layout|
Paul Chapman - Synopsys Ltd.
Process technology at 20nm and below brings new layout challenges. There are many more DRC checks and layout proximity effects which could take you into endless iterations. In this tutorial we will look at which issues are new, which can be addressed by good design practice, and which need enhancements to EDA tools to provide good performance / area trade-offs while maintaining good productivity. Technologies that will be covered in this tutorial include rule-based layout, schematic-driven layout, and pattern-based multi-device layout features.
Analog, Custom Digital and Mixed-signal Design Engineers, CAD Managers and Engineering Managers
|Full Custom Layout Automation with Helix|
Mark Keane - Cambridge Silicon Radio Ltd., Ross Addinall - Synopsys Ltd.
Helix is an advanced device-level automated placement solution for analog, and mixed-signal IC designs such as PLLs, SerDes, ADCs and PHYs. In this tutorial we will see how Helix "First Look" allows a rapid, yet accurate area estimation. The layout engineer can then refine the constraints allowing a DRC clean, tape out quality placement to be generated minutes after a design change. True concurrent productivity between the circuit and layout designer results in a reduced and more predictable design time, and better quality layout.
Analog, Custom Digital and Mixed-signal Design Engineers, CAD Managers and Engineering Managers
|B6 - Design for Test I|
|DFT and ATPG for Mixed 2-phase Latch and Edge Triggered Flop-based Designs|
Richard Illman - Dialog Semiconductor
The use of both 2-phase clocked latches and edge triggered flops in a scan-based test poses a number of problems for scan insertion and test pattern generation; particularly when combined with scan compression. However, the use of these types of sequential elements is becoming increasingly important in low-power applications. RS type latches are also needed to capture asynchronous events, but can cause DFT problems. This paper describes DFT styles and ATPG flows using TetraMAX and DFTMAX within the Synopsys environment for this design style. The topics covered include design and clocking rules, library models, DFT rule checking, ATPG and verification/debug. The paper also covers techniques to improve IDDQ/burn-in coverage for these design styles.
|A Hybrid ATPG and Application Testing flow to Localize a Complex RF SoC Failure|
Kai Wang, Rhys Weaver - CSR Plc., David Johnson - Synopsys Ltd.
The failure diagnostic process in deep submicron system on a chip (SOC) devices is becoming increasingly difficult, as more functions are integrated into the design. This integration limits I/O accessibility and often results in failures which have their cause hidden in embedded functional blocks. Therefore failure analysis for SOC devices must consider not only a localized fault but also the impact of the fault in related hardware blocks, firmware and even application software.
This paper explores the range of testing, including application testing, required to confirm and localize a Bluetooth RF communication failure. The root cause was traced to a digital fault by using a Synopsys Tetramax ® scan diagnostic tool and then correlating the RTL and layout information to a physical location. The failure mechanism and the benefits of using transitional scan patterns are also discussed.
|Thursday, May 16, 2013|
3:30 PM - 5:00 PM
|C1 - FPGA Implementation and FPGA-based Prototyping III|
|Complex SOC Prototyping using Xilinx Virtex 7 based HAPS-70 Systems|
Paul Robertson - Broadcom, Andy Jolley - Synopsys Ltd.
The challenge of Implementing latest complex Mobile Multi-Media SOCs onto FPGA based platforms for prototyping and S/W development activities has been assisted via the Introduction of the latest multi-die Xilinx Virtex 7 FPGAs which have extended the individual device capacities to around the 12M ASIC gate mark which improving I/O and Core performance. This paper from Paul Robertson of Broadcom outlines the process of preparing such a complex SOC for Implementation on the latest Virtex 7 based HAPS-70 Prototyping Systems from Synopsys, handling new challenges related to making best use of the multiple-die FPGAs and then bringing-up the Prototyping Systems to be functional whilst ensuring Optimal System Performance
|Bring Up and Debug of FPGA Prototypes|
Mick Posner - Synopsys Ltd.
This tutorial highlights how to effectively employ best practices and design automation tools to accelerate the bring-up and debug of IP and SoC subsystems with an FPGA-based prototype. Expert prototyping engineers will show examples using the latest generation of Synopsys FPGA-based prototypes through all phases of an implementation: initial power-up; subsystem bring-up; and full system initialization. The application of prototype troubleshooting and design debug techniques at each stage will be presented as a case study. This includes assessment of the specific debug need, best fit of particular debug techniques, and the end result of each session. Attendees will leave with a clear understanding of how and when to apply techniques to complex FPGA-based prototypes.
Target Audience: Engineers and Engineering Managers responsible for ASIC/SoC verification, emulation, and prototyping who are seeking the latest methods and tools to accelerate FPGA-based prototype bring-up and RTL debug.
|C2 - Low Power Implementation III|
|Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High-Performance Mobile SoCs|
John Biggs, David Flynn, James Myers - ARM
Power gating is now a mainstream leakage mitigation technique in all modern application processor cores, but saving away program state and actually shutting down is an energy gamble left to the Operating System. A more energy optimal approach is to use hardware state retention registers but the associated area and performance penalties have prevented wide adoption to date. This paper describes an advanced state retention scheme which builds upon power gating with minimal additional area and performance impact, discusses application to an ARM processor implemented using Design Compiler and IC Compiler tools with a UPF-based flow and ARM 28nm physical IP.
|Using Formal Equivalence Verification Tool Efficiently on a UPF Design|
Venkatesh Jakke - Intel
Equivalency checking of a design with multiple power domains and power states can be challenging with tight project schedules. In this paper, the authors discuss how a UPF (Unified Power Format) design was debugged and made sign-off clean in Formal Equivalence Verification (FEV) tool, and the lessons learned in how to do this productively in terms of flow, tool runtime and engineering effort. They describe how real and false failures were found by FEV tool, and debugged during synthesis, test-insertion and place and route. The design contained a very large bus structure which added to the challenges. The approach used in FEV tool to this bus-structure is also discussed.
|C3 - High-Performance Implementation III|
|Engineering Trade-Offs in the Implementation of a High-Performance ARM® Cortex™-A15 Dual Core Processor|
Joe Walston - Synopsys Inc., Stuart Riches - ARM
Learn about the engineering trade-offs and flow development process to balance gigahertz+ performance and low power on a dual core ARM Cortex-A15 processor sub-system. This tutorial will show how to use engineering best practices and the Galaxy platform to meet challenging performance targets while maintaining leakage power in TSMC 28HPM design projects. Some key Galaxy features used include physical guidance for a predictable implementation flow, transparent interface optimization for top-level closure, and final stage leakage recovery for leakage power optimization. The techniques in this session can be used in your ARM Cortex-A15 implementations.
Design Implementation Engineers working on ARM CPUs, GPUs, and other high performance cores
|C4 - Low Power Verification|
|Architecting Power Awareness in a Constrained Random OVM Testbench|
Kevin Hyland - Intel
For IC designs in power sensitive applications, the ability to define multiple power domains, switched dynamically based on changing system requirements, is a powerful mechanism in reducing the overall power consumption of the circuit. This capability increases the IC's complexity to deal with scenarios that occur on power events. The challenge from a verification perspective is to verify this added complexity. This paper details the strategy deployed in addressing that challenge on a 3 million gate SoC design.
|Low Power Verification using Power State Table Coverage|
Christophe Lamard, Jean Marie Guillermin - ST Microelectronics, François Cerisier, Mathieu Maisonneuve - Test and Verification Solutions, France
This paper describes low power verification principles and the use of power state table to identify invalid power states and power transitions. The paper will show how to use the UPF power state tables to describe valid states and transitions for verification purposes. We will then explain issues related to reset states and transitional states and show how to use the power state table coverage to identify new sequences to implement.
|C5 - Analog Mixed-signal/Full Custom Design III|
|Analog and Mixed-signal Verification Methodology Using Verilog-AMS|
Peter Thompson - Synopsys Inc.
The majority of today's designs contain significant analog and mixed-signal content. Even SoCs that are designed for essentially digital functions still require PLLs for timing control, digitally-controlled power management circuits, and high-speed I/O devices. In this tutorial we discuss how the Synopsys analog / digital co-simulation methodology can be used for logic and timing verification of mixed-signal designs that contain digital place-and-route, custom digital and analog circuits. The tutorial will focus on the use of behavioral modeling techniques for improving simulation performance and enabling top-down design. This includes comparing Verilog-AMS with Real Number Modeling and creating different models for some mixed-signal blocks.
|Circuit Simulator Release Update - Getting Ready for the Next Technology Node |
Dan Zhu - Synopsys Inc.
This tutorial will discuss the latest innovations in Synopsys’ market-leading simulators and introduce new features available in the latest release of HSPICE, FineSim and CustomSim. The updates will cover technology advances in device modeling, simulator performance and capacity, and advanced circuit analysis features designed to help you meet the challenges of smaller geometry nodes and changing process models.
Analog, Custom Digital, Memory and Mixed-signal Design Engineers, CAD Managers and Engineering Managers
|C6 - Design for Test II|
|Meeting Quality Goals for Gigascale Designs: Trends and Solutions|
Dave Johnson - Synopsys Ltd.
This tutorial will highlight leading-edge capabilities in the Synopsys synthesis-based test solution for maximizing productivity, increasing test quality, and lowering test cost. First we will discuss how standards-based DFT has evolved within DFTMAX compression to save time and effort when implementing test for extremely complex designs. Next, we will examine several advanced detection mechanisms in TetraMAX ATPG for improving defect coverage. Finally, we will show new features in the tools that lower the cost of testing ARM processor-based designs and other multicore SoCs.
Designers and Managers interested in test, quality and manufacturing