SNUG UK Abstracts 

Thursday, May 24, 2012
10:45 AM - 12:15 PM
A1 - Tutorial: FPGA Implementation and FPGA-based Prototyping I
Synplify Pro/Premier Technology Enhancements for Next Generation High Capacity Designs
Andy Jolley [Synopsys Ltd]
The Introduction of higher complexity and high density FPGA Technologies introduces new challenges for the implementation cycle. This session overviews recent enhancements to Synthesis technologies that enable quicker design set-up and iteration times. The session also overviews support for latest P&R implementation software with new constraint formats.

A2 - User Session & Tutorial: Low Power
An ARM Cortex-M0 for Energy Harvesting Systems: A Novel Application of UPF with Synopsys Galaxy Platform
Jatin Mistry [University of Southampton], James Myers [ARM]
In energy harvesting systems, energy is effectively infinite but output power is severely limited. In this paper we first present a novel state retention power gating technique, called Sub-Clock Power Gating, which addresses this ultra-low power budget. It works in synergy with voltage and frequency scaling and power gates combinational logic within the clock cycle to reduce active power. Secondly, we describe how the technique was implemented on an ARM Cortex-M0™ microprocessor for fabrication and discuss our experience of using UPF with Synopsys' Galaxy Platform to achieve the required power gating. Finally, silicon measured results are given.

Formality Low Power Equivalence Checking with UPF
Tom Ryan [Synopsys Ltd]
This tutorial presents advanced topics associated with low-power equivalence checking using UPF. Learn information and techniques that help you understand and efficiently debug low-power UPF verifications in Formality. See how you can provide the required setup to obtain a complete verification that covers all power states. Hear about common issues that may be encountered during low-power verification and how you can easily resolve them.
Target audience: Formal equivalence checking users of low-power designs.

A3 - Tutorial & User Session: Front End Implementation & Signoff I
Galaxy RTL: Design Compiler Family Update
Rod Carroll [Synopsys Ltd]
This tutorial presents the latest advancements in the Design Compiler family of products including DC Explorer, Design Compiler Graphical to help you achieve best-in-class quality-of-results in the shortest possible time. See how you can speed-up the development of high-quality RTL & constraints with DC Explorer for a faster design implementation and generate an early netlist to start physical exploration in IC Compiler even when your design data is incomplete. Learn methodologies to achieve superior design results while streamlining the flow for a faster, more predictable design implementation using physical guidance technology (SPG) in Design Compiler Graphical. Finally hear about how you can complete verification quickly with Formality equivalence checking without sacrificing quality-of-results.
Target Audience: RTL Designers, CAD Managers & Engineering Managers

Converting Existing Software to Hardware using SynphonyCC: A Case Study of an Open Source Connect-6 Solver
Sumanta Chaudhuri, Peter Y. K. Cheung [Imperial College London]
The goal of this work is to evaluate the ease with which we can convert existing C/C++ code to hardware using off-the-shelf High Level Synthesis (HLS) Tools. In this article we used used Synphony C Compiler (SCC) from Synopsys, and used an open-source Connect-6 solver as a case study.
Connect-6 is a newly invented game, and a part of the computer Olympiad. The open-source connect-6 solver is most suitable for this case study because it is a general purpose software not written with hardware implementation in mind. The preliminary unconstrained synthesis with SCC generates hardware which occupies 30% of the Cyclone II FPGA(EP2C70F896C6), runs at a clock frequency of 37.68 MHz, and takes 47984 cycles to make a move on average. This cycle count can be reduced to 28787 by using streams and exposing inter-loop parallelism. It faithfully reproduces the software behaviour.

A4 - Tutorial & User Session: Verification I
Next Generation VIP - UVM Methodology
Fabian Delguste [Synopsys France]
The number and complexity of standard interfaces is being driven by the demand for more features and higher performance. This creates new challenges for verification. How should the interfaces be incorporated into the verification plan? Given the increased complexity of the IP and its verification should 3rd party VIP be considered? How well would 3rd party VIP integrate into a UVM/OVM/VMM test environment? Is it possible to boost productivity when debugging complicated protocols by working at the protocol level? This presentation talks about the new generation of verification IP that addresses these issues. A Reference Verification Platform for the AMBA AXI/ACE protocol will also be shown as a means to accelerate ARM processor-based verification using Discovery VIP.
Target Audience: Engineers and Managers interested in the verification involving standard interfaces in a SystemVerilog testbench environment such as UVM, OVM or VMM.

Easier RAL - All You Need to Know About the UVM Register Layer
Doug Smith, Dr. David Long [Doulos]
UVM provides the framework to create register models referred to as the register abstraction layer (RAL). Describing a register model can be quite tedious and rather burdensome to maintain; hence, the need for an Easier RAL. In this paper, UVM RAL concepts like register blocks, address maps, adaptors, predictors, front-door/backdoor access, built-in sequences, and register coverage are explained. Likewise, the use of free register generators is shown. Using generators to build and maintain the register model along with some simple guidelines for integration provides the essential knowhow to quickly and effectively benefit from UVM’s Register Abstraction Layer.

A5 - Tutorial & User Session: Analog Mixed-signal / Full Custom Design I
Recent Developments in Field of SPICE and fastSPICE Circuit Simulation
Damian Roberts [Synopsys Ltd.]
This presentation will discuss the challenges of analog and mixed signal verification and the recent advances in Synopsys SPICE and FastSPICE tools that seek to address them.
Target Audience: Analog and Mixed-signal Verification Engineers

Mixed-Signal Behavioural Models : A Necessary Evil
Chris Brown [Mixed-Signal Verification Consultant]
This presentation will cover the need for behavioural models in mixed-signal design and verification. It will discuss the issues with creating behavioural models and how to verify the models are correct/accurate and fit for purpose
Target Audience: Mixed-Signal Verification Engineers

A6 - User Session & Tutorial: Design for Test
DFT for Fragmented Digital Blocks in Mixed Signal Designs
Richard Illman [Dialog Semiconductor]
Increasingly mixed signal designs have small digital blocks embedded within the analogue functions as well as a main digital core. This paper describes a scan compression architecture to minimise the impact and risks associated with this design style. It also describes the techniques used to ensure the accuracy of test coverage reporting in these types of designs.

Galaxy Test and STAR Memory System Updates
Dave Johnson [Synopsys Ltd], Yervant Zorian [Synopsys Inc]
This tutorial will provide information on the best use of recent enhancements to DFTMAX Compression and STAR Memory System. A review of the benefits and pitfalls of sharing I/O resource across multiple CODECs will be covered, along with how to debug designs to provide the best benefit of compression. The tutorial will also show how recent enhancements to STAR Memory System allow efficient support of Memory BIST and self-repair when using ARM Cortex-A9 and Cortex-A15 processors.
Target Audience: DFT Engineers and Managers, especially Engineers implementing designs using ARM cores.

Thursday, May 24, 2012
1:30 PM - 3:00 PM
B1 - User Session & Tutorial: FPGA Implementation and FPGA-based Prototyping II
Experiences Porting a Design from an ASIC Implementation Flow to an FPGA Flow
Mike Dunk [Infineon Technologies]
FPGA implementation tools have evolved down a different path to the commonly used ASIC implementation tools. Some of the differences are due to the physical limitations imposed by the FPGA architecture, but in some ways the tools are just "different". Consequently anyone who is used to standard ASIC synthesis/layout flows will suffer some culture shock when switching to the FPGA tools. This paper describes some of the experiences of porting a large multi-CPU microcontroller that had been designed using a standard ASIC flow onto an FPGA prototyping platform. Aspects covered in this paper include design considerations, such as clock network simplification and area/functionality reduction, and tool flow considerations, such as constraining and debugging.

Effective Strategies for Bringing Up and Debugging an FPGA-based Prototype
Frank McMillan [Synopsys Ltd]
Timely achievement of functional prototype can be a difficult and imposing task. Each stage of design bring-up imposes unique requirements and challenges. This tutorial will focus on how to ease the bring-up and debug process by (a) defining the goals and requirements of each bring-up phase and (b) demonstrating the corresponding bring up and debug techniques that best meet the requirements.
Target Audience: Current or potential FPGA-based prototypers looking for efficient ways to debug their platform.

B2 - Tutorials: Back End Implementation I
Creating Multi-IO Ring Die Using IC Compiler
Colin Davidson [Synopsys Ltd]
As technology nodes continue to shrink, often die size is limited by the size required to form a single, perimeter ring of IO drivers. To minimize die size, most design teams faced with pad limited die sizes are turning to multi-IO ring layouts. This tutorial walks through how to create multiple IO rings on a die, and how to populate the rings with both general purpose IO drivers and IO macros. The multi-IO ring layouts can be used for both wire bond and flip chip packaging.
Target Audience: Physical Design Engineers and Managers

Double-Patterning Aware Extraction & Signoff at 20nm
Clay McDonald [Synopsys]
This tutorial will cover 2 topics addressing parasitic extraction when designing for smaller geometry nodes: With the increased amount of design data to be handled at chip-finishing, any ECO performed at this late stage usually has significant impact on turnaround time. To reduce this TAT, we will look at a new approach for the handling of metal fill as part of parasitic extraction for STA. When targeting designs for fabrication at 20nm or below, multi-patterning techniques are being adopted to overcome lithographic limitations. This second section will look at the changes being made in the parasitic extraction flow to cater for multiple mask usage to meet these manufacturing needs.

Dealing with Metal Fill in 28nm ECO Extraction Flows
Clay McDonald [Synopsys]
This tutorial will cover 2 topics addressing parasitic extraction when designing for smaller geometry nodes: With the increased amount of design data to be handled at chip-finishing, any ECO performed at this late stage usually has significant impact on turnaround time. To reduce this TAT, we will look at a new approach for the handling of metal fill as part of parasitic extraction for STA. When targeting designs for fabrication at 20nm or below, multi-patterning techniques are being adopted to overcome lithographic limitations. This second section will look at the changes being made in the parasitic extraction flow to cater for multiple mask usage to meet these manufacturing needs.

B3 - Tutorial & User Session: Front End Implementation & Signoff II
Getting the Most from Synthesis to Improve Your Datapath QoR
Reto Zimmermann [Synopsys GmbH]
With Datapath content increasing in today’s designs, it is more important than ever to understand how to take advantage of the advanced datapath features in your implementation flow. This session will review recent and upcoming updates to the DesginWare Datapath technology that can help you achieve QoR goals in your design. New features including the Internal Rounding in the top-down compile flow and the Datapath Extraction analysis features will be the focus of this presentation. Additionally, a brief refresher of the Datapath RTL coding guidelines will also be presented.
Target Audience: Design Engineers, Engineering Managers and Chip Architects

Applying Multi Corner Multi Mode Methodology on an Interface IP
Seyda Aygin [Ericsson Microelectronic Design Center]
Converting timing information from a standard that contains 7 different speed modes (400 KHz – 208MHz), 2 different voltage signaling levels and DDR (Dual Data Rate) mode to timing constraint is challenging. If multiple scenario optimizations are performed only in the back-end flow, this can result in fixing timing violations at a very late stage of the flow. It can be very critical especially if these timing violations are setup violations and RTL fix is required. We have used the Design Compiler Multi Corner Multi Mode methodology (MCMM) for our timing checks before delivering our interface IP RTL and timing constraints to RTL2Netlist team to overcome this challenge. This article presents:
• How each timing information, such as duty cycle variation, input clock rise/fall times and se-tup/hold timings, is converted into Synopsys timing constraints
• MCMM usage experience in synthesis flow
• Comparison of results between MCMM and single scenario results

B4 - User Session: Verification II
I Spy with My VPI: Monitoring Signals by Name, for the UVM Register Package and More
Jonathan Bromley [Verilab]
Verification environments commonly need to react to value-changes on arbitrary DUT signals that are not part of a standard interface protocol. The package presented here supports both value probing and value-change detection for signals identified at runtime by their hierarchy name, represented as a string. This provides a useful enhancement to the UVM Register package, allowing the same string used for backdoor register access to be used also for value-change detection. It is also an interesting case study in the use of SystemVerilog DPI and VPI in the same package. For environments entirely coded in SystemVerilog, the package is completely portable. We also discuss how it can be applied to VHDL signals in a mixed-language environment. The package source code will be freely available under the Apache 2.0 licence.

A Beginner's Guide to Using SystemC TLM-2.0 IP with UVM
Dr David Long, John Aynsley, Doug Smith [Doulos]
UVM 1.x includes support for the communication interfaces defined by the SystemC TLM-2.0 standard, although some implementation details differ. This enables integration of SystemC TLM-2.0 IP into a SystemVerilog UVM verification environment. The connection between SystemC and SystemVerilog currently requires a tool-specific language interface such as Synopsys TLI, since it is not yet implemented as part of UVM. This paper begins with a brief overview of TLM-2.0 aimed at novice users. It then discusses the steps required to add a SystemC TLM-2.0 model into a SystemVerilog UVM environment and simulate it with VCS. At each step, issues that users will face are explored and suggestions made for practical fixes, showing the relevant pieces of code. Finally, the paper gives a summary of areas where the UVM implementation of TLM-2.0 differs from the SystemC standard and proposes workarounds to ensure correct communication between the SystemVerilog and SystemC domains.

B5 - User and Tutorial: Analog Mixed-signal / Full Custom Design II
An Alternative Approach to Connect Modules in Verilog-AMS
Peter Grove [Wolfson Microelectronics]
In general the connectivity and feedback loops between the analogue and digital can be checked using known Verilog-D techniques, such as real number modelling, $bits2real and Manchester encoding. These methods are very useful to check connectivity and system level functions when the underlying models are good enough. For some blocks it is important to run what is known as a mixed mode simulation, where the digital is run in the digital simulator and the analogue is run in a Spice simulator.
In most designs the interface between the digital and analogue blocks uses level shifters of some kind. By leveraging this it is possible to create a flexible a2d/d2a model that makes use of these instances and reduces the number of automatic insertion of connect modules. This paper explains how the flexible level shifter model can be created and how this can be used in a real situation using VCS® AMS capabilities.

The Generation of Timing Views for Analogue IP Delivery
Andy Milne, Synopsys Ltd. [Synopsy Ltd.]
One of the main challenges in designing analogue IP is ensuring its successful integration into a full mixed signal SoC. Typically, top level implementation and timing verification for these SoCs is carried out using industry standard digital tools such as ICC and PrimeTime. In order for the analogue IP to efficiently fit into these digital flows, it is necessary for the timing characteristics of the block to be described in 'liberty' (.lib) format. Accurately characterising mixed signal blocks for timing can be a complex and time consuming task.
Target Audience: Analog and Mixed-signal Verification Engineers

B6 - Tutorial & User-Tutorial Session: Lynx Design System
A Complete Audio IP Subsystem for Your SoC in Minutes
Raza Malik [Synopsys Inc.]
Audio requirements for consumer products continue to grow: devices become internet-connected, multi-channel content is everywhere, plus consumers want features like virtual surround sound. The industry continues to demand shorter time-to-market, lower risk and lower cost. This can be accomplished by using pre-integrated, pre-verified IP subsystems that take away all the traditional hardware, software and prototyping effort, and enable seamless plug-in to the application (software) on the host processor.
This session discusses how the DesignWare SoundWave Audio Subsystem enables designers to create a complete audio solution for their SoCs in minutes.
Target Audience: Design Engineers, Software Engineers, Chip Architects and Engineering Managers

Taking the Cost and Guesswork out of Building a Technology Proven Flow
Richard White [PicoChip]
For companies without dedicated CAD departments to develop their in-house flow, engineers can find their time wasted fixing flow related issues and not focusing on adding real value to their designs. As the drive to ever smaller nodes continues, a proven flow at a previous technology becomes unproven at the new node. Which means development work and investigation must be repeated. These are heavy costs for any size company to bear. Lynx offers a technology-proven solution for such companies, takes the guesswork out of this process and lets you get back to what you do best--bringing your unique technology to reality quicker and more reliably. This paper will explore the benefits of using a pre-validated production design system to efficiently move to a new technology node and discuss the level and type of customisations that are required to match the design system to the SoC under development.

Thursday, May 24, 2012
3:30 PM - 5:00 PM
C1 - User Session & Tutorial: FPGA Implementation and FPGA-based Prototyping III
Making the most of FPGA Prototyping with the Universal Multi-Resource Bus (UMRBus)
Paul Robertson [Broadcom]
The Universal Multi-Resource Bus (UMRBus) is a high-performance communication bus that has can be used for a variety of applications to assist with the bring-up, management and usage of high-capacity FPGA Prototype Platforms. The UMRBus can be driven by a variety of S/W applications to allow for system configuration and remote access, Device-Under-Test (DUT) Stimulation and Analysis, Co-Simulation and even Hybrid and System Prototyping. This paper overviews the usage of the UMRBus throughout the lifecycle of a real-world FPGA Prototyping Project. It covers the different use modes adopted at various points in the project including the control of user defined debug techniques. The paper provides details of application techniques and provides best practice recommendations.

Clash of the Titans: Hybrid Prototyping, the Combined Strength of both Virtual and FPGA-Based Prototyping
Michael Posner [Synopsys Inc]
Every engineer now knows that no longer can hardware be designed without considering all the aspects of the software which will run on it. More importantly hardware validation can no longer be completed without firmware & software but these cannot be completed without an accurate representation of hardware. Catch 22 !!!
Prototyping technologies are key to addressing hardware and software development issues. Each approach is recognized as bringing value, but the main question in the users mind is typically what is the effort involved in utilizing them.
This session is intended to promote understanding of prototyping in its various forms and their application to the task of hardware-software development, integration, debug and validation. It includes technical information on three prototyping approaches: Virtual prototyping, FPGA-based prototyping and Hybrid prototyping, utilizing both Virtual and FPGA-based prototypes creating a unified prototype that leverages the relative strengths of each technology. This session is especially valuable to existing FPGA-based prototyping users who with a small incremental effort can bring up their prototype typically 3-6 months earlier, even before all RTL is available and at the same time enhance their firmware/software development and debug environment.
Target audience: FPGA-Based Prototypers with large Third-Party Cores

C2 - User Session & Tutorial: Back End Implementation II
Reducing Silicon Real Estate Through Layer Aware Buffer Optimisation
Nigel Hughes [Intel]
Recent trends in silicon process technology have lead to an increasing variation in electrical parameters such as metal layer resistance; to an extent that a modern process node typically exhibits 20 times less resistance for the upper routing layers. This has lead to significant challenges to ensure pre/post layout extraction correlation of the intended routing topology implemented during the place and route flow. This variation also provides the opportunity to target lower resistance layers in order to reduce the amount of signal buffering required during optimization and thus save chip area. Using the latest IC Compiler’s optimization flow; to perform Layer Based Optimization. This placement based feature targets specific fanout networks in the design.
We discuss the usage model for this approach, observed area savings as well as enhancements to the design performance such as routability and timing, using an advanced Intel design.

Faster Top-Level Closure With Transparent Interface Optimization
Jon Dawes [Synopsys Ltd]
Transparent Interface Optimization (TIO) in IC Compiler is a new capability that addresses the challenges of gigascale design and enables faster top-level closure. This tutorial will provide designers technical information on TIO, its usage, current capabilities and roadmap.
Target Audience: Design and CAD Engineers and Managers responsible for physical implementation and verification

C3 - User Session & Tutorial: Front End Implementation & Signoff III
Timing Sign-off with Statistical Variability: Advanced On-Chip-Variation Modelling (AOCVM) - the theory and the practice
Andrew Appleby, Touqeer Azam, Sonia Caldwell, Feng Hong, Mark Scoones [CSR]
Statistical variability has been threatening digital designers for many years. However, it is only now with transistor dimensions below 45nm that we are really starting to see problems in design sign-off. Traditional design methods are becoming more and more pessimistic due to variability, and approaches that use worst case derates can lead to overdesign and longer time to closure. Various approaches to variation and margin management have emerged since the inception of static timing analysis tools. In this paper we will examine the sources of device variation, and consider the available methodologies for modelling variation in static timing based sign-off flows. We will discuss some of the considerations of generating AOCV tables including the design environment within which the tables will be used. This paper highlights how the correct choice of input slew, interstage capacitance and voltage for the tables can significantly affect the quality of results.

ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Simon Bloyce [Synopsys Ltd]
PrimeTime’s 2011.12 release extends the production-proven ECO technology from earlier releases to multiple new areas of design rule constraint (DRC) fixing. Together, PrimeTime ECO enables you to perform ECO fixing for timing and DRC across multiple scenarios in parallel using CPU resources efficiently from your compute environment. New enhancements in DRC fixing include trade-offs for timing costs and a flexible approach to utilizing compute resources for multi-scenario fixing. This tutorial is for designers responsible for timing convergence and signoff and will show how users are effectively using PrimeTime’s ECO solution with the latest ICC flows.
Target Audience: Timing signoff Engineers and Design Managers

C4 - User Session & Tutorial: Verification III
Property Checking of Datapath using Word-Level Formal Equivalency Tools
Theo Drane [Imagination Technologies], Himanshu Jain [Synopsys, Inc]
The construction of datapath offers considerable verification and validation challenges throughout the design process; whether this be proving equivalence between system-level, RTL and gate-level models or validating the design itself. Furthermore, there may be properties required by specifications, standards or the surrounding datapath logic that are essential for correct function. Examples of these properties include proving termination of iterative algorithms, error bounds and permutativity. Using the latest Boolean equivalence checkers that work at the word-level, it is possible to prove such word-level properties of datapath designs. In this work we present a variety of datapath properties and their motivation. We show how these properties can be written and present the results of checking these properties using a word-level Boolean equivalence checker. The ability to check these properties efficiently allows us to safely use smaller more efficient hardware, improve code reliability, reduce time to discovering hard corner case bugs and minimise validation effort.

Debugging Low-Power Simulations
Bhavesh Patel [Synopsys, Ltd]
Low power designs are complex to verify and very time consuming to debug. Shortening the debug time for low power simulations helps to increase overall verification productivity. With the help of examples, this session will cover the common failure signature of low-power simulations and recommended approach on how to debug typical failed low-power simulations. The goal of this session is to provide users an introduction on debugging LP simulations.
Target Audience: Engineers and Managers interested in the verification of low power designs. Familiarity with low power design techniques would be helpful.

C5 - Tutorials: Analog Mixed-signal / Full Custom Design III
A Timing Shell Approach to Integrating Mixed-signal Macros into a Place and Route Flow
Damian Roberts [Synopsys, Ltd]
The ever increasing complexity of SoC designs, with blocks from an ever greater number of sources (IP, analog, mixed-signal) requires a much smoother interoperability between full-custom and semi-custom tools. One key functionality is the exchange of full custom macros between a full-custom and a synthesis/place and route environment, which is a time consuming and critical task. This presentation will demonstrate how Synopsys’ IC Compiler – Custom Designer Co-Design can be used to implement such a methodology, which makes the interface circuitry (Timing Shell) available to Custom Designer as well as to IC Compiler.
Target Audience: Designers of Analog and Mixed-signal blocks. ICC users needing to integrate such blocks into their designs

CustomExplorer Ultra – Meeting the Mixed-signal Verification Challenge
Paul Chapman [Synopsys, Ltd]
Mixed-signal verification and regression has thousands of simulations to setup and manage, complex test bench and corner setups, and a massive amount of data to analyze. Multiple data formats, languages, and simulators need to be supported. This tutorial shows how CustomExplorer Ultra addresses these challenges to increase mixed-signal verification productivity while also simplifying the process.
Target Audience: Designers of Analog and Mixed-signal blocks

C6 - Tutorials: Design IP
Best Practices for Implementing Memories and Libraries to Deliver Superior PPA
Zaka Bhatti [Synopsys, Inc]
Selection of memory compilers and logic libraries has significant impact on the power, performance and area of SoC designs. This tutorial presents best practices for implementing the optimal combination of memories, libraries and embedded test and repair to meet your design requirements. Also learn how the DesignWare Memory Compilers and Logic Libraries are used in conjunction with Synopsys tools including ICC and DC to deliver a high-performance, low-power and differentiated SoC design.
Target Audience: Design Engineers, System Architects

The Evolving Integrated Communication AFE
Luis Matias [Synopsys Portugal]
The AFE is a critical element of the communications transceiver. This tutorial looks into the building blocks that make up the AFE and how its requirements continue to evolve as more advanced communications protocols are developed. The characteristics of the AFE for several communication systems will be reviewed and best practices for its integration within today’s complex SoCs discussed. This tutorial also provides an overview of the DesignWare® Data Converter IP Portfolio and how it is used to create efficient analog interface solutions that are robust and meet the integration requirements of the SoC developers.
Target Audience: Design Engineers, System Architects

Non-Rectilinear FRAM Generation
Chai Siew Fong, Ang Boon Ching, [Intel]
Non-rectilinear polygon on die always pose challenge to designers during macro FRAM generation. A typical source of non-rectilinear shape will be PAD and diagonal routing. The intent of this paper is to share the solution for non-rectilinear shape FRAM generation as well as non-rectilinear polygon MilkyWay outputting format’s impact.