| | Preliminary topics include (but are not limited to):
- High Performance Design (Low-Power Design, Top-Level Integration and Optimization, High Performance Methodologies for applications such as Graphics/GPUs and Processors)
- Applying Advanced Technologies (Advanced node, 3DIC, FinFET)
- Accelerating SoC Verification (Full Chip Validation, Digital Block Verification, Analog-Mixed-Signal Verification, Low-Power Verification)
- Prototyping (Virtual Prototyping, HAPS, Hybrid Prototyping)
- Designing and Verifying FPGAs
- Selecting and Integrating IP
- Managing and Optimizing the Compute Infrastructure for EDA Applications (High Performance Computing, queue & job management, storage/CPU/license resource management, impact of emerging technologies on EDA)
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| Required Templates | |
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| Dates to Remember |
| April 10, 2013 |
Call for papers opens |
| June 3, 2013 |
Call for papers closes |
| June 3, 2013 |
Preliminary Acceptance Notification |
| July 9, 2013 |
Draft Papers due |
| August 14, 2013 |
Final Papers due |
| September 10-11, 2013 |
SNUG Taiwan | |
SNUG thanks the members of the 2013 Technical Committee who volunteer their time and expertise to ensure SNUG’s technical quality, local perspective and value to the users of Synopsys tools and technology.