Ambassador Hotel
Hsinchu, TaiwanTuesday, August 28, 2012
Wednesday, August 29, 2012
| Time | Description | | | August 28, Tuesday | | 9:20-10:10 | Keynote: Deirdre Hanford
Sr. Vice President
Synopsys | | 10:10-10:20 | Welcome - SNUG Technical Committee | | 10:20-10:40 | Break | | 10:40-11:20 | VIP Keynote | | 11:20-12:00 | VIP Keynote | 12:00-1:30 | Lunch
| | 1:30-3:30 | TA1: High Performance Cores (HPC)
Processor and Application Development Ecosystem
High-Performance Cores: Design User Experiences | TA2: Verification
Verification Reference Platform
Regression Performance Management
Low-power Assertion and Coverage | TA3: AMS
Simulation Performance
IR Analysis
Library/Memory Characterization | | 3:30-4:00 | Break | | 4:00-6:00 | TB1: High Performance Cores (HPC)
Case Study: Techniques for High-Performance Cores using Synopsys Galaxy Platform
"Ask the Experts" Panel | TB2: Syn/LP/FM
UPF Flow Experience Sharing
DC/FM SVP Flow
Low Power with Designware
DC Explorer Technology | TB3: System-Level Design
ESL for Processor Design
Designing Programmable Hardware Accelerators
Accelerate Software Development |
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| Time | Description | | | August 29, Wednesday | | 9:20-10:00 | Keynote: Simon Segars
EVP and General Manager
ARM | | 10:00-10:20 | | | 10:20-11:00 | | | 11:00-11:40 | VIP Keynote | | 11:40-12:00 | Best Paper Award
SNUG Technical Committee | 12:00-1:30 | Lunch
| | 1:30-3:00 | WA1: Physical/Low Power
UPF Experience Sharing
ICC Technology
3D-IC Technology | WA2: Design for Test/PrimeTime
UPF Flow Experience Sharing
AOCV Technique
DFT SDD
New PrimeTime Technology | WA3: IP
IP Solutions from Synopsys and Leading Foundry Partners | | 3:00-3:30 | Break | | 3:30-5:30 | WB1: High Performance Cores (HPC)
High-Performance Core Design Clocking Techniques
Achieving Core Hardening Objectives
Case Study: Low Power on High-Performance Cores | | WB3: FPGA
ARM Prototyping
FPGA Prototyping Including Synopsys IP | Sponsor Expo
5:00 - 6:30
Lucky Draw
5:30 | | 6:30 | | |
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