SNUG Silicon Valley Abstracts  

Monday, March 24, 2014
9:00 AM - 10:30 AM
Welcome and Keynote:
Designing Change
Dr. Aart de Geus, Chairman and co-CEO -Synopsys Inc.
In our current semiconductor design community, the word "change" is, to say the least, an understatement. From a dizzying array of emerging "smart" niche end-products to major market trend shifts to ecosystem reconfigurations at every level, the world around us is morphing at an unprecedented pace. The challenge for designers to keep pace has never been greater.

The good news is that we're up for it! In his presentation, Aart will give an overview of many years of investment and innovation efforts, resulting in an exciting sweep of major new design productivity advancements in our design and verification platforms.


Monday, March 24, 2014
11:00 AM - 12:30 PM
MA-01 ICC Update
IC Compiler 2013.12 Release Highlights
Mohan Aswathnarayan - Synopsys, Inc.
IC Compiler's I-2013.12 release delivers significant improvements in timing, area and power for high-performance designs, as well as enhanced support for emerging nodes (20nm, 16nm, and 14nm) throughout ICC’s place and route flow. Topics covered in this session include full flow improvements and major enhancements on the timing front, including path based AOCV analysis, post-route AWE delay calculation, and PT correlation checker. We will also provide a hierarchical flow update, including support for RDL shielding and data flow analysis (DFA) layout window integration, and an update on the low-power methodology, which has been simplified via golden UPF support. DFA and low-power design implementation will be explored in greater detail in other SNUG technical sessions.

Synopsys Tools Used:
IC Compiler

Target Audience:
IC Compiler users


MA-02 Physical Implementation
Routing DDR PHY Matched Length Signals Using Galaxy Custom Router
Maged Attia - Synopsys, Inc.
In this tutorial you will learn how Galaxy Custom Router and IC Compiler running within the Lynx Design System will achieve faster time to quality results for high-speed DDR/PHY designs. Galaxy Custom Router, in conjunction with IC Compiler, allows designers to develop a unique mixed-tool design flow that addresses the high-speed and low-skew requirements of DDR I/O routing. It also addresses floorplanning, placement, and routing for large DDR digital cores. This tutorial will demonstrate Galaxy Custom Router's capabilities to route precision matched-length signals, resulting in hand-crafted quality at a push of a button.

Synopsys Tools Used:
IC Compiler, Galaxy Custom Router

Target Audience:
Physical implementation engineers


MA-03 Low-Power Implementation
Low-Power Implementation of Complex MIPS Cores
Maya Mohan, Nagesh Sakhamuru - Imagination Technologies
Dynamic power is a major component of the total chip power, and getting lowest power with balanced frequency and area is the key to successful SoC. It is one of the primary ingredients driving the success of MIPS cores. In an effort to get the optimal power of the MIPS cores, we started focusing on some of the key areas within Design Compiler and IC Compiler tools and making calculative changes in methodology along with IP selection process.

This paper focuses on factors affecting dynamic power and tradeoffs considered for the MIPS family of CPU cores. Some of the key areas in Synopsys DCT and ICC flow that helped in reducing dynamic power are SPG based optimization, SAIF based optimization, self-gating, power options in place/clock/route steps, and Concurrent clock and data optimization (CCD). Selection of technology-specific Standard cells and Memories also played a key role in achieving the optimal dynamic power goals.

Synopsys Tools Used:
Design Compiler Topographical, DCG, IC Compiler

Target Audience:
Intermediate

Low-Power Design in the FinFET Technology
Benjamin Mbouombouo - LSI Corporation
As the planar technology hits the device scaling limit in the 16nm channel length range, leakage power accounts for an increasing portion of the total power consumption. The FinFET technology introduces a paradigm shift addressing this specific limitation, where it has not only a better scalability, but also better short-channel characteristics and a more effective way to suppress the leakage. The FinFET technology brings a significant performance increase compared to planar technology, while at the same time introducing a new challenge pertaining to high input cell capacitances on FINs.

With this new reality, the dynamic power has become the dominant factor in total power calculation, and there is also a new behavior regarding the cells selection for faster timing closure.

Synopsys Tools Used:
Design Compiler Topographical with minPower Design Ware, PrimeTime PX, PrimeTime, Power Compiler, IC Compiler

Target Audience:
Advanced


MA-04 Circuit Simulation
CustomSim-Based Comprehensive EM/IR Analysis, Visualization, and Violation Correction
Gaurang Chaudhari, Sateesh Chandramohan, Prashant Lokeshwar - ARM; Danny Cheng, Darren Hsu - Synopsys, Inc.
Shrinking geometries and higher clock frequencies have made IR Drop and Electromigration (EM) analysis a critical sign-off step. In this paper we discuss the use model of CustomSim's Native Reliability Analysis features to perform EM/IR analysis. We also discuss how the integrated environment of CustomSim RA and CustomSim RA Viewer analyze, visualize, and fix the violations. This paper also describes possible automation from the analysis stage to violation corrections.

Synopsys Tools Used:
CustomSim Reliability Analyses, CustomSim RA Viewer, StarRC, and SPRES

Target Audience:
Intermediate

Low-Power and Simulation Performance in Mixed-Signal
Dave Cronauer - Synopsys, Inc.
In this session, we will review the recent enhancements in the Discovery-AMS mixed-signal area, with a focus on two particular enhancements. We will discuss how low-power simulation with UPF can be used in mixed-signal, and we will discuss techniques to control the power for analog and digital blocks. We will also describe how save and restore can be used to improve the performance of mixed-signal simulations. Save and restore can be used in regression testing where all tests share the same start-up/initialization phase. It allows skipping the start-up phase by using the saved results from one simulation in the other simulations.

Synopsys Tools Used:
VCS, CustomSim-XA

Target Audience:
Mixed-signal verification engineers who need UPF based low-power verification and/or mixed-signal verification engineers who want to improve the performance of their regressions with Save and Restore


MA-05 Verification Vision
Next Order of Productivity and Performance through Technology, Methodology, and Integration
Arturo Salz - Synopsys, Inc.
SoCs are transforming the electronics industry by integrating a staggering amount of functionality into high-performance, low-power, single-chip implementations with embedded software. Inevitably, as SoCs become larger and more complex driven by the convergence of functionalities, they strain the performance and productivity of verification methodologies and tools.

Verification tools have served fairly well, but are increasingly limited by the complexity of simultaneously validating different abstraction levels. The combination of abstraction levels and verification flows introduces new classes of failure modes impossible to verify by any single method. This has led to a new paradigm of verification by massively integrated techniques. Recently introduced in Verification Compiler, this concept integrates many novel technologies that lay the foundation for future technology breakthroughs. In this presentation, Arturo Salz, Synopsys Scientist, offers his view on verification technology trends and looks into the crystal ball on how Verification breakthroughs embodies a rethink of SoC verification.

Synopsys Tools Used:
VCS, VIP, ZeBu, Verdi, MVSIM

Target Audience:
Verification engineers and managers


MA-07 Signoff - Physically Aware ECO Flow
An Investigation of the Efficacy of PT-ADV in a Non-Synopsys PnR Flow
Jim Fong - Rambus; Po Leung - Synopsys, Inc.
Leakage recovery and fast ECO via physically aware data are intriguing features for ASIC flows. In our case, we have a non-Synopsys PnR flow but were able to demonstrate the efficacy of leakage recovery and physically aware ECO for four sample designs in 28 nm. Minor massaging was required to translate ECO tcl from PT-ADV into a usable form for our PnR. Most ECO suggestions from PT-ADV were implemented in our flow with good timing correlation after going through the PnR ECO fix.

Synopsys Tools Used:
PrimeTime

Target Audience:
Advanced

PrimeTime ECO - Now Physically Aware
Troy Epperly - Synopsys, Inc.
Join us as we introduce the latest physically aware advances in PrimeTime ECO technology, designed to ensure even faster convergence with implementation and ultimately shorter ECO turnaround time. We will describe how PrimeTime ECO is now placement, routing, and congestion aware - identifying DRC and timing fixes that result in minimal disruption to an existing netlist.

As part of this tutorial, we will share a range of best practices for getting the most out of these PrimeTime ECO physically aware enhancements and provide examples of the impact they are already having on real customer designs. We will also describe how these new physically aware enhancements and the IC Compiler Minimum Physical Impact (MPI) capability combine to maximize ECO QoR and minimize ECO turnaround time.

This tutorial is a must-see for any designer seeking to spend less time on ECO iterations.

Synopsys Tools Used:
PrimeTime SI

Target Audience:
Designers interested in signoff-based timing and design closure


MA-08 DDR4 and LPDDR4 IP
Faster DRAM: What You Need to Know About LPDDR4-3200, DDR4-3200, and Next-Generation DRAM
Graham Allan, Mark Greenberg - Synopsys, Inc.
DDR SDRAM devices continue to evolve, and mobile devices like LPDDR4 are getting faster and more mainstream than their "PC" DDR counterparts, such as DDR3/4. Even though 3200Mb/s is achievable with both LPDDR4 and DDR4, these interfaces are significantly different compared to the mobile and PC DRAMs that preceded them. What follows LPDDR4 and DDR4 is a technologically challenging roadmap featuring several application specific DRAMs.

This presentation compares the requirements of LPDDR4 IP against those for DDR4 IP. It also examines how a low-power PHY can be made to run at 3200Mb/s with the new LPDDR4 features and signaling in a mobile application compared to the reliability, availability, and serviceability features of the DDR4 IP, enabling DDR4 to meet the requirements for enterprise/server/storage SoCs. We will also look at next generation DRAM technologies that may replace or complement LPDDR4 and DDR4.

Synopsys Tools Used:
DesignWare DDR4 and LPDDR4 IP

Target Audience:
System Architects, Design Managers, and Design engineers who will be working with DDR or LPDDR"


MA-09 HAPS
Automating SoC RTL to Operational Prototype
Ajay Jagtiani, Joseph Marceno - Synopsys, Inc.
The size and complexity of the latest generation of ASIC/SoC designs put extraordinary pressure on prototyping specialists to deliver high-performance FPGA-based prototypes as quickly as possible. Time-to-first-prototype is a key period in the schedule that demands high capacity, rapid implementation, and a high degree of software automation. This session will introduce Synopsys' next generation HAPS software design environment for multi-FPGA implementation, providing superior automation, fastest time to operational prototype, a path to maximum system performance, and high productivity.

Synopsys Tools Used:
HAPS-70

Target Audience:
Current HAPS users and engineering managers responsible for ASIC/SoC prototyping who are seeking the latest methods and tools to accelerate FPGA-based prototype bring-up


Monday, March 24, 2014
12:15 PM - 2:00 PM
MA-10 Implementation Lunch and Learn
Winning the Productivity Challenge - Tapeout Success at the Leading Edge of IC Design
Despite a surge in physical design challenges in recent years, designers continue to "Win the Productivity Challenge" against tight schedules, exploding complexity and stringent silicon technology. How do they do it? Join us for lunch and listen to the world's experts from leading semiconductor companies as they discuss breaking through productivity barriers in this thought-provoking session.


Monday, March 24, 2014
12:30 PM - 2:00 PM
MA-11 IP Lunch and Learn
Physical IP Development on FinFET - There's Nothing Planar About It!
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Embedded Memories and Logic Libraries at Synopsys
To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That includes scaling, lower power consumption and higher speeds. To achieve this, analog/mixed-signal development techniques and design styles have to be re-created and implemented with very close foundry cooperation. This session discusses the FinFET characteristics of physical IP design and how they differ from planar devices. It will describe the impact FinFETs have on existing circuit designs and layout topologies for widely used IP such as DDR, USB, PCI Express, embedded memories and logic libraries. In addition, this presentation will highlight the methodologies that incorporate advanced process qualification vehicles.


Monday, March 24, 2014
2:00 PM - 3:30 PM
MB-01 DC Update
Design Compiler 2013.12 Release Highlights
Jim Argraves - Synopsys, Inc.
This tutorial presents the latest advancements and methodologies in Design Compiler, including DC Explorer and Design Compiler Graphical, to help you achieve best-in-class quality of results while reducing design schedules. This session will discuss innovative optimization to achieve lower area along with usability improvements, such as the new cross-probing and RTL analysis capabilities for efficient debugging. Attend the session to see the highlights of the 2013.12 synthesis release that improves quality of results, reduces congestion, and enhances productivity for designs at established and emerging nodes.

Synopsys Tools Used:
DC Explorer, DC Ultra, and Design Compiler Graphical

Target Audience:
Frontend implementation engineers and managers


MB-02 Custom Physical Implementation
Best Practices for Custom Layout Productivity: How Laker Users Have Cut Layout Time in Half
Neel Gopalan - Synopsys, Inc.
Users who make the best use of the tools and methodologies available to them can substantially reduce the time it takes to create hand crafted layouts. In this tutorial, we will review the key steps in the custom layout creation process and highlight the best practices currently in use for reducing overall layout time. We will also show how layout methodology has been updated to maintain high productivity when laying out with FinFET devices. Layout methodology best practices will be illustrated using Laker Custom Design software.

Synopsys Tools Used:
Laker

Target Audience:
Physical design engineers and layout methodology engineers


MB-03 Physical Implementation
Implementation of Multi-Source Clock Tree Synthesis
Yina Tang, Tian Yang - NVIDIA; Yashpal Bhola - Synopsys, Inc.
One of the biggest challenges in high-performance chips and large complex designs is controlling clock latencies and minimizing skew. Conventional clock tree synthesis can result in long latencies, large skew, and more on-chip variation effects, while scripted custom solutions are difficult to scale and maintain. To address these challenges, the multi-source clock tree synthesis methodology (MSCTS) in IC Compiler is extremely useful.

In this paper, we will illustrate how multisource CTS can be implemented through IC Compiler multisource clock tree methodology and how it leads to better clock metrics. The native MSCTS solution in IC Compiler is scalable, maintainable, and repeatable, and the tool can make better decisions to take care of power and area metrics of the clock tree while targeting latency and skew.

Synopsys Tools Used:
IC Compiler

Target Audience:
Intermediate

Cloning DDR4 RDL Routing With Galaxy Custom Router (GCR) Editing Environment
Jiankang Wang, Young Koog - Samsung; Denis Goinard, Amit Patel, Nabil Yazdani - Synopsys, Inc.
The increased complexity of the DDR4 design running at 2400 Mhz requires tightly controlled skew and latency for the data, clock, and differential signals. Designing 72-bit DDR4 requires eight bytes of dq/dqs, and one additional ECC byte. With the help of the cloning functionality of the GCR Editing Environment, the effort is spent on one byte for the DDR pad/bump placement and RDL routing. Then the placement and RDL routing patterns are automatically cloned to all bytes of the DDR signals, along with the power/ground bump and routing structures with required signal:power:ground ratio.

Using the cloning feature greatly improved work efficiency, the quality of the DDR signal/power routing, and the latency and skew balancing crossing the DDR interface which reduced the DDR interface wire length variation by 9X over the previous method. GCR is an excellent addition to IC Compiler (ICC) users for complex SoC design. It allows sharing of the same design database, enabling concurrent editing, and routing of top level, which is essential for a high-speed, structured, customized approach.

Synopsys Tools Used:
IC Compiler, Custom Design

Target Audience:
Advanced


MB-04 Circuit Simulation
Verification Methodology for Array-Based Memories
Logic equivalence checking for custom-designed memories is a critical component in ensuring that the behavioral description in RTL correctly captures the design intent of the schematic netlist. One of the major challenges in this regard is the limitation of traditional logic-cone based formal verification techniques when applied to memories. The two primary reasons for this are limited support for memory components like sense amplifiers, bit-cells, and difficulty in mapping comparison points due to structural differences. This paper discusses a verification methodology for memory signoff. The paper also details the techniques used to exhaustively verify the different modes of memory operation encompassing both SRAMs and RFs to uncover real design issues.

Synopsys Tools Used:
ESP-CV

Target Audience:
Intermediate

Extracting Impulse Responses in HSPICE
David Banas - Altera Corporation
It is often desirable to use HSPICE, to characterize a linear, time invariant (LTI) system by calculating the impulse response of a transistor level netlist model of the system. However, generating an ideal Dirac delta function (or, equivalently, an ideal step function) using the standard independent source elements available in HSPICE is difficult, if not impossible. Furthermore, deriving the impulse response of the LTI system by performing an AC sweep analysis and Fourier transforming the results is an endeavor for advanced users only. We present a "trick," which can be used to circumvent this obstacle. Our trick makes use of the UIC option to the .TRAN command, in order to fool the simulation into producing the impulse response of the system under test (SUT), without resorting to a frequency domain analysis followed by the requisite Fourier transform. We explain how to use this trick in a simple example deck.

Synopsys Tools Used:
HSPICE

Target Audience:
Intermediate


MB-05 Verification IP
UVM Verification Using Verification IP
Thomas Bodmer, Karl Whiting - AMD; Vijay Akkaraju - Synopsys, Inc.
The AMD Fusion Controller Hub team is involved with designs that support multiple industry standard protocols which are implemented as individual controller IPs. This session will cover the team's experience in implementing a consistent verification environment for each of the IP blocks using the Universal Verification Methodology (UVM) class library for all their verification and integrating Synopsys Verification IP (VIP) for the following protocols: ARM® AMBA® AXI™, USB 3.0, UFS and GB. The decision to "buy" versus "make" their VIPs will also be discussed. Also covered will be details on using the VIPs to verify adherence to the protocol features, coverage, debug, performance, and enhancements.

Synopsys Tools Used:
VIP, VCS, Protocol Analyzer

Target Audience:
Verification engineers

Accelerated Verification of ARM-Based SoCs Using Highly Reconfigurable VIP and Custom Scoreboard
Bharti Verma, Neel Sonara - Broadcom Corporation; Frank Gerbig, Amir Nilipour - Synopsys, Inc.
In this paper, we will discuss how we used the highly configurable Synopsys Discovery Verification IP for the ARM® AMBA® standard and its built-in and ease-of-use features to verify a complex multi-CPU SoC design that spans various AMBA protocols. We will explain how writing design-specific scoreboards, in addition to using VIP system monitors to observe the transactions and check the protocol, helped us find bugs that had been missed in earlier verification. We will highlight the techniques used in writing the custom scoreboard using UVM-based VIP for the AMBA protocols and share our successful results deploying Discovery VIP in our verification flow. Since coverage closure was a main concern, we'll discuss how the built-in coverage planning and analysis tools helped us achieve this goal. Finally, we'll discuss how we used the VIP's performance analysis reporting feature to measure critical bandwidth and latencies across the design.

Synopsys Tools Used:
AXI, VIP

Target Audience:
Introductory


MB-06 Advanced System Verilog Constraints
Reverse Gear: Re-Imagining Randomization Using the VCS Constraint Solver
Bryan Morris, Paul Marriott - Verilab Canada Inc.; Jonathan Bromley - Verilab UK Ltd.
Randomization is usually used to create stimulus as well as interesting device-under-test configurations. With functional coverage, confidence that the interesting state space of the DUT has been hit can be achieved.

Since the constraint solver is so powerful, it is interesting to use it in reverse gear. Due to a SystemVerilog feature, it is possible to use it as a versatile checking engine. For example, after monitoring a transaction, you can use the existing constraints to determine the transaction kind, if it was a valid transaction or which errors have been observed.

This paper will describe techniques to use the VCS constraint solver, SystemVerilog class constraints, together with judicious use of state variables to build a powerful declarative engine for verification environments in order to answer questions of the form, "Which kind of configuration could have given me these values," as well as solve an equation for one of its variables.

Synopsys Tools Used:
VCS

Target Audience:
Advanced

Interchangeable SystemVerilog Random Constraints
Jeremy Ridgeway - LSI Corporation
SystemVerilog constraints are declarative in nature. To change the profile on a randomized value for a test, the class containing the constraint is extended, the new class instantiated in its place (e.g., via UVM factory), and simulation (re-)compiled. This approach is time- and knowledge-expensive.

We present a suite of SystemVerilog constraint building blocks that are instantiated during simulation. A front-end Flex parser dissects a constraint string, then interacts with VCS through the direct programming interface (DPI) to instantiate a SystemVerilog constraint at random-time on some value (in a type-parameterized container class). A test bench-wide resource manager like UVM maintains constraint strings composed before and during simulation.

With the advanced simulation profiler in VCS, we show that our constraints are competitive in solving time and, with some optimizations, in simulation time and memory. A significant overhead pervades but flexibility to fully interchange constraints without recompilation is valuable.

Synopsys Tools Used:
UVM, VCS Simulator (with DPI), VCS unified simulation profiler

Target Audience:
Advanced


MB-07 Leakage Recovery & ECO
Signoff Leakage Recovery
Helen Liang, Subash Sukumaran - Toshiba America Electronic Components, Inc.
Leakage power consumption plays a significant role in deep submicron CMOS technology. In PrimeTime version 2012.12, Synopsys introduced a new ECO feature to reduce leakage power while maintaining signoff QoR. This paper will discuss how the PrimeTime leakage recovery flow can be effectively used to reduce leakage power while maintaining signoff QoR and how it compares with other methods. We will also detail the steps of the PrimeTime leakage recovery flow and how we integrated this feature into our design tape out.

Synopsys Tools Used:
PrimeTime

Target Audience:
Advanced

Utilizing Signoff Based Multi Scenario ECO to Solve Unique Design Challenges
For timing closure, traditionally the number of modes are reduced wherever possible to save runtime and memory usage. But this paper discusses our experience of creating new modes as a divide-and-conquer approach, which helped us in reducing pessimism. Overhead of extra modes is reduced by adopting signoff ECO, which also removed additional pessimism by the use of PBA and AOCVM during fixing. This helped us not only for timing ECO, but regular hold fixing as well, leading to significant area/power saving and congestion reduction. This paper also discusses the unintended side effects of using the signoff ECO and workarounds.

Synopsys Tools Used:
PrimeTime

Target Audience:
Advanced


MB-08 Embedded Memories and Logic Libraries
Hardening DSPs for Performance and Power with DesignWare Logic Libraries and Embedded Memories
Ran Snir - CEVA
Devices continue to require better performance and longer battery life, demanding SoCs to deliver excellent speed and consume less power. DSP cores play a key role in SoCs targeting a wide range of end products, from smartphones and wearable devices, to wireless infrastructure. Depending on the application, these core implementations may target high or low speeds but they always seek to keep area and power dissipation very low. In this session, CEVA will present results and best practices in hardening DSP cores to achieve performance targets, while consuming low-power and minimal area utilizing Synopsys' 28-nm DesignWare Logic Libraries and Memory Compilers as well as Synopsys' implementation and signoff tools. CEVA will also show how choosing the correct IP and methodology helps achieve optimal results as well as discuss best practices to fine tune the results to reduce leakage power.

Synopsys Tools Used:
DesignWare Embedded Memories and Logic Libraries

Target Audience:
SoC/ASIC designers and system/chip architects who are interested in high-performance and low-power DSP core hardening


MB-09 HAPS
Achieving Maximum System Performance on Multi-FPGA designs using HAPS-70 System
Kiran Vedanabhatla, Xin Zhao, Padma Nagaraja - SanDisk; Maitrey Makim - Synopsys, Inc.
As a result of shrinking time-to-market and increasing complexity of designs, FPGA prototyping and full-SoC validation have emerged as crucial phases for an ASIC program to be successful. This paper provides an in-depth knowledge about smart techniques used in various stages of SoC validation for enterprise storage solutions. It includes architecting a high-level plan to prototype an entire SoC on HAPS-70 FPGA system, augmenting DesignWare IP blocks such as DDR3 to be FPGA compatible, bringing-up block-level IPs and their associated custom daughter cards, executing the entire design through high-performance HSTDM flow using Certify and debugging firmware, and hardware using integrated Identify & UMRBus. Using this approach, we can successfully build a robust full-SoC validation platform while achieving maximum system performance.

Synopsys Tools Used:
HAPS 70, Synplify Premier, Certify, Identify, UMRBus

Target Audience:
Advanced

High-Speed Reliable Interconnects on HAPS-70 Systems
Srikanth Annangi - Synopsys, Inc.
Design partitioning, pin planning, and interconnect planning are key challenges in prototyping large SoCs. Time Division Multiplexing (TDM) for data transfer across FPGAs is widely used for interconnect planning. This tutorial highlights the best practices and design automation tools to implement TDM techniques on HAPS-70 systems for High Speed Reliable Data Transfer and reduced interconnectivity. Session attendees will leave with a clear understanding of the High Speed TDM (HSTDM) Architecture and Error Check Mechanism, TDM signal grouping, TDM ratio selection, trace assignment, and system debug utilities for HSTDM implementation.

Synopsys Tools Used:
Certify, Identify, HAPS-70

Target Audience:
System validation and prototyping engineers, who are seeking advanced techniques for reliable and high-performance data transfer between FPGAs on HAPS-70


Monday, March 24, 2014
3:45 PM - 5:15 PM
MC-01 Advanced Physical Implementation
Innovative Technologies in Physical Implementation for Building Leading Edge SoCs
Saleem Haider, Neeraj Kaul - Synopsys, Inc.
Join us for an exciting look into a breadth of techniques and technologies designed to meet the growing challenges of IC design.

Target Audience:
Physical designers, technologists, and management interested in learning about advanced tools and methodologies


MC-03 Frontend Implementation
ECO Implementation Assistance and Advanced Debugging Using Formality Ultra
David Low - Synopsys, Inc.
This tutorial introduces Formality Ultra for ECO implementation assistance and advanced debugging. First, we will describe how Formality Ultra can speed up manual ECO implementation and verification processes. The session will cover the identification of the netlist areas that correspond to the RTL ECO changes, interactive design changes, fast verification of the ECO, and exporting of the ECO changes to downstream tools such as IC Compiler and Design Compiler. Next, we will show how the advanced features of Formality Ultra can be used to speed up the debug process for failing and inconclusive verifications.

Synopsys Tools Used:
Formality Ultra

Target Audience:
IC design engineers and managers who want to learn about advanced debugging techniques and the new Formality Ultra features to improve productivity during the functional ECO flow


MC-04 Circuit Simulation
Signal Integrity Analysis of High-Speed Serial Links Using HSPICE
Tetsuhisa Mido - Synopsys, Inc.
This tutorial introduces the latest features of HSPICE for high-speed channel designs and illustrates examples of how designers may utilize these new capabilities. At multi-Gigabit-per-second data rates, designers must analyze complicated, frequency-dependent effects in all system components throughout the signal path and make sure the design meets protocol specs by maximizing the use of techniques like impedance matching and equalization. New features of HSPICE, such as enhanced multi-port S-parameter handling and nonlinear-system-enabled statistical eye diagram analysis, are designed for this purpose and will be demonstrated in this session.

Synopsys Tools Used:
HSPICE, Custom WaveView

Target Audience:
Designers of high-speed communication channels such as DDR, USB, PCIe, HDMI, and Giga-bit Ethernet

Custom WaveView for Advanced Analysis, Debugging and Measurement Automation
Manu V Pillai - Synopsys, Inc.
Custom WaveView is widely used for waveform viewing, complex measurements, and regression purposes. The latest version of the tool, v2013.12, contains additional features for performing advanced analysis and debugging. This tutorial covers new features of Custom WaveView (some available prior to v2013.12), with more focus on advanced analysis debugging and measurement automation. The different types of jitter analysis, FFT, and Eye diagram in Custom WaveView are very useful for analog and SI applications. Custom WaveView's new DDR3/DDR4 specific measurements will help engineers perform very complex timing violations for DDR designs. Measurement automation with ACE-TCL and batch mode waveform comparison will help with verification and regression.

Synopsys Tools Used:
Custom WaveView, CustomExplorer

Target Audience:
CAD engineers, signal Integrity engineers, analog/mixed-signal designers


MC-05 Verification IP
Advanced Verification Techniques Applied to an ARM AMBA 5 Protocol-Based SoC
Tushar Mattu - Synopsys, Inc.
Market windows continue to shrink at the same time as SoC complexities increase, with multiple CPU clusters connected by cache-coherent interconnects and an increasing number of interface protocols. Verification IP (VIP) is at the heart of SoC verification and must deliver simulation performance, ease of use and productivity features that enable verification teams to hit their schedules. The current generation of wrapped VIP has run out of steam. This session will show how next-generation SystemVerilog VIP for ARM® AMBA® 5 CHI and other protocols delivers superior ease of use, performance, debug and validates complex cache state transitions for coherent protocols to accelerate schedules and improve product quality. Topics covered include verification planning, scenarios, tests, coverage, error injection, protocol aware debug, and protocol checking and performance analysis. You will learn how you can take a step up in productivity and bug-finding by using the next generation of verification IP.

Synopsys Tools Used:
VCS, VIP

Target Audience:
Verification engineers and managers


MC-06 Verification Methodology & Productivity
The "X" Factor: Address It in RTL Simulations
Imtiyaz Ron, Hari Sharma - Broadcom Corporation; Karim Ameziane - Synopsys, Inc.
In current verification cycles, gate-level simulations have become a necessary evil to discover any issues related to synthesis scripts, timing constraints, clock domain crossings, un-initialized logic etc. Due to shrinking timelines for projects, there is lot of pressure on verification engineers to reduce gate level simulation time. In gate-level simulations majority of the time is spent in debugging the dreaded "x-propagation" or "unknown propagation." A majority of these issues are due to "Pessimistic Xs." Buried under the piles of "Pessimistic Xs" are some of the "Optimistic Xs," which might mask real design issues. Finding these Xs buried under the mountain of other Xs is real challenge. Hence there is a need to bring cycle forward and find them in RTL simulations rather than gate-level simulations. This paper tries to provide a way to address "Optimistic X" issues in RTL simulations using the x-prop tool.

Synopsys Tools Used:
VCS

Target Audience:
Intermediate

UVM Transactions: Definitions, Methods, and Usage
Clifford E. Cummings - Sunburst Design, Inc.
Fundamental questions most novice UVM users have include: Why use classes instead of structs to define transactions for verification environments? What are advantages to using classes to represent transactions in a verification environment? What methods should be defined in a UVM transaction class and why are there both field macros and do_macros for creating the transaction methods?

This paper will detail advantages related to using class-based transactions and answer questions about why there is so much confusion surrounding transaction method definitions and usage. This paper will also detail transaction method usage and field definition guidelines and tradeoffs.

Synopsys Tools Used:
VCS with pre-compiled UVM libraries

Target Audience:
Intermediate


MC-07 Advanced Signoff and Design
Synchronization and Metastability
Steve Golson - Trilobyte Systems
The phenomenon of metastability is inherent in clocked digital logic. Many techniques have been presented for minimizing metastability, both for crossing clock domains and for handling asynchronous inputs. Some of these ""best practices"" have unexpected weaknesses and must be used carefully, particularly at smaller process nodes. This paper will explore these shortcomings and suggest alternative schemes that are more robust. A PrimeTime methodology for verifying multi-clock designs will be presented.

Synopsys Tools Used:
PrimeTime

Target Audience:
Intermediate

PrimeTime Advanced Waveform Propagation
Carol Scemanenco - Synopsys, Inc.
In this tutorial we will look into the future of FinFET technology nodes and the impact these new structures have on static timing analysis. These three-dimensional structures offer performance, area, and power benefits but also introduce more complex parasitic characteristics than planar structures. This increased parasitic complexity results in waveform distortions that can have a significant impact on timing.

We will describe how PrimeTime's waveform propagation technology accounts for the sub-20nm affects that are strengthening phenomena such as Miller Effect and long tail waveform distortions. We will also describe how we have made the PrimeTime sub-20nm flow more robust by identifying and handling bad library data.

Synopsys Tools Used:
PrimeTime SI

Target Audience:
Designers responsible for STA at deep submicron technology nodes


MC-08 PCI Express IP
Yes! You Can Use PCI Express for Mobile and Enterprise SoCs
Scott Knowlton, Richard Solomon - Synopsys, Inc.
This presentation explores the evolution of PCI Express from its prior server and desktop focus to spanning the entire spectrum from ultra-mobile devices to high-performance computing. First, it will describe how the new M-PCIe ECN, along with existing features such as L1 sub-states and Readiness Notifications, enable PCI Express to save power and extend battery operation in mobile products appearing in the 2014-2015 timeframe. The presentation will then discuss the 16GT/s signaling rate announced as part of the upcoming PCI Express 4.0 Base Specification and how it serves the high-performance computing environment. The presentation will also cover key issues facing designers incorporating these new PCI Express features in both mobile and enterprise spaces, including bandwidth and clocking considerations, PHY interfaces, power management impacts, and link-related tradeoffs.

Synopsys Tools Used:
DesignWare PCI Express IP

Target Audience:
Designers, design managers, and system/chip architects who are implementing M-PCIe (PCIe over M-PHY) or PCI Express 4.0/3.0/2.1/1.1 into SoC designs


MC-09 HAPS
Putting IP and Subsystem Prototyping on the Fast Track
Mick Posner, Antonio Costa - Synopsys, Inc.
The number of IPs used in complex SoCs is increasing very rapidly and hence IP subsystems are becoming an important part of the SoC development and validation design cycle. In this tutorial we will introduce the new HAPS Developer eXpress, HAPS-DX, solution for complex IP and subsystem prototyping and the new DesignWare IP Prototyping kits accelerating IP and subsystem bring-up streamlining IP to SoC integration. The DWC IP prototyping kits accelerate SoC integration by providing a comprehensive reference design with embedded processor, configured HAPS-DX system, FPGA-based prototyping design environment for DesignWare Controller + PHY IP and software reference drivers with example applications working "out-of-the-box." In this tutorial we will introduce the HAPS-DX and will showcase how the DWC IP Prototyping kits can be used for:
  • Embedded software development as a stand-alone platform
  • DWC IP Subsystem Reference design with Controller and PHY IPs
  • Prototype a large SoC with multiple DWC IP Prototyping kits
  • DWC Controller IP and PHY IP configuration exploration

Synopsys Tools Used:
HAPS-DX, HAPS ProtoWare-DX, DesignWare IP

Target Audience:
Engineers and engineering managers responsible for ASIC/SoC verification, software development and prototyping who are seeking the latest methods and tools to accelerate SoC FPGA-based prototyping; system architects who are seeking a complete pre-validated subsystem reference designs


Monday, March 24, 2014
4:00 PM - 8:00 PM
Designer Community Expo
Wrap up your first day at SNUG by relaxing with colleagues and Synopsys technical and executive staff at the Designer Community Expo. Grab a beverage and sample the food. Visit with Synopsys and over 60 of our partners who will demonstrate integrated solutions to help you address your design challenges. Enter drawings for chances to win great prizes throughout the evening.


Tuesday, March 25, 2014
9:00 AM - 10:00 AM
Technology Keynote
Innovation - The Thrill and Thorns of Navigating Through Uncharted Territories
Dr. Sebastian Thrun, Founder and CEO of Udacity, VP and Research Fellow at Google, and Professor of Computer Science at Stanford University
Technical innovation is increasingly changing our daily lives but how do these innovations come to life? Where do the ideas spring from, and what is the path to success when you're navigating through completely uncharted territories? Gain an insider's perspective as Dr. Thrun outlines the thrilling and sometimes thorny path he and his team are navigating through as they work to bring us self-driving cars, Google Glass heads-up displays and an entirely new university from scratch.


Tuesday, March 25, 2014
10:30 AM - 12:00 PM
TA-01 Physical Implementation - Data Flow Analysis
Accelerating Floorplan Creation Using DFA in ICC/DE
Charles Tang, Krishna Kumar Gundavarapu - Cisco Systems
As Cisco designs are being implemented in process nodes 28nm or below, design complexity and size have increased by manifolds. Number of plan groups and connectivity in the top level has increased the complexity of top-level floorplanning. Also, within each plan group, optimal floorplan creation becomes a very challenging and time-consuming task. Physical Designers are provided limited information about the data flow. When RTL designer resource is limited or unavailable, floorplanning tasks involve iterative cycles of placement, timing/congestion analysis, and refinements. We have addressed this problem by using the Data Flow Analysis (DFA) feature in IC Compiler/DC Explorer. In this paper, we'll focus on techniques that we used to analyze data flow at the top-level and within plan groups and how we apply that knowledge to refine floorplans and drive synthesis to produce the best QoR in physical implementation. Also, we'll share how we use DC Explorer and ICC-DP's Data Flow Analysis to produce a high quality floorplan, the time it took for us to perform these tasks, and implementation results.

Synopsys Tools Used:
IC Compiler, DC Explorer

Target Audience:
Intermediate

Using Data Flow Analysis for Floorplanning
Rajiv Dave - Synopsys, Inc.
This tutorial presents the 3 parts of IC Compiler's Data Flow Analysis (DFA) capabilities for floorplanning: Logical Connectivity Analysis, Advanced Flyline Analysis, and Macro Array Editing. With this foundation, we present practical ways to use DFA, including creating initial floorplans for use with DC Explorer using the IC Compiler Design Planning link, and optimizing macro placement for best QoR in IC Compiler. DFA was first released in G-2012.06-SP2 with a two-window GUI. In I-2013.12, DFA is integrated into the IC Compiler layout window. This tutorial presents DFA capabilities using the integrated user interface of I-2013.12.

Synopsys Tools Used:
IC Compiler, DC Explorer

Target Audience:
Physical and RTL Designers


TA-02 In-Design Physical Implementation/Verification
Managing Metal Fill and Its Impact on Your Design
Dan Marolda - Synopsys, Inc.
Metal fill has become a major concern for designers because of its significant and growing impact on design timing. This session will present design flow solutions for metal fill that are timing-aware and allow you to minimize the impact of fill on timing. The session will also show the latest auto-incremental fill capabilities with IC Compiler In-Design that are essential to maintain fast turnaround times with today's complex manufacturing needs. We will also look at the latest metal fill requirements for advanced nodes and how these will impact your design flow.

Synopsys Tools Used:
IC Validator, IC Compiler

Target Audience:
Design and CAD engineers and managers responsible for physical verification and Implementation

In-Design Flows for Faster Tapeouts
Anand Patil - Aquantia
Reaching design closure can be incredibly challenging for engineers designing on advanced process nodes. Design size, timing requirements, and litho-driven double patterning rules are driving the need to automate traditional design flows. In this session we will discuss flow improvements, such as the ability to merge GDS library and routed design data and capabilities to automatically find and repair DRC/DPT errors post-route. We will then present results showing the benefits of these flows in a designer's environment

Synopsys Tools Used:
IC Validator, IC Compiler

Target Audience:
Design and CAD engineers and managers responsible for physical verification and implementation


TA-03 Test
Low DPPM and Low Cost Testing for All Process Nodes and FinFETs
Adam Cron - Synopsys, Inc.
Process variations at small geometries give rise to physical defects that require additional tests for achieving low defective parts per million (DPPM). At the same time, higher test compression is needed to reduce the test data volume and test execution time. This tutorial will highlight how leading edge capabilities in Synopsys' TetraMAX ATPG, such as slack-based transition delay testing and cell-aware testing, are being used to enable low DPPM testing and diagnostics for both advanced and established process nodes and FinFETs. We will also discuss DFTMAX Ultra, a new add-on to DFTMAX, that enables higher scan compression and faster test frequencies using fewer test pins. Once parts have been fabricated, TetraMAX can be used to perform physical diagnostics for fast and accurate fault isolation, and Yield Explorer can be used to perform design-centric yield analysis to accelerate yield ramp.

Synopsys Tools Used:
DFTMAX, TetraMAX

Target Audience:
Designers and managers interested in test, quality, and manufacturing


TA-04 Circuit Simulation
Circuit Simulator Release Update: The Solution for Tomorrow's Challenge
Tom Hsieh - Synopsys, Inc.
Do you ever:
  • Feel uncertain about the simulation challenges that lie ahead when moving to a new process node?
  • Wonder how Synopsys’ HSPICE, CustomSim, and FineSim solutions help address your simulation challenges?
  • Wish you had insight into the latest advances in SPICE and FastSPICE solutions?

This tutorial provides proven solutions and features that enable you to maximize the efficiency of your simulations. For HSPICE, performance improvements in BSIM-CMG model, signal integrity for S-element, and local/global accuracy setting will be shared in this session. For FastSPICE, we will share various performance improvements, new features support (Static CCK, MOSRA, RA, etc.), as well as some powerful debugging capabilities.

Synopsys Tools Used:
HSPICE, CustomSim, FineSim

Target Audience:
Analog/mixed-signal design engineers, CAD managers & engineering managers


TA-05 UVM Methodology
A Register Layer Gallimaufry
Tim Corcoran - Willamette HDL Inc.
One of the most exciting features of the UVM library is the Register Layer. By extending a set of base classes, the user can abstract the often tedious read/write interface to registers and memories ease tasks like reset testing and reduce the stress of constantly evolving memory maps. It's not all poetry and music however. For the unwary, there can be many discordant notes. This paper presents a collection of topics to help you avoid mistakes and make optimum use of some lesser known but highly useful Register Layer APIs.

Synopsys Tools Used:
VCS

Target Audience:
Intermediate

How UVM-1.1d Makes the Case for Unit Testing
Neil Johnson, Jean-Marc Tremblay - XtremeEDA Corporation
UVM makes the case for unit testing in hardware development through an open-source project called UVM-UTest. In UVM-UTest, unit test suites were written for several core components of the UVM. The intent was to rigorously verify the functionality of each component in isolation, an approach uncommon in hardware verification. The result of this unit testing was 10 obvious defects found over the course of only 6 weeks. If there are defects in the UVM, what defects are hidden in your code?

This paper introduces unit testing and describes how it differs from and plays complement to existing verification practices. It then documents the development of UVM-UTest, how the project was conceived, styles for unit tests written, and its success measured in terms of defects found in the UVM. The paper concludes with lessons learned related to unit testing and recommendations for applying unit testing beyond the UVM.

Synopsys Tools Used:
UVM

Target Audience:
Intermediate


TA-06 UVM Methodology
Methodology for Command Line Control of Configurations and Sequences Using Synopsys Discovery I2C VIP
Mohammad Rizwan - Broadcom Corporation; Gaurav Chugh, Amir Nilipour – Synopsys, Inc.
For today's complex SoCs, availability of full-featured, highly configurable and easy-to-integrate VIPs is essential to achieve time critical tasks of verifying enhancements and modifications to such designs. In the course of this paper, we will describe the experience with this Synopsys Discovery I2C VIP, its seamless integration into the SoC UVM infrastructure, and how the VIP features allowed us to find critical RTL weakness in a very short duration. We will also cover the methodology deployed to run the same test with different configuration and sequences, using command line options to achieve complete functional coverage. All aspects of advanced verification enabled by this VIP will be covered in detail including I2C protocol checks, error injection capability, score boarding, functional coverage and verification plans for transaction and scenario based coverage, reusable and configurable sequences, call-backs support, and protocol analyzer.

Synopsys Tools Used:
VCS, Discovery I2C VIP, Verdi, Protocol Analyzer

Target Audience:
Advanced

Layering Protocol Verification: A Pragmatic Approach Using UVM
Mehul Kumar, Rahul Chauhan, Gurpreet Kaire - Broadcom Corporation; Ravindra Ganti, Subhranil Deb - Synopsys, Inc.
Layering protocols are modeled using layering structures that mirror the protocol layers. There are significant challenges in modeling verification components for layering protocols such as (1) reuse, (2) scalability, (3) controllability, and (4) observability. Furthermore, there may be requirements for complex test scenarios where a great deal of interaction is required between test sequence execution and response. It is important that the test sequences be provided with fine-grain control of the desired verification components to execute the required complex test patterns for protocol verification at various layers. In this paper we present a pragmatic approach using Universal Verification Methodology that we developed for layering protocol verification to address the challenges mentioned above. This framework provides (1) a rich set of controls for layering drivers and sequencers to allow interactive complex test pattern generation and verification, (2) the ability to inject errors at any given layer without having to modify the underlying sequences, (3) the ability to run any given layer test sequence from a top-level virtual sequencer, and (4) the ability to perform peer-to-peer and complete protocol stack verification.

Synopsys Tools Used:
VCS, Verdi

Target Audience:
Intermediate


TA-07 Signoff- FinFET & Process Variation Panel
The "Real World" Weighs in on FinFET and Process Variation Impact
Brian Cline - ARM; Glen McDonnell - Broadcom; Tom Quan - TSMC; Susan Wu – Xilinx; Jacob Avidan, Bari Biswas - Synopsys, Inc.
Over the past several years, the semiconductor industry has been preparing for the arrival of FinFET technology, which has promised to deliver higher performing, lower power devices at densities that allow unprecedented functionality to be designed into a single IC. The challenges have been well documented and innovative solutions have been proposed by foundries, EDA vendors, and designers, but where do we stand today? Have the technology challenges been addressed, are the design and analysis tools meeting expectations, and has the potential of FinFET truly been harnessed? In this panel discussion, hear industry experts on the forefront of innovation evaluate the reality of the FinFET promise. Panelists will discuss their hands-on experiences in the areas of process technology, parasitic modeling, variation modeling, timing signoff analysis, and IP and design development. Highlights will include real design experience with increased process variation and a solution to remedy these effects.

Synopsys Tools Used:
PrimeTime SI, StarRC

Target Audience:
SoC, IP, and CAD engineers and managers interested in hearing about real world experiences with FinFET and DSM signoff technology


TA-09 USB 3.1 IP
Integrating USB 3.1 in Your Next SoC Design
Morten Christiansen - Synopsys, Inc.
The presentation explores the evolutionary and revolutionary changes between USB 3.0 and USB 3.1 and how they affect host controllers, hubs, and PHY IP. The presentation will also describe the challenges of designing a USB 3.1 consumer SoC, based on lessons learned from real USB 3.0 implementations. Furthermore, the session discusses how applications such as mass storage and communication can benefit from the high throughput of USB 3.1. The presentation will conclude with examples of multi-purpose SoC implementations that incorporate USB 3.1 as well as a range of connectivity protocol interfaces like USB 3.0, SSIC, LLI, UFS, M-PCIe, and PCI Express.

Synopsys Tools Used:
DesignWare USB controller and PHY

Target Audience:
Design engineers and system architects who are interested in integrating USB 3.1 IP into their SoCs


TA-10 Systems
Using Platform Architect MCO to Optimize Your Micro-Server SoC Architecture for Performance and Power
Gururaj Rao - Synopsys, Inc.
In this session, we will address HW-SW partitioning and cache coherent interconnect optimization for a micro-server SoC and how early architecture simulation with Synopsys Platform Architect MCO enables design teams to achieve the right system performance, power, and cost. A practical example will be used to:
  • Create an application performance model of typical server workload, by specifying the timing characteristics (processing cycles, activation interval) and memory access requirements of application-specific communication and compute tasks
  • Create a combined power/performance model of the micro-server SoC architecture that contains multicore processing elements, caches, cache-coherent interconnect, and memories, including annotation for power consumption
  • Map the application model to SoC architecture model in order to measure, analyze, and explore end-to-end application latency and throughput for different server workloads.

Synopsys Tools Used:
Platform Architect MCO, DesignWare uMCTL2 TLM model

Target Audience:
SoC architects, specifically in the micro-server area"

Performance Analysis for the Synopsys DesignWare Universal DDR Memory Controller Using Synopsys Platform Architect MCO
Asheesh Khare - Synopsys, Inc.
The Synopsys DesignWare Universal DDR Memory Controller (uMCTL2) provides sophisticated features like bank interleaving and transaction reordering to optimize memory throughput for many parallel transaction streams. Specific latency and bandwidth requirements from different SoC subsystems including main CPU, video, and audio can be managed via advanced Quality of Service capabilities. A sub-optimal configuration can significantly reduce the overall memory efficiency as well as impact the performance of individual sub-systems. In this session you will learn how to find the best configuration for your application by using Synopsys' Platform Architect MCO, a performance analysis environment with a comprehensive SystemC transaction-level model library for workload modeling, traffic generation, and modeling of interconnect and uMCTL2 memory subsystems.

Synopsys Tools Used:
Platform Architect MCO, DesignWare uMCTL2 TLM model

Target Audience:
SoC architects and HW engineers responsible for system performance, SoC integration, and memory optimization


Tuesday, March 25, 2014
12:00 PM - 1:30 PM
TA-11 Design Compiler Lunch and Learn
Shrinking Design Area and Schedules for Established and Emerging Nodes
Come hear your peers discuss how they are utilizing new Synopsys synthesis technologies to meet the challenges of today's complex designs at both established and advanced nodes. Panelists will discuss how they are using Design Compiler Graphical to achieve smaller area, reduced congestion and faster convergence. Additionally, you will hear how the latest capabilities in DC Explorer's RTL analysis can help you develop high-quality RTL more quickly. Don't miss out on this very special event.

Target audience:
RTL design, CAD and backend engineers and managers


TA-12 Verification Lunch and Learn
Addressing the Challenges of SoC Verification
Learn how leading companies ensure successful SoC verification by using Synopsys solutions to address the verification challenges of the most advanced SoC designs. You will hear a panel of users share their experiences using Synopsys solutions to address SoC verification challenges with advanced testbench deployment and debugging methodologies, VIP, and coverage closure. Additionally, they will share the benefits of having access to state-of-the-art solutions for every task in functional verification flows, from architecting a design and verification environment, to performing high-capacity, high performance static and formal applications, to achieving RTL signoff with advanced coverage closure solutions.


Tuesday, March 25, 2014
1:30 PM - 3:30 PM
TB-01 High-Performance Core Implementation
Performance-Focused Implementation of a Dual-Core ARM Cortex-A57 Processor at the 20nm and 16nm Process Technology Nodes
Saran Kumar Seethapathi, Joshua Garrett, Fang Wang - Broadcom Corporation
In this session, Broadcom will share experiences with the physical implementation of a dual-core ARM® Cortex®-A57 processor at the 20nm and 16nm process technology nodes. We will start with an overview of the Cortex-A57 processor and its performance/power profile before sharing implementation challenges specific to the core. The session will focus on differentiating technologies in Design Compiler, IC Compiler, and PrimeTime that were effective in achieving the power and performance targets for this processor core. Technologies highlighted include the SPG flow, layer-aware optimization, multisource CTS with concurrent clock and data optimization, DPT friendly library layout and routing compliance, and physical-aware ECO. The session will also cover results achieved by exercising these technologies through the Galaxy Implementation Flow.

Synopsys Tools Used:
Design Compiler, IC Compiler, PrimeTime

Speed, Power, and Complexity Exploitation and Exploration for Mobile GPU
Alex Chang - MediaTek
With increasing demands from gaming and ultra-high resolution display in tablets and high-end smart phones, GPUs have become a dominant IP posing many challenges for implementation, including speed, power and complexity. Speed-wise, GPUs continue to follow CPUs but with an even lesser power budget. Complexity-wise, GPUs are a complex SoC requiring an efficient and accurate hierarchical design flow. To address these challenges, GPU implementation has entered a new domain that requires continual flow exploitation and innovative exploration. In this session, we will present MediaTek's high-performance GPU flow based on Synopsys tools and outline areas for improvement.

Synopsys Tools Used:
Design Compiler, IC Compiler, PrimeTime SI

Target Audience:
Logic and physical design engineers, design and CAD team managers and project leaders

AMD Shares Highlights from Their Successful Tapeout of an ARM Cortex-A57 MPCore Processor
Samit Chakraborty, Satyavathi Akella, Sam Huynh, Manoj Rehani, Phillip Young - AMD
AMD recently taped out a server SoC based on an ARM® 64-bit ARMv8 architecture. This session includes an overview of the complex SoC with special emphasis on the implementation of the dual-core ARM Cortex®-A57 MPCore™ processor at its heart. The core was fabricated in a GF 28nm process using ARM standard cells and memories. Achieving the frequency target, while meeting an aggressive schedule was enabled through a carefully crafted, predictable methodology that leveraged multiple capabilities from Synopsys' Design Compiler, IC Compiler, and PrimeTime tools. The session will highlight key capabilities used and best practices observed for this on-time tapeout success.

Synopsys Tools Used:
Design Compiler, IC Compiler, PrimeTime SI

Target Audience:
Logic and physical design engineers, design and CAD team managers and project leaders


TB-02 Low-Power Design
Full-Chip Low-Power Static Verification using Verdi Signoff-LP
Debajani Majhi, Leah Clark - Broadcom Corporation
This paper presents the low-power full-chip static verification evaluation effort done for VSI-LP within Broadcom and compares the results with a competitive industry tool. With every technology node shrink, the power architecture becomes more complex, and advanced low-power methods such as static and dynamic voltage and frequency scaling, power gating, and state retention make the verification task even more complex. The low-power verification challenge is also amplified by the fact that the majority of the low-power function is introduced into the gate-netlist during synthesis and physical implementation, which is late in the design process. Most of the tools available on the market for low-power static verification are not able to handle the current design sizes and complexities without compromising the run time and memory usage. In this paper we will discuss how VSI-LP addresses those issues and others. We will also present a case study of a large chip and how VSI-LP performed on it.

Synopsys Tools Used:
Verdi Signoff-LP

Target Audience:
Intermediate

Verdi Signoff-LP: Next-Generation Low-Power Static Verification
Narayana Koduri - Synopsys, Inc.
Verdi Signoff-LP is a next-generation low-power static checker that verifies low-power design intent, architecture, and structures. It provides much higher performance and capacity (>3x-5x) over previous generations of static checkers. In this tutorial you will learn how to use Verdi Signoff-LP, including design and UPF read-in, and perform various low-power checks. It will include details of debugging different design problems with the help of the graphical user interface, various reports, and schematics. You will gain an understanding of the ""best practice"" flow to triage problems, including filtering reports and managing design waivers.

Synopsys Tools Used:
Verdi Signoff-LP

Target Audience:
Verification engineers and managers"


TB-03 Test
Deploying DFTMAX Ultra: Usability is Paramount
Renee Logan, Vladimir Kovalev, Anil Moolchandani - SanDisk
SanDisk has been implementing compression technology for many years. Our past experience is with DFTMAX and we are in the process of transitioning to DFTMAX Ultra. In this paper we present our experience in this transition. With DFTMAX Ultra we got additional flexibilities that allowed us to address design issues that impact the overall scan compression architecture. We present such optimizations. This paper is an example of an industrial environment and decisions that impact scan compression. Results of the implementation are presented with data.

Synopsys Tools Used:
DFTMAX Ultra, TetraMAX, VCS

Target Audience:
Introductory

Implementing Hierarchical DFT Architecture for Ultra Large Designs Using DFTMAX Core Wrapping and Test Scheduling
Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Raghavedra Rao - LSI Corporation; Vikas Pissay - Synopsys, Inc.
In this paper, a DFT scan architecture and methodology for very large designs is presented. We cover the entire scan design implementation and generation of efficient and optimized test patterns. For very large designs, if a hierarchical ATPG approach becomes the only way to address the capacity and runtime challenges during pattern generation, then it would require a lot of DFT planning during the scan architecture in terms of which blocks/cores need to be wrapped and tested in parallel at the SoC level. In addition to this, the limited number of scan channels at the SoC level requires a comprehensive compression solution to minimize the overall test cost. This paper discusses detailed aspects of how the core wrapping with test scheduling feature of DFTMAX addresses these challenges.

Synopsys Tools Used:
DFTMAX, TetraMAX

Target Audience:
Advanced

Achieving Extreme Compression for GPU System on Chip Designs
Jon Colburn - NVIDIA
High-volume testing of complex System on Chip designs at reasonable test cost makes test data and test time compression an absolute requirement. This paper describes a multilevel compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure for test data compression, plus adds a high-speed data access technique for additional test time reduction. In addition to maximizing the compression ratios it is important to limit the impact on area and timing of the device being tested so test signals are minimized while improving the modularity of the inserted design-for-test structures. We present the flow for assembling the various components and give results that show the combination of these techniques provides a reduction of over 500x in test data volume and a reduction in test time of over 2000x.

Synopsys Tools Used:
DFT Compiler, TetraMAX

Target Audience:
Intermediate


TB-04 Circuit Simulation
Single Executable FineSim Technology for Analog and Full-Chip Simulations, Analyzing Performance, Statistical Variation and Design Violations' Checks
Raed H Sabbah - Micron Technology, Inc.
FineSim is the leading unified and single executable simulator that combines SPICE and FastSPICE simulation methodology in a single environment for memory design at Micron. FineSim introduces both SPICE and FastSPICE simulation capabilities within one engine that is capable of running in either mode for the same stimulus input and option sets. This methodology has helped us reduce the overhead of maintaining and dealing with two different tools and two separate simulation environments leading to ease of use and better assimilation of Analog and Custom Digital design. Besides the unification of simulation environment, this paper highlights FineSim’s high-performance statistical simulations and some of the substantial and important Static and Dynamic Circuit Check capabilities we use to detect and tackle design problems that help to automate circuit debugging and diagnostic checks in our designs. Finally, we underline FineSim’s superior simulation speed in comparison with other simulators.

Synopsys Tools Used:
FineSim, HSIM

Target Audience:
Intermediate

A Framework for Automating Circuit Simulations
Sandeep Dechu - Synopsys, Inc.
This tutorial covers the challenges CAD, flow automation, and design engineers are facing in developing, maintaining, and using automated flows. We will review how those issues are addressed using Lynx and how we developed a GUI based transistor level simulation regression system. We will showcase how this regression system makes CAD engineers' and designer' lives easier with powerful simulation and resource handling, a job monitoring system, reporting, and customizability features. We'll also discuss how we customized Lynx to create validation and correlation systems.

Synopsys Tools Used:
Lynx, FineSim, Custom WaveView

Target Audience:
Design engineers, CAD and flow automation engineers


TB-05 Simulation Acceleration with ZeBu
Verification of SoC Designs with ZeBu HW Emulator
Gwyneth Sauceda - Synopsys, Inc.
With so much to do during a product development cycle, project teams must use all available solutions to deliver a quality product on time. To complement simulation, hardware emulation use is growing, especially for SoC designs. In this tutorial, we will review best practices for SoC verification and validation utilizing hardware emulation. Key debug features, easy to use transaction-based acceleration and advanced unified compile flow of the ZeBu emulation system will be covered. An SoC design with an embedded core and graphic engine executing on the ZeBu emulator will be available for demos.

Synopsys Tools Used:
ZeBu

Target Audience:
Verification and emulation engineers and managers

Deploying ZeBu Transaction-Based Verification on Imagination GPUs
Colin McKellar - Imagination Technologies; Fabian Delguste - Synopsys, Inc.
In this session, we describe how Zebu-Server3 has been used to emulate Imagination Rogue-6XT IPs. The original ICE-based solution is explained, as well as its pros and cons. Then, a new approach based on Zebu transactors is fully walked through with focus on its architecture, reuse of legacy testbench and enablement for driver live development. Finally, we provide some results on measured runtime performance, reuse between platforms and deployment to other customers.

Synopsys Tools Used:
ZeBu

Target Audience:
Verification and emulation engineers and managers


TB-06 Advanced Verification Debug with Verdi
Going Beyond the Waveform: Advanced Debug Techniques in Verdi
Bindesh Patel, Archie Feng, Alex Wakefield - Synopsys, Inc.
In order to keep up with increasing design complexity, there has been an explosion of new verification methodologies, techniques, and tools. Software has shifted left in the verification cycle leading to a need for genuine HW/SW co-debug. UVM has officially achieved mainstream status, which means understanding of class-based testbenches, constrained-random verification, and transaction-level modeling is no longer optional.

While methodologies, automation, and other verification solutions help with overall verification closure, along the way, a human engineer is still responsible for figuring out what is going wrong. With the amount of data and complexity involved with today's environments, it is increasingly impractical to attempt to debug with only the traditional signal-level waveforms. In short, new ways to do things require new ways to debug them. In this tutorial, we will teach you how to:
  • Debug advanced SV test benches interactively
  • Analyze auto-captured UVM transactions & messages
  • Debug embedded software and hardware together
  • Visualize and debug low-power designs and UPF-based environments
  • Customize Verdi with VIA scripts and applications

  • Synopsys Tools Used:
    VCS, Verdi

    Target Audience:
    Design and verification engineers and managers


TB-07 Library Modeling for STA: POCV Variation and Library Cell Validation
Advanced Node Random Device Variability Modeling and Margining in Characterization and STA
Tamer Ragheb, Steven Chan, Ning Jin, Richard Trihy - GLOBALFOUNDRIES
Due to the continuous reduction in feature size from one technology node to another, many high order effects, such as device and gate variability and parasitics, have become more prominent. Consequently, it is necessary to include a design margining methodology to cover their effects on performance and power. In this paper, we discuss the evolution of design margining methods starting from On-Chip Variation (OCV) up to Liberty Variation Format (LVF) and the trade-off between accuracy and cost in each of them to help designers to choose the right margining methodology for a given technology node, design, and margin headroom available. We discuss each methodology from both angles of library characterization/preparation and static time setup as well as the accuracy of the results as compared to Monte Carlo SPICE simulations as our golden reference.

Synopsys Tools Used:
SiliconSmart, PrimeTime, StarRC

Target Audience:
Advanced

Automating PrimeTime vs. HSPICE Validations
Eduardo Flores, Krishnakumar Ramakrishnan - Synopsys, Inc.
This tutorial introduces a mechanism for automating the correlation of PrimeTime paths in HSPICE using the Lynx Design System. Traditional validation techniques consist of PrimeTime and library users running some timing paths with HSPICE. This correlation exercise is possible through the PrimeTime command write_spice_deck. There are articles on SolvNet explaining how to launch such validations and scripts available that help users select paths which are good for correlation purposes, launch HSPICE, and collect results. This process requires manual intervention. We will present an automated solution which enables users to easily customize the tests, follow their execution, and view results in both high-level and detailed modes. Analysis of multiple corners on multiple designs can be fully automated with a refined control over how many parallel jobs can be launched simultaneously.

Synopsys Tools Used:
PrimeTime SI, HSPICE, Lynx Design System

Target Audience:
PrimeTime users, library characterization teams

Parametric OCV (POCV): A Viable and Recommended Alternative to AOCV for Variation Aware Static Timing Analysis
Khaled Heloue - AMD
At 32nm nodes and below, local process variation can lead to significant delay variation and chip yield loss. Accounting for local process variability during path delay calculation in static timing analysis has changed over the years from on-chip variation (OCV), to pseudo statistical OCV (AOCV), to parametric OCV (POCV). POCV is a more accurate model for delay variations for general mixed cell type paths and does not suffer from graph-based vs. path-based depth pessimism that is inherent to AOCV. We strongly recommend POCV for 32nm designs and below, and will present an internal correlation study on POCV vs. AOCV on various 28/20nm blocks that shows slacks to be highly correlated with just a few outliers.

Synopsys Tools Used:
PrimeTime ADV

Target Audience:
Managers and designers responsible for timing signoff at advanced nodes


TB-08 Custom and Advanced Node Parasitic Extraction
NVIDIA's Advanced Node Custom Design Experience with StarRC
Sudhir Agarwal - NVIDIA
With the growing complexity at advanced technology nodes, there is an ever-increasing need to use innovative solutions to get faster turnaround time for custom design flows with minimal accuracy loss. Interconnect parasitic extraction and simulation performance are at the forefront of this challenge, demanding efficient tool interfaces and interactive debugging capabilities. In this presentation, Sudhir Agarwal, Principal Engineer at NVIDIA, will share NVIDIA's custom design experience as they move to 20nm and below technologies, including how they effectively exploit StarRC capabilities to boost designer productivity and achieve trusted signoff accuracy for all transistor level flows.

Synopsys Tools Used:
StarRC, HSPICE

Target Audience:
IP designers and custom circuit designers

GLOBALFOUNDRIES PDK Development and Tool Qualification
Venkat Ramasubramanian - GLOBALFOUNDRIES
As designers move to advanced nodes to incorporate FinFETs in their high-performance, low-power designs, they are recognizing the need for a deeper understanding of the complexities of foundry processes and qualification and how this relates to their design flow and IP development. In this session, GLOBALFOUNDRIES will discuss the development and verification of their PDKs for advanced nodes, focusing on qualification of signoff tools such as StarRC and Rapid3D.

Synopsys Tools Used:
StarRC, Rapid3D, Raphael

Target Audience:
Digital and IP designers focusing on physical verification, extraction, and/or static timing analysis/simulation

Solving Extraction Challenges at 10nm
Bari Biswas - Synopsys, Inc.
As FinFET devices are entering production at 14 and 16nm, foundries are already preparing for the next level of die shrink at 10nm and delving into the challenges of this next process node. Achieving finer conductor line width resolution at denser geometries requires extending double-patterning to "multi-patterning," bringing with it increased sources of variation in cell-level parasitics and static timing analysis. In addition, FinFET devices are evolving to more exotic silicon profiles, requiring even more complex fabrication and modeling. In this session, Bari Biswas, Sr. Director of R&D for Synopsys' parasitic extraction team, offers insights into new demands placed on lithography and device modeling and the innovative solutions being explored in collaboration with technology partners.

Synopsys Tools Used:
StarRC

Target Audience:
Physical design CAD engineers, TCAD and process development engineers, and IP designers


TB-09 High Speed PHY IP
Addressing the Challenges of Multi-Protocol High Speed PHY Design
Rita Horner, Paul Hua - Synopsys, Inc.
As the cost of IC design rapidly increases due to the reduction in feature sizes, companies are no longer designing products that target just a single application. Instead, ICs are architected to utilize multi-protocol physical layer (PHY) IP which can be connected to multiple different protocol-specific physical coded sub-layers and controllers. This augments the functionality of the device, enabling programmability and reducing the overall design cost. The presentation describes the design challenges addressed by a 12.5 Gbps PHY that supports a range of protocols and electrical specifications, all requiring different reference clock inputs, specific jitter requirements, and wide range of line rates.

Synopsys Tools Used:
DesignWare Enterprise 12G PHY

Target Audience:
Design engineers, design managers, and system architects who are interested in implementing 12G SerDes IP into their SoCs


TB-10 Systems
Application of Virtual Prototypes, Current and Future
Robert Kaye - ARM
The last few years have seen a rapid growth of virtual prototypes, abstract simulation models used by SoC software developers. There are many factors driving this growth, including maturing technology, increased business pressure, and changing software development paradigms.

In this presentation we will explore the underlying technology that enables virtual prototype development and deployment at all stages of the SoC design process with Synopsys Virtualizer and VDK tools and models. This will be illustrated through a range of different real-world use cases and user experiences.

Finally, we will look at the future of virtual prototypes: what are the challenges and how are these being addressed? What trends are driving new requirements and functionality, what new use cases could these developments unlock, and how will the technology evolve in the near- to mid-term?

Synopsys Tools Used:
Virtualizer, VDK Links to VCS, ZeBu, HAPS

Target Audience:
Intermediate

Using Synopsys VDKs for Developing UEFI and Linux Drivers for Synopsys DesignWare IP Interfaces and ARMv8 Processors
Mojin Kottarathil - Synopsys, Inc.
In this tutorial we will introduce tools and methods for early bring-up and debug of DesignWare Interface IP drivers in context of ARMv8 processor-based software stacks. On the software side, we will focus on the Unified Extensible Firmware Interface (UEFI) standards for Linux for micro-servers. Special attention will also be put on the so-called kernel based virtualization, relevant for server software stacks, and the impact on developing device drivers. We will present how Synopsys VDKs can jumpstart bring-up, integration, and debug of drivers. Tutorial attendees will leave with a clear understanding of the technical benefits VDKs provide for the software engineer.

Synopsys Tools Used:
Virtualizer, Virtualizer Development Kits (VDKs), DesignWare TLM Library

Target Audience:
Software developers and architects responsible for BIOS and OS bring-up


Tuesday, March 25, 2014
3:45 PM - 5:15 PM
TC-01 Advanced Physical Implementation
R&D Panel: Get the Inside Track in Physical Implementation
Michael Jackson, Mark Bales, Pei-Hsin Ho, Aiqun Cao, Thomas Andersen - Synopsys, Inc.
Interact with key Synopsys physical implementation technologists as they discuss the various design challenges, both today and in the future, and how Synopsys' latest technologies can turn these into opportunities for success.

Target Audience:
Physical designers, technologists, and management interested in learning about advanced tools and methodologies"


TC-04 Circuit Simulation
Transistor Level Static Circuit Analysis, an ERC Solution for Deep Sub-Micron Low-Power Custom Digital, Memory and Analog IP Designs
Jason Hwan - Synopsys, Inc.
This tutorial is for circuit designers looking for methodical ways to detect design errors in low-power circuit designs. This tutorial describes how to use CircuitCheck to apply transistor level static analysis for efficient design error detection without running traditional circuit simulations. Key topics that will be discussed include essential ERC (electrical rule check) assertion, detecting power induced leakage path in memory designs, and detecting over-bias problems in critical area of analog circuits. In addition, designers will learn how to manage these design errors using a graphical debugging environment with CustomExplorer-Ultra.

Synopsys Tools Used:
CircuitCheck, CustomExplorer-Ultra

Target Audience:
CAD engineers, analog designers, mixed-signal verification engineers, and design managers


TC-05 Verification Coverage Closure
Functional Coverage Database Using UCAPI
Robert Goldman - NVIDIA
Functional coverage closure is a key part of any modern verification effort. Synopsys provides the basic tools to collect coverage and generate reports in HTML or ASCII. Those tools are good at handling a single testbench and single versions of those testbenches. To complement the basic features, additional infrastructure can enhance support for merging and tracking across multiple versions of the same testbench or across different test benches with overlapping groups. This paper examines a working UCAPI & SQL solution developed to enable user-specified reports and statistics on multiple months of collected data. The solution was deployed on a design with more than three million functional coverage bins, enabling faster analysis and coverage closure.

Synopsys Tools Used:
URG, UCAPI, SystemVerilog

Target Audience:
Introductory

Full-Chip Application of an Automated Code Coverage Closure Methodology
Syed Suhaib, Keegan Brown, Prosenjit Chatterjee - NVIDIA; Ashvin Dsouza, Abhishek Muchandikar - Synopsys, Inc.
Code coverage closure is an essential metric for ensuring a design has been thoroughly tested, but coverage closure often comes late in the design cycle when schedule pressure is high, and includes intensive work to manually identify and waive coverage goals which are unreachable. Recent formal techniques can be used to automatically identify these unreachable goals, but comprehensive analysis of large-scale designs can be prohibitive. We present an Automated Code Coverage Framework (ACCF) methodology for attaining line and conditional coverage exclusions automatically at a full-chip level, using a combination of RTL simulation and formal analysis to generate exclusions for unreachable coverage points for units within the chip. Simulation coverage data is used to accelerate formal analysis by eliminating already-reached cases, and exclusions are automatically included in downstream coverage reporting. A case study is performed showing unreachable case detection rates across units of a large-scale design and demonstrating significant acceleration of coverage closure.

Synopsys Tools Used:
Magellan, VCS

Target Audience:
Intermediate


TC-06 Power Estimation and Coverage
Early Vector Based Dynamic Power Estimation
Eshwar Parigi - Broadcom Corporation; Ravi Chopra - Synopsys
As the clock speed increases, the dynamic power is becoming more and more important. Current flows for dynamic power measurement require a full-chip gate-level simulation and also a full-chip timing closed database. This means full-chip dynamic power is available just a few days before tapeout when it's difficult to make any changes for design at that time. With this flow we can very accurately measure power at every step of the design at block level.

Synopsys Tools Used:
Verdi, PrimeTime PX

Target Audience:
Intermediate

Auto Line and Conditional Functional Coverage for DV Code
Gaurav Vaidya - Cisco Systems
Line and conditional coverage doesn't exist off-the-shelf for DV code as it does for RTL code. Such coverage can be very useful to quickly find major coverage holes in both stimulus and scoreboard classes before one delves deeper into pruning and tweaking the test suite. There are some ways of adding line and conditional coverage in DV code, but they require adding a lot of overhead code. This paper describes a method that is both scalable and avoids code duplication. Here, a variable tracks the line numbers that are hit, and the coverage class has bins for each line number of interest. This method is developed on to automate it and make it easier to deploy.

Synopsys Tools Used:
URG

Target Audience:
Intermediate


TC-07 Timing Closure & Characterization for Macros
Differential Clock and Topology Handling in NanoTime
Norb Heindl - Synopsys, Inc.
Full-swing differential circuitry is a common technique employed in SerDes and similar designs and requires more complex static timing analysis verification. Since the H-2013.06 release, NanoTime Ultra supports static timing analysis of these types of full-swing differential circuits, expanding the coverage of transistor level verification. This tutorial introduces the support, provides examples, and describes ongoing enhancements, enabling the user to quickly access these new features.

Synopsys Tools Used:
NanoTime

Target Audience:
Designers of digital and mixed-signal macros; signoff and/or characterization engineers

20nm Timing Characterization and Signoff of Advanced FPGA Custom Circuits Using NanoTime
Gurdarshan Kalra, Fu-Hing Ho - Xilinx, Inc.; Sahil Bargal - Synopsys, Inc.
This paper describes the use of the NanoTime transistor-level static timing analysis tool for analysis of typical FPGA designs at Xilinx. The complexity of timing analysis on programmable logic circuits is discussed, and design modeling issues that affect analysis accuracy, runtime, and pessimism are examined. Solutions deployed at Xilinx to address those issues and features added to NanoTime to support improved analysis accuracy of FPGA custom circuits are covered. Finally, design team productivity enhancements and the signoff checklist are described.

Synopsys Tools Used:
NanoTime, PrimeTime

Target Audience:
Intermediate


TC-08 Signoff Physical Verification
High-Performance Physical Verification of Advanced Designs at NVIDIA
Sudhir Agarwal - NVIDIA
Verification turnaround time (TAT) has always been one of the top concerns for chip designers. It becomes an even bigger issue when dealing with large designs on some of the industry's most advanced silicon processes. In this session we will review multi-CPU scalability and other techniques implemented by NVIDIA to improve TAT for DRC and LVS using IC Validator.

Synopsys Tools Used:
IC Validator

Target Audience:
Design and CAD engineers and managers responsible for physical verification

LVS Ease of Use and Debugging
Dwight Ly - Altera Corporation
Designs are getting more complex, and with an increased amount of circuits in the design, debugging LVS issues is not an easy task. In this session you will learn about ICV LVS ease of use features, text short debugging using ICV VUE to locate multiple text shorts in a single run, and other LVS debugging features that increase productivity for designers.

Synopsys Tools Used:
IC Validator

Target Audience:
Design and CAD engineers and managers responsible for physical verification


TC-09 Compound Floating Point Units
Designing Compound Floating Point Units with an Efficient Pre-Validated IP Based Approach
Alexandre Tenca - Synopsys, Inc.
This presentation discusses how the features, IP, and methodology of the new DesignWare Foundation Cores product enable designers to quickly create customized compound floating-point hardware solutions. The session covers the usage of C models for floating-point operators, new IP that supports compound operators, and an innovative approach that provides more freedom for designers to implement specialized floating-point algorithms. Learn how the DesignWare Foundation Cores allow designers to achieve better productivity and reduce verification effort, while realizing the area and power savings of a customized compound floating-point unit. The solution allows designers to perform floating-point operations on a less restrictive representation, for which normalization and rounding is not mandatory. The presentation also includes design cases to illustrate the benefits, numerical behavior, and tradeoffs of this alternative.

Synopsys Tools Used:
DesignWare Foundation Cores

Target Audience:
Design engineers, design managers and system architects with interest in numerical algorithms and floating-point


TC-10 Coverity
Introduction to Coverity
Dr. Andreas Kuehlmann - Coverity; John Chilton - Synopsys, Inc.
Hardware verification tools and methodologies have been refined over multiple decades and now offer a reliable process to get HW designs right within a few iterations. In contrast, software verification is still in its infancy as evident by the large number of quality and security problems we encounter on a daily basis. Many of them, like the recently uncovered iOS and MacOS security vulnerability, have severe business implications ranging from brand damage to product recalls and lawsuits. Coverity has pioneered a new generation of software testing technologies that is based on deep semantical analysis of the source code. This analysis is the basis to automatically uncover quality defects and security vulnerabilities as well as guiding test development on the critical code. In this session, we will introduce Coverity's technology foundations, its core products, and their typical application in practical development lifecycles. Finally, we will examine specific types of defects that can be found using Coverity's products.


Tuesday, March 25, 2014
4:45 PM - 6:30 PM
SNUG Pub
SNUG 2014 is hosting Silicon Valley's largest pub with a local brewfest! Featuring beer from local breweries, SNUG Pub is sticking to the basics - great beer, food, games and an opportunity to mingle with fellow attendees, Synopsys R&D, and Synopsys Executives. Join us after Tuesday's sessions.


Wednesday, March 26, 2014
9:00 AM - 10:30 AM
WA-01 Advanced Physical Implemenation
Emerging Node Design with IC Compiler
Neil Moore - Synopsys, Inc.
This tutorial is for IC designers planning to use IC Compiler for emerging node designs with emphasis on support for manufacturing compliance (placement constraints, double patterning, DPT aware routing, extraction, etc.). We will highlight the design challenges posed by FinFET design and how IC Compiler can resolve these issues with its convergent flows for timing, leakage and area. Finally, we will demonstrate the significant productivity benefits of utilizing the In-Design capabilities of IC Compiler/IC Validator, coupled with the close signoff correlation and convergence throughout the Galaxy platform.

Synopsys Tools Used:
IC Compiler, IC Validator

Target Audiencev:
IC designers targeting 16nm designs with IC Compiler and IC Validator


WA-02 Test
Accelerate SoC Testing Using Synopsys' DesignWare STAR Hierarchical System and DesignWare STAR Memory System
Arnaud Wenzel - ST
As designs continue to increase in size and the use of IP increases, it is difficult to complete testing of large SoCs within the desired schedule and cost using traditional full-chip methodologies. The variety of IP blocks with different test interfaces makes it extremely challenging and time-consuming to integrate and test all of the IP at the SoC level. In addition, the increasing embedded memory IP on designs and new defects at small geometries require an efficient memory test, repair, and diagnostics solution to achieve high SoC yield and lower silicon cost. In this session, we will present SoC test leveraging IP and logic block-level test using STAR Hierarchical System, which accelerates SoC testing by enabling faster design closure and improved test QoR with hierarchical testing of all IP, including analog/mixed-signal IP, digital logic blocks, memory, and interface IP.

Synopsys Tools Used:
DesignWare STAR Hierarchical System, DesignWare STAR Memory System, DFTMAX, TetraMAX

Target Audience:
Designers, DFT engineers, test engineers, product engineers and foundry engineers who are, or will be, designing or characterizing SoCs


WA-03 Formal Verification and Functional Qualification
Formal Verification of GPU Level of Detail Datapath Block
Kesava R. Talupuru - Qualcomm
In computer graphics a technique called Level of Detail (LOD) is used to improve real-time rendering performance. LOD allows GPU to select different level of details of textures, also called MIPMAP, based on texture to object mapping ratio (LOD). These LOD calculations in GPU are complex floating point operations involving finding reciprocals, derivative computations, derivative adjustment, elliptical transformations, etc. Since the floating point input space for this LOD block is huge, it is not practical to exhaustively verify in simulation. In order to get exhaustive proofs, we leveraged a formal tool called Hector High-Level C to RTL Equivalency Checking from Synopsys. In this paper, we will present various advanced formal techniques we have to use to get exhaustive proofs for this block: assume-guarantee reasoning, case splitting, multiple solve strategies, cutpoints, etc.

Synopsys Tools Used:
Hector Equivalency Checking tool

Target Audience:
Intermediate

Integration of Certitude Coverage Collection
Keegan Brown - NVIDIA
Certitude provides a mechanism to measure and improve the ability of a testbench to detect possible faults in a design under test. Conventional Certitude usage expects engineers to run analysis at one or more discrete points in the design cycle, however limited runs create difficulty in keeping fault coverage metrics up-to-date as designs and testbenches evolve. This paper describes a system for automating Certitude analysis of designs to provide regular metrics and fault coverage results with no direct user action. The automation allows for tracking Certitude coverage results over time in order to measure testbench and checker progress. Additional benefits included providing timely notice of unexpected fault coverage decreases and making reports available to the user on-demand to minimize overhead. Techniques are discussed for minimizing the runtime by selection of faults to be analyzed, as well as proposed tool enhancements that could be used to further reduce incremental time required for regular automated runs.

Synopsys Tools Used:
Certitude

Target Audience:
Intermediate


WA-04 Verification Closure
Verification Closure Flow
Michael Horn - Synopsys, Inc.
This tutorial will walk through the standard verification closure flow and talk about what is needed at each step. The flow includes planning, metrics gathering, verification execution, analysis and ultimately shipping a product. From this tutorial, you will discover that Synopsys has unique capabilities which can be applied to your verification project right now to deliver a higher quality product. As the flow is discussed, technologies will be highlighted such as Verification Planner, Discovery VIP, RALGen, Certitude, VCS, Verdi Signoff and more. Come see how Synopsys enables a complete verification closure solution to create first pass success with your designs.

Synopsys Tools Used:
VCS, Certitude, ZeBu, VSI-LP, VIP

Target Audience:
Verification engineers and managers


WA-05 FPGA Synthesis
Effortless Xilinx Vivado IP Flows
David Lopez, Jon Nagareda - Synopsys, Inc.
Today's FPGA designs use an increasing amount of IP in a variety of forms, be it from the FPGA vendor or a third-party IP provider. In this tutorial you will learn best practices for integrating IP that has been generated using the Xilinx Vivado IP Catalog. Topics covered include how best to incorporate encrypted and unencrypted IP, RTL and netlist-level IP, Memory Interface Generator (MIG), and PCI Express IP into your Synplify synthesis design. Use of the emerging IEEE-1735 standard for IP encryption and rights management being adopted by FPGA and EDA vendors alike will also be discussed.

Synopsys Tools Used:
Synplify Premier, Vivado, VCS

Target Audience:
Xilinx FPGA designers integrating Vivado IP into their designs


WA-06 High Performance Computing for Silicon Design
High-Performance Computing for Silicon Design
Silicon design technical complexity increases every year due to new features and the shrinking of process technology. Intensifying the trend, business drivers like shorter product development time and the pressure for reduced headcount and lower cost raise the need for a substantial increase in pre-silicon verification, a high degree of design automation, and global multi-site design teams. These factors related to both technological and business issues astronomically increase demand for computing and storage, which in turn drives the need for product development to be engineered in an optimal computing environment.

Target Audience:
IT personnel and CAD managers who manage compute resources for EDA applications


Wednesday, March 26, 2014
10:45 AM - 12:15 PM
WB-01 Low-Power Implementation
Low-Power Design Implementation
Gloria Chen, Jeffrey Lee - Synopsys, Inc.
This tutorial will review low- power technologies available in the Design Compiler family of synthesis products, IC Compiler place and route, and PrimeTime SI. Along with an overview of core optimization technology, attendees will also learn about key 2013.12 multi-voltage (MV) features such as support for a new “Golden UPF” methodology. For advanced IC Compiler users, enhanced support for controlling the routing topology and buffering (physical feedthroughs) for MV design implementation will also be covered in this session.

Synopsys Tools Used:
DC Ultra, DC Graphical, Power Compiler, IC Compiler, PrimeTime SI 

Target Audience:
Implementation engineers and managers designing for low-power


WB-02 Test
Automated Volume Diagnostics for Accelerated Yield Learning in Advanced Nodes
John Kim, John Kirkland - Synopsys, Inc.
As the industry progresses into advanced nodes, design process interactions are contributing to a larger portion of the initial yield losses than ever before. While traditional methods are effective for yield learning of general process issues, and early process test chips can help eliminate some number of gross design process systematics, it is becoming more difficult to comprehensively characterize all possible design/layout variations and standard cell usage only using such vehicles. ATPG scan diagnostics offer an efficient and effective method to identify systematics and enable the analyst to isolate important yield issues that may otherwise be difficult. In this session, we describe several automated methods to systematically analyze such data. We also incorporate other supporting data to drive rapid failure analysis and yield ramps, as well as new analysis methods to characterize design attribute and process fail rates, in order to drive process fixes more effectively.

Synopsys Tools Used:
Yield Explorer, TetraMAX, PrimeTime, Camelot

Target Audience:
DFT, product, yield, and failure analysis engineers and managers


WB-04 Verification Environment Qualification
Certitude Functional Qualification: Applications in the C/C++ Domain
Marty Rowe - Synopsys, Inc.
The amount of effort spent creating, debugging and maintaining a typical verification environment often outstrips the effort spent on the design itself. Measuring the effectiveness of verification is critical to ensuring high-quality, bug-free designs. As the use of languages like C/C++ to represent portions of the design continues to increase, the ability to obtain such measurements via traditional techniques becomes difficult. Certitude's mutation-based approach assesses verification effectiveness by measuring the environment's ability to activate, propagate and detect potential bugs. This technique, in use with RTL designs for years, can now be applied to components described in C/C++, with similar benefits.

This tutorial will cover the following:
  • A primer on the use and operation of Certitude
  • An overview of how these techniques can be applied to components described in C/C++
  • A survey of specific applications and benefits in the C/C++ domain

Synopsys Tools Used:
VCS, VCS-MX, Certitude

Target Audience:
Verification engineers and managers


WB-05 VCS Update
VCS 2014.03 Release Highlights
Rohit Narkar, Latha Venkatachari - Synopsys, Inc.
In this tutorial you will learn about the new features and enhancements in the latest VCS version (VCS 2014.03). Some of the features that will be covered in this tutorial are: performance improvements for RTL and constraint-heavy designs, enhancements for mixed-signal (AMS) low-power simulation, low-power coverage, X-propagation, and new SystemVerilog language features. We will also discuss various features in VCS that can help improve Verification Engineer productivity.

Synopsys Tools Used:
VCS, VCS-MX, XPROP, VCS NLP

Target Audience:
Verification engineers and managers


WB-06 FPGA Synthesis
Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goals
Paul Owens, Shankey Srinivasan - Synopsys, Inc.
Quality of Results is a primary objective for many FPGA designers. In this tutorial you will learn about the latest Synplify Premier techniques and methodologies for maximizing the timing performance of your design, while keeping design iterations to a minimum. Topics covered include: utilities and techniques that allow you to assess and optimize your constraints, how to get improved timing correlation, coding styles, project and optimization settings that improve QoR, and how to achieve faster overall timing closure.

Synopsys Tools Used:
Synplify Premier, Vivado

Target Audience:
FPGA Designers under tight schedules, needing to maximize timing performance


WB-07 Compute Farm Resource Selection and Management
CPU Choice, Server Architecture, and BIOS Settings for EDA Tool Performance
Kamran Casim - HP; Manish Neema, Glenn Newell - Synopsys, Inc.
SandyBridge, Ivybridge, Haswell? Single socket, dual, quad? Hyper-Threading on or off? Turbo? Default BIOS vs. energy saving vs. max performance and the effect on EDA tool performance. Traditional servers are two or four sockets, but vendors are bringing faster single socket servers to market in new dense form factors, but with fewer cores. We will demystify the options and present relative performance results using Synopsys EDA Tools, including Design Compiler, PrimeTime, VCS, HSPICE, Liberty NCX, Proteus, TCAD, CATS, and ZeBu Compile.

Target Audience:
IT personnel and CAD managers who manage compute resources for EDA applications

Fair Sharing of Compute Resources in a Complex Enterprise Environment
Omar Hassaine - Univa; Joe Fu - Synopsys, Inc.
While most Distributed Resource Managers (DRMs) provide functionality to evenly share access to compute resources based on policy set by administrators, the out-of-box functionality may not be adequate to handle very complex enterprise organizational structures and projects, or the delegation of control over subsets of the resources. In this presentation we will discuss a custom solution jointly developed by Synopsys and Univa that provides fine-grain sharing of over 40K cores across several organizational business units, several projects, and over 1,000 users, without impacting end user submission workflow. This presentation covers the base functionality provided by Grid Engine's Share Tree policy, Grid Engine extension points such as Job Submission Verifiers (JSVs), the custom extension to handle the complex requirements, and system monitoring and tuning.

Target Audience:
IT personnel and CAD managers who manage compute resources for EDA applications


Wednesday, March 26, 2014
12:15 PM - 1:45 PM
WA-07 Lynx Design System Lunch and Learn
Using Lynx Design System Automation to Accelerate Design Processes - SoC Flow, Custom Design Correlation and Regression Throughput
Steve Cline - Altera Corporation; Eduardo Flores, Lydia Lee, Terry O'Brien - Synopsys, Inc.
The complexities of advanced SoC design constantly challenge tape-out timelines. Lynx Design System can simplify and automate flows for many critical implementation and validation tasks, enabling engineers to focus on achieving performance and design goals. This Lunch and Learn will introduce you to how Altera is leveraging Lynx in their next generation design flow to lower risk and improve schedule predictability. Additionally, you will learn about innovative and sophisticated automation solutions for circuit validation, correlation, and IP regression that are demonstrably improving customer productivity.

Topics covered will include automating:
  • Launch, monitor, and analyze correlation of NanoTime vs. HSPICE characterization for large scale custom design suites
  • Mixed-signal IP validation and customer release environment

Target Audience:
Design engineers, CAD engineers, engineering managers, and program managers


Wednesday, March 26, 2014
1:45 PM - 3:15 PM
WC-01 High Level Synthesis
Using Synphony C Compiler to Speed Implementation of Image Processing IP
Craig Gleason - Synopsys, Inc.
Video and image processing hardware has become pervasive in smartphones, cameras, camcorders, autos, security equipment, and a host of other devices. As the algorithms often begin in C and C++, high-level synthesis (HLS) from these languages to high-quality RTL can boost design productivity by 5-10X. In this tutorial we will introduce Synopsys' Synphony C Compiler (SCC) HLS solution and show how you can use it with SCC's C++ image processing library to accelerate the delivery of high-performance image processing pipelines in a fraction of the time it takes using traditional methods.

Synopsys Tools Used:
Synphony C Compiler, Design Compiler

Target Audience:
RTL designers, architects and algorithm designers of image processing hardware


WC-02 Test
SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Arun Kumar - Synopsys, Inc.
SoC test becomes significantly more complex as designs become larger and the amount and variety of IP used increases. Today's SoC present a unique set of test challenges including higher test costs, higher power consumption during test, lower design productivity, and new defects at small geometries (FinFET). We will discuss new features and capabilities of the DesignWare STAR Memory System, Synopsys' memory test, repair and diagnostics solution, that address these challenges. In addition, we will describe the unique capabilities of the DesignWare STAR Hierarchical System, a hierarchical test solution for all IP/cores on your SoC including interface IP, analog/mixed signal IP, and digital logic blocks.

Synopsys Tools Used:
DesignWare STAR Memory System

Target Audience:
Designers, DFT engineers, test engineers, product engineers and foundry engineers who are, or will be, designing or characterizing SoCs. The tutorial will provide introductory and advanced content.


WC-04 Static Low-Power Verification
Increase Low-Power Verification Productivity
Ajay Thiriveedhi - Synopsys, Inc.
Low-power design has changed the way verification is being done. Complex power management techniques like retention, DVS, and DVFS add new complexities to logic simulation. With ever increasing pressure on the total time available for design verification, an efficient low-power verification methodology should involve a combination of conventional functional verification techniques like planning, assertions, and coverage, along with advanced simulation technologies that help engineers more easily find verification holes and design bugs. This tutorial will provide an overview of how various technologies available in the Synopsys verification tool suite can be leveraged to increase the thoroughness and productivity of low-power verification of your design. It will show how technologies like VCS NLP with power aware verification environment (PAVE) capabilities, together with XPROP and Verdi-PA can be combined to provide a powerful low-power verification and debug platform that helps users find low-power design bugs in a quick and efficient manner.

Synopsys Tools Used:
VCS, VCS NLP, XPROP, Verdi

Target Audience:
Verification engineers and managers


WC-06 FPGA Synthesis
Analyze and Report on Your FPGA Design with Ease Using Tcl
Maitrey Makim - Synopsys, Inc.
With today's extremely short product schedules, FPGA designers are under pressure to deliver designs that have differing objectives depending upon the particular project. Synopsys FPGA tools have been enhanced for greater Tcl compatibility with ASIC synthesis and FPGA vendor place and route tools. New commands allow compilation databases to be quickly created and analyzed for faster design debug. In this tutorial, you will learn and see live examples of how to use Tcl to query and diagnose the design database. You will learn how to mine the design database to create custom reports. The tutorial will also show how Tcl can be used to customize and automate the overall design flow, including how to automate the process of constraints and attribute setting and how to script incremental design fix-up flows.

Synopsys Tools Used:
Synplify Pro/Premier

Target Audience:
FPGA Designers who need to improve design implementation productivity


WC-07 Storage and OS Impact on EDA Tools
Accelerating VCS Verification for Faster Time-to-Market (TTM) Through Scalable Parallel Infrastructure
Bikash-Roy Choudhury - NetApp
Continually increasing design complexity is creating ongoing challenges for design verification, as well as for the underlying infrastructure. This paper discusses the use of NFSv4.1/pNFS to accelerate VCS runtime and help optimize time to results. The proposed architecture based on scale-out storage infrastructure with pNFS allows seamless growth with business demands. Further enhancements can be achieved for Synopsys VCS performance, with up to 19% improvement for build times and 26% reduction time for runs using NetApp clustered ONTAP 8.2 and NFSv4.1/pNFS, over traditional storage and NFSv3. This translates to up to a 1.4x job completion time improvement.

Target Audience:
IT personnel, CAD managers and tool users interested in new storage technologies for performance improvement

OS Roadmap for EDA Design
Richard Paw - Synopsys, Inc.
Changing the version of the operating system for your EDA compute environment introduces risk into the design process. Design cycles are often much longer than the version support provided by operating system vendors. In addition, supporting multiple projects in the datacenter means that updating your design environment is a complicated juggling act of systems, tool versions, designs, and operating systems. A solid understanding of the operating system support roadmap for your tools is critical to your compute environment plans. This presentation will discuss Synopsys' operating system roadmap, as well as the EDA Consortium OS Roadmap for new design starts, which covers tool support for the flagship products for the major EDA vendors. You will also be able to provide feedback on the OS roadmap directly to Synopsys.

Target Audience:
IT personnel and CAD managers who manage compute resources for EDA applications


WC-08 Verdi Interoperable Apps (VIA) Developers Forum
WC-08 Verdi Interoperable Apps (VIA) Developers Forum
(1:45 pm – 6:00 pm)
Don't miss the inaugural VIA Developers Forum focused on accelerating SoC debug and verification. At this forum, SoC design teams can learn about further maximizing the effectiveness of Synopsys’ Verdi solution, the industry's de facto debug platform, with custom automation programs that leverage the underlying design analysis and debug infrastructure. In addition to industry-leading technical presentations and an insightful keynote, VIA Developers Forum provides networking and social opportunities to meet other developers and executives from leading SoC teams. Join your fellow engineers and leave with practical information you can use on your current projects, and inspiration for how to take debug innovation and verification productivity to the next level. An informal networking event including food and beverage will follow.

Presenters:
Users from NVIDIA, Faraday, IBM, RealIntent, and others will share their experiences at the VIA Forum


Publish Only
Handling Design Variability During Timing Signoff
Alexander Tetelbaum - Abelite Design Automation
This paper provides useful tips and recommendations on how to handle multiple global and local variations in process (transistor, wire, and via parameters), voltages (including multiple V-domains that may be partially correlated), temperatures, and ageing degradation during timing signoff. It discusses minimization of the number of signoff corners needed for signoff while avoiding a risk of silicon failure due to insufficient number of corners. The presentation will share our experience and knowledge that designers can use in their practice. The paper teaches how to better use PT-SI or PT-VX.

Synopsys Tools Used:
PrimeTime

Target Audience:
Advanced

Ease of Transition and Evaluation of ICC for Established Nodes
Kai Chiou - Integrated Device Technology; Krishna Devineni - Synopys
This paper presents the evaluation of IC Compiler for transitioning all IDT design tapeouts from Talus Vortex to IC Compiler. The blocks that were used for this evaluation were a technology mixture of 55nm to 180nm.

Initially, IDT had serious doubts about the ability of IC Compiler to perform well for established node designs since we had relied on Talus Vortex and trusted it for all of our design needs. In this paper, we provide details on the out of the box LCRM (Lynx Compatible Reference Methodology) flow along with CCDO (Concurrent Clock and Data Optimization) that was used on two designs. We share results from these runs that provide the productivity and confidence that IDT requires during the transition phase.

Synopsys Tools Used:
IC Compiler

Target Audience:
Introductory

Faster Timing Closure with PrimeTime Physically-Aware ECO on 20nm Technology Multi-Scenario Designs
Shelly Xia - Altera Corporation; Harry Yu - Synopsys, Inc.
The 20nm advanced technology provides increasing challenges to the engineering change order (ECO) process due to requirements in handling Vt-min spacing, double-patterning rules and more congested designs during the placement of ECO cells, and the need to handle the increasing number of scenarios. The PrimeTime physically-aware ECO technology provides the capability for design teams to efficiently deal with timing signoff ECOs across multiple scenarios with minimal disturbance to cell movement and routing to achieve better timing closure. In our study, we are able to show improvement in setup, hold, max transition, max cap, and power saving with fewer ECO iterations for faster timing closure.

Synopsys Tools Used:
IC Compiler, PrimeTime

Target Audience:
Advanced