SNUG Silicon Valley Abstracts  

Monday, March 25, 2013
9:00 AM - 10:30 AM
Keynote Address 1
Massive Innovation and Collaboration into the "GigaScale" Age!
Aart de Geus, Chairman and co-CEO, - Synopsys, Inc.
The semiconductor industry is on the bridge to a new world of complexity empowered by smaller dimensions, new transistor types, enormous IP reuse, and a focus on the great potential of electronic systems. In other words, the GigaScale Age is upon us!

In addition, our customers are facing uncertain markets where merely making a better version of their last product is not sufficient. To survive and thrive in new and unknown markets, designers and their ecosystem partners are accelerating both their innovation and their collaboration with key partners. They expect the same from their EDA, IP and services partners.

In his presentation, Aart will give an overview of the enormous amount of recent innovation and collaboration happening at Synopsys as we enable "Moore's Law plus, plus" for yet another decade!


Monday, March 25, 2013
11:00 AM - 12:30 PM
MA01 - IC Compiler 2013
IC Compiler 2013.03 Release Highlights
Synopsys
IC Compiler's latest release delivers significant improvements in faster design closure, high-performance/low power design and advanced process node support.  The 2013.03 release includes minimum physical impact ECO implementation, useful skew for clock and data optimization, new technologies for reduced power, and expanded double patterning support for a color-ready place and route solution. This session will present an overview of the release highlights, many of which will be explored in greater detail in technical sessions throughout the SNUG program.

Synopsys Tools Used:
IC Compiler

Target Audience:
This is an informative session that will be applicable to all IC Compiler customers


MA02 - Challenges and Strategies for Advanced Designs
High Performance SoCs: Effective Strategies for achieving Optimal Performance, Power & Faster Design Closure
Santhosh Pillai, Sarita Baswant, Ashwani Gupta, Prasanth Koduri, Vi Nguyen, Sowjanya Mukka - Samsung Semiconductors
Today's designs provide different challenges for various aspects of parameters to be achieved. In most cases, the recommended methodology scripts from vendors with customization by the designers are able to address the challenges for most of the designs. The challenge comes for designs with high-performance need and yet meets aggressive power/area targets. That makes it difficult to use all techniques used in high-performance designs. We need to have an optimal solution to close the design with the best blend of performance, power, and area.

In this paper, we will discuss and present many techniques of achieving best of performance, power, area and design closure including, but not limited to, power optimization, skew optimized vs. power optimized clock tree, layer-aware timing optimization, scenario selection/compaction, high-performance optimization etc. The objective is to share the best overall results using Synopsys IC Compiler based on several hierarchical tapeouts at Samsung Semiconductor.

Synopsys Tools Used:
IC Compiler

Target Audience:
Will benefit the design community involved in high performance designs - Intermediate

Routing at 20nm - It is Challenging but Achievable
Chad Hale - ARM
This paper describes some of the routing challenges at 20nm and the need for close collaboration between foundry, IP provider and EDA tools. Design rule complexity has increased significantly since the days of simple space and width rules. This paper will dive deep at a few of the new 20nm routing rules and how coding them incorrectly will significantly impact DRCs and run time of a design. It will look at evaluating DFM rules and determining which ones to include. This paper will also discuss how routing rules are implemented and verified. It will also cover why the VIA definitions have increased exponentially over previous nodes. While some of the rules are yet to be supported in ICC, several techniques were used to address these challenges. It concludes with best practices and results in terms of the violations seen in ICC and correlation with signoff verification across different test vehicles.

Synopsys Tools Used:
IC Compiler

Target Audience:
Engineers facing 20nm routing challenges - Advanced


MA03 - IC Compiler Custom Co-Design
IC Compiler Custom Co-Design
Synopsys
In this technology session you will learn how IC Compiler Custom Co-Design accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.

Synopsys’ Galaxy unified implementation solution enables design teams to easily move between digital and custom implementation flows while maintaining design data integrity. IC Compiler Custom Co-Design enables higher productivity through advanced features such as DRC/LVS-correct interactive auto-routing for shielded nets, differential pairs, matched auto-routing, automatic bus/river routing, twisted-pair routing, and automatic DRC correction technology.

Tools Used:
IC Compiler Custom Co-Design & Galaxy Custom Router

Target Audience:
IC Complier engineers & CAD engineers


MA04 - Verification with OVM/UVM Methodologies
Reset Testing Made Simple with UVM Phases
Ben Chen, Brian Hunter - Cavium, Rebecca Lipon - Synopsys
Reset testing is a crucial element of functional signoff for any chip. The architectural components of the entire verification environment need to be correctly synchronized to be made aware of the reset condition. Scoreboards, drivers and monitors need to be tidied up, and the complex stimulus generation needs to be killed gracefully.

Handling these complexity’s with a company-wide framework requires a well-coordinated effort by all team members and is often incompatible with externally developed IP.

Now with UVM’s phase jumping capabilities and its native ability to kill phase-related threads and sequences, we can deploy an industry-wide standard model for reset testing. This paper will explore UVM-compliant methodologies and best practices for idle, active, soft and multi-domain reset testing based on experience deploying UVM in the networking domain.

Synopsys Tools Used:
VCS

Target Audience:
UVM users interested in reset testing with integrated IPs - Intermediate

OVM/UVM Scoreboards - Fundamental Architectures
Cliff Cummings - Sunburst Design, Inc.
One of the most complex components in an OVM/UVM testbench is the scoreboard. Simple tutorials on the theory behind and the creation of the scoreboard are scarce.

This paper will describe two fundamental OVM/UVM scoreboard architectures. The first architecture is a standalone scoreboard component with two UVM analysis implementation ports, which poses unique challenges when declaring and using UVM ports and methods. The second architecture is a highly-reusable scoreboard with predictor class and comparator class and the fundamental theories that make this architecture relatively easy to use. The comparator also employs two uvm_tlm_analysis_fifos, to help simplify the implementation. This simple tutorial will assist engineers to become acquainted and proficient with scoreboard development. The techniques described in this paper can be used with either OVM or UVM verification environments

Synopsys Tools Used:
VCS

Target Audience:
All verification engineers - Intermediate


MA06
MA06-A "No Man's Land" - Constraining Async Clock Domain Crossings
Paul Zimmer - Zimmer Design Services
Technical Committee Award Winner!
Fifos using gray-coded pointers are a common technique for passing data between asynchronous clock domains. This technique has a hidden assumption that the skew between the bits is minimal relative to the clock periods involved. But this assumption can be violated by P&R tools, and common STA techniques will not flag the problem, since they treat asynchronous domain crossings as unconstrained. This paper discusses the problem and proposes some techniques for constraining these paths.

Synopsys Tools Used:
Design Compier, PrimeTime

Target Audience:
Users challenged with asynchronous clock domain crossings - Intermediate


MA06-B
MA06-B Efficient Timing Constraint Analysis and Debug using PrimeTime-GCA
Peter Lindberg - LSI Corp.
Technical Committee Award Honorable Mention!
Whether large SoCs or small IP blocks, correct timing constraints are critical for achieving a functional design with optimal implementation. PrimeTime’s check_timing and report_analysis_coverage commands have traditionally been the method for validating constraints however this approach lacks checks in many areas and provides limited debug capability. This paper presents how we used PT-GCA to significantly boost the quality of our constraints in a fraction of the normal time. It discusses how we used GCA to implement custom constraint checks and also discusses limitations of this tool. This paper is intended for advanced users of timing closure tools.

Synopsys Tools Used:
Galaxy Constraint Analyzer, PrimeTime, Design Compiler

Target Audience:
Anyone working on timing closure for a SoC or hardmac - Advanced


MA07 FPGA-Based Prototyping
My BFF FPGA-Based Prototyping Solution: Better, Faster, and Flexible
Synopsys
With growing design size and complexity and a need for high performance, deciding which FPGA-based prototyping solution to choose is critical in the product development process. Do you build a custom board OR decide to try to eliminate development risk by adopting a commercial system? In this tutorial Synopsys experts in FPGA-based prototyping showcase the next generation HAPS-70 system and the key automation features that make commercial prototyping solutions attractive.
In this tutorial, you will learn:
  • How the enhanced HapsTrak 3 I/O connector technology with HSTDM delivers up to 3x performance improvement in data throughput over traditional pin multiplexing
  • How to accelerate multi-FPGA partitioning by up to 10x as compared to manual methods
  • How the modular system architecture of the HAPS-70 systems scales from 12-144 million ASIC gates to accommodate a range of design sizes, from individual IP blocks and processor sub-systems to complete SoCs
Target Audience:
Engineers and Engineering Managers responsible for ASIC/SoC verification, emulation, and prototyping


MA08 AMS for FinFET and 3DIC
Planar MOSFET to FinFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3
Tom Mahatdejkul, Ling Chien, Sreenivas Aluru - ARM
ARM's early engagements with technology developers and foundries positions ARM IP to be ahead of the curve. This early access to industry-leading technology also provides for a steep learning curve with currently available Synopsys tools which include HSPICE for SPICE simulation, FineSIM for characterization and StarRC with Rapid3D for layout parasitic extraction. In this paper, experiences in development stages from layout, to parasitic extraction, to simulation will be discussed as well as some comparisons and benchmarking parametrics of tool performance of FinFET technology vs. planar technology will be presented.

Synopsys Tools Used:
HSPICE, StarRC, FineSim.

Target Audience:
Engineers running SPICE simulation and extraction, validation and resource planning - Introductory to Intermediate Level

A New SPICE Simulation Approach for 3D IC Integration
Susan Wu, Jianlin Wei - Xilinx; Horace Lam - Synopsys
New, emerging 3D IC technology offers powerful advantages, such as high speed interconnects, increased design capability, bandwidth, and power savings, which enable designers to go beyond “Moore’s law”. However, 3D IC design also poses new challenges for some EDA tools and design methodologies.

This paper presents new 3D IC simulation features that Xilinx developed with Synopsys and implemented in HSPICE/HSIM to support 3D IC analysis and simulations. By introducing module block syntax for each die, this approach enables multi-dice chip level simulations under the existing SPICE simulation environment. Besides providing the simulation capabilities for 3D IC designs, the major advantage of the new approach over the traditional one is its capability to retain each die’s netlist, technology models and parameters separately. Our approach provides a full 3D IC simulation solution, which works for any combination of technologies without limitation to the number of the chips integrated.

Synopsys Tools Used:
HSPICE, CustomSim, StarRC

Target Audience:
Users of HSPICE, CustomSim, StarRC - Intermediate


Monday, March 25, 2013
12:30 PM - 3:30 PM
MA10 Lunch and Learn
Designing IP for FinFET Technology: The Opportunities and Challenges
Jamil Kawa, R&D Director - Synopsys
Although planar CMOS technology continues to scale to 20-nanometer (nm) and beyond, FinFET technology offers superior attributes and demonstrates better results in the areas of performance, leakage and dynamic power, intra-die variability and retention voltage. Although FinFETs are emerging as the device technology of choice at these advanced nodes, they introduce new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. Join this lunch-and-learn to understand the benefits and challenges of transitioning from planar to FinFET technologies and how IP plays a significant role in this transition.

Synopsys Tools Used:
DesignWare IP Target Audience: System Validation Engineer, Software Engineers, Hardware Engineers


Monday, March 25, 2013
2:00 PM - 3:30 PM
MB01 ARM GPU Implementation at 20nm
Proving the 20nm Implementation Ecosystem Using an ARM Mali GPU with a Full Galaxy Tool Flow
Shawn Hung - ARM
ARM and Synopsys collaborated to implement an ARM Mali GPU-based SoC in 20nm technology with ARM physical IP as a silicon test vehicle to prove out a full DPT-compliant Synopsys Galaxy implementation flow. We'll begin the presentation by outlining the differences between implementing an ARM GPU compared to a traditional ARM CPU core. We will then cover the challenges introduced by complex process rules at 20nm, including double pattering, and how they were addressed. To help prepare designers for the challenges at 20nm and beyond, we'll also share the best practices learned through this collaboration.

Synopsys Products:
Full Galaxy Implementation flow for 20 and below

Target audience:
implementation engineers, especially those interested in 20nm and below, as well as those interested in GPU implementation.


MB02 Advanced CTS Methodologies
Holistic Clocking Methodology that Supports Low-Skew (<20ps) and High-Speed (>1.5GHz) Clocking with Low Power for 28nm Designs
Anand Iyer, Kedar Kulkarni, Tim Kasper, Abhishek Kumar - Advanced Micro Devices, Inc.; Denise Powell, Chirakala Chinavenkata - Synopsys
Clock consumes one third of the power in any chip. The higher the frequency, the worse the power. For high-speed systems with very low skew, clock grid is perhaps the most efficient way to propagate the clock. This paper talks about some of the best practices of implementing a high-speed clock structure that can reduce power at the same time. The paper is based on the learning that we gleaned from implementing such a scheme for a 28nm design. The clocking structure was implemented with some innovative features from Synopsys. The design was taped out in 2012.

Synopsys Tools Used:
IC Compiler

Target Audience:
ICC users - Intermediate

Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler
Can Sitik, Baris Taskin - Drexel University
Multi-voltage clocking with a tree-topology distribution network is a popular technique used for low-power design methodologies with sophisticated automation techniques existent in industrial tool flows. The existing clock mesh flow proposed by IC Compiler must be improved in order to implement multiple clock meshes on an SoC-type design with multiple voltage domains. Toward this goal, this paper proposes a new flow for IC Compiler in order to implement a single-clock multi-voltage domain clock mesh with isolated clock meshes and pre-mesh trees at each domain. The proposed flow is integrated into the traditional IC Compiler design flow without any modifica-tions; therefore it adds an automated flow for the multi-voltage domain clock mesh design capa-bility to IC Compiler, with a script available to IC Compiler users.

Synopsys Tools Used:
IC Compiler

Target Audience:
Implementation engineers - Intermediate


MB03 Design Compiler Update
Galaxy RTL: Design Compiler Family 2013.03 Update
Synopsys
This tutorial presents the latest advances and methodologies of the Design Compiler family of products, including DC Explorer, Design Compiler Graphical, Power Compiler and Formality. The session will describe technologies in the 2013.03 synthesis release that deliver better circuit quality, improved quality of results, and enhanced ease of use. Topics include new layer aware buffering technology to accurately model delays at smaller process nodes, enhanced support for Multi-Bit cell mapping and improvements to power optimization. You will also learn how DC Explorer enables connectivity analysis and floor planning at an early design stage. Formality 2013.03 will be discussed including enhancements that offer improved completion for challenging designs, new hierarchical verification capabilities and faster RTL to gate performance.

Synopsys Tools Used:
Design Compiler Family—DC Explorer, Design Compiler Graphical, Power Compiler, and Formality

Target Audience:
This is an informative session that will be applicable to all Design Compiler and Formality customers


MB04 Debugging with Verdi
Verdi Transaction Based Debugging for SoC Designs
Synopsys
Debugging the hardware of an SoC design is a challenging task by itself and it’s made even more difficult when the designer needs to correlate the software “events” with the hardware “transactions” in order to debug a problem. A simple command from the software program can turn into hundreds of transactions in hardware making it a nightmare to manage and browse. In addition, these transactions can be zero delay, overlap one another, and be interleaved, which are difficult to view using a traditional waveform viewer. In this tutorial, you’ll learn how to maximize your productivity by using Verdi's Transaction Based Debugging technology to correlate and visualize the software “events” with the corresponding hardware “transactions” and browse, trace, and debug transactions. You’ll learn how the tool’s vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.

Synopsys Tools Used:
Verdi3

Target Audience:
RTL Verification Engineers, Logic Design Engineers, SoC Engineers


MB05 Measuring and Improving Verification Quality
Functional Signoff: A Process for Measuring and Improving Verification Quality to Ensure Bug-Free Designs
Synopsys
Verification engineers continually struggle with questions related to verification effectiveness. Do my test scenarios exercise the functionality sufficiently? Is my checker and assertion infrastructure complete? Traditional coverage techniques only determine if you’ve executed all lines of code or whether you’ve exercised all important functionality that you have defined. This analysis may not be sufficient, and there is no objective measure of “completeness”. This session will explain how Certitude Functional Qualification augments traditional coverage to provide unique insight into the quality of simulation and formal verification environments. Certitude’s proprietary mutation-based process inserts “artificial bugs” or faults into the design and measures the ability of the verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality and identify specific holes and weaknesses that can allow RTL bugs to slip through the process.

Synopsys Tools Used:
Certitude Functional Qualification Solution

Target Audience:
Verification Engineers and Managers interested in a functional signoff capability


MB06 Optimizing Extraction Performance and Accuracy
Optimizing Extraction Performance: Samsung Success with StarRC Simultaneous Multi-Corner Extraction
Santhosh Pillai - Samsung
As process technologies continue to shrink, extraction tools are required not only to handle much larger designs but also to precisely model ever-increasing sources of manufacturing variability. This increase in variability has spawned a greater number of extraction corners as well as an increase in overall modeling complexity, resulting in a dramatic jump in extraction TAT. StarRC recently introduced its new Simultaneous Multi-Corner Extraction feature which mitigates the runtime impact of extracting additional process corners. This innovative solution provides a distinct advantage in reducing overall TAT without compromising StarRC’s highly accurate results. In this session, Samsung will share its experience using this cutting-edge solution to reduce runtime without sacrificing accuracy at 28nm.

Synopsys Tools Used:
StarRC

Target Audience:
Designers interested in improving parasitic extraction performance with multiple corners

Fast Extraction and Accuracy for Advanced 20nm and 14nm Designs
Synopsys
Advanced process nodes and transistor architectures, such as FInFETs, provide significant advantages with higher density, higher performance, and lower leakage and power consumption. But they also penalize extraction Turnaround Time (TAT) due to larger design sizes, increased number of corners and higher modeling complexity in both the sign-off and timing closure ECO flows. In this presentation, StarRC’s R&D team will describe how they deliver faster runtime performance using highly-optimized multi-core architectures and multi-corner extraction analysis while maintaining vital extraction accuracy. They will also discuss how they are examining future design methodologies and hardware trends to reduce the complexity of extraction in advanced design nodes.

Synopsys Tools Used:
StarRC

Target Audience:
Designers interested in learning about faster extraction techniques in StarRC and productivity opportunities for advanced node designs

StarRC Transistor-level Extraction: Optimizing Accuracy and Performance for Custom AMS Flows
Synopsys
Highly-accurate transistor-level extraction is critical not only for device and IP characterization, but also for verifying design robustness in areas like reliability, ESD failures, and timing analysis. In this tutorial, Synopsys StarRC Corporate Application Engineering experts will give an update on how StarRC has improved overall transistor-level accuracy to ensure design integrity. They will also guide users on best practices for performing extraction with StarRC to optimize performance and improve productivity and the user experience.

Synopsys Tools Used:
StarRC

Target Audience:
Designers interested in improving parasitic extraction performance and accuracy for transistor-level design flows


MB07 Bringup and Debug of FPGA based Prototypes
Pest Control, Hunt Down Bugs Like the Experts
Synopsys
This tutorial highlights how to effectively employ best practices and design automation tools to accelerate the bring-up and debug of IP and SoC subsystems with an FPGA-based prototype. Expert prototyping engineers will show examples using the latest generation of Synopsys FPGA-based prototypes through all phases of an implementation: initial power-up; subsystem bring-up; and full system initialization. The application of prototype troubleshooting and design debug techniques at each stage will be presented as a case study. This includes assessment of the specific debug need, best fit of particular debug techniques, and the end result of each session. Tutorial attendees will leave with a clear understanding of how and when to apply techniques to complex FPGA-based prototypes.

Target Audience:
Engineers and Engineering Managers responsible for ASIC/SoC verification, emulation, and prototyping who are seeking the latest methods and tools to accelerate FPGA-based prototype bring-up and RTL debug.


MB08
MB8-A Using IBIS-AMI Models in HSPICE
David Banas - Altera
In this paper we show how to incorporate high-speed serial transceiver models, which have been written to the new behavioral modeling standard, IBIS-AMI, into HSPICE decks written for signal integrity simulation. The advantage of doing so, compared to using SPICE models of the transceivers, is speed. Decks run with these behavioral alternatives tend to run 3, or even 4, orders of magnitude faster than those which use the transistor-level SPICE equivalents. However, there are some pitfalls to be wary of. We explain these pitfalls and how to code around them, in order to ensure first time success. Also, accuracy is always a concern when adopting a behavioral modeling approach. Real world examples are provided that demonstrate what sort of correlation can be expected between decks run with IBIS-AMI transceiver models, and those using transistor-level SPICE models.

Synopsys Tools Used:
HSPICE

Target Audience:
HSPICE users; those wishing to incorporate IBIS-AMI models into their HSPICE decks - Intermediate


MB08-B
MB8-B Top-Down Post Full-Chip Verification for SRAM Boundary Simulation with FinesimPro
Garry Tse - SPANSION Inc.; Danny Cheng, Synopsys
Traditional block-to-full chip design flow uses ideal sources to simulate the behavior of the blocks. Final functional verification is done on full chip level. It is very time-consuming to repeat the full chip simulation if designer needs to perform additional checks on particular blocks. This paper shows a top-down scheme to verify block operation. The proposed flow use FinesimPro and other utilities to mimic a block’s full chip context in a standalone simulation. The flow reduce the need of re running time consuming full chip level simulation as design iterations takes place. We demonstrated that the new flow is accurate by comparing the block level simulations with full simulations. This flow enables engineers to have quicker turnaround time for accurate block level verification.

Synopsys Tools Used:
FinesimPro

Target Audience:
Design, CAD, verification engineers and managers - Intermediate


Monday, March 25, 2013
3:45 PM - 5:15 PM
MC01 Place and Route Vision Session
Advances in Place-and-Route Technology
Synopsys
Even though IC designers around the world have made IC Compiler the clear leader for place-and-route, customer feedback tells us there is still more we could do to ease the burden of the Physical Design engineer. Perpetually increasing chip complexity, shrinking market-introduction windows and ever-increasing demands on performance make Physical Design one of the most challenging tasks for an IC design house. This session will present the Synopsys vision for what it is going to take to meet these challenges.


MC02
MC2-A Floorplanning and Layout Feasibility with Multi-Instance Partitions
Sanjay Balasubramanian, Priya Joshi, Pratik Lunavat - Intel Corp.
Floorplanning and layout feasibility of large designs with cell counts exceeding 1 million has significant challenges in terms of convergence schedule and design complexity. There is also a concerted effort to make the design – RTL and layout - modular to enable reuse and improve scalability. Physical partitioning of the floorplan enables each partition to converge in parallel. If these partitions are multi instance modules (MIM), the number of unique partitions that need to be converged is reduced enabling a scalable design, enhanced productivity, and reduced time to market.

In this paper, we focus on floorplanning and layout feasibility of a design dominated by multiply instantiated physical partitions. We present a flow that generates the initial floorplan for all the modular partitions. We showcase some solutions to the layout challenges encountered in dealing with MIM’s that are connected by abutment only. We share results that demonstrate the throughput and resource efficiency of such an approach.

Target Audience:
Designers challenged with integrating MIMs to partitions that are MIM and abutting - Intermediate


MC02-B
MC2-B Achieving Predictable Timing in ASIC Flow using Design Compiler Graphical/IC Compiler for High Performance Designs
Venkataraman Srinivasagam - Cisco Systems Inc.
Design Compiler Graphical's (DCG) solution has become the default synthesis engine for high-frequency and macro-dominated designs. As metal geometry gets smaller, the net delay has become predominant than the gate delay. Designers face difficulties on how the design has to be coded and structured for ease of timing closure in the back end for a macro-dominated and congested block. This paper illustrates the challenges faced in 1GHz switch ASIC in 28nm technology node where DCG QOR started deviating when the placement structure and routing topology differed between the synthesis tool and the placement tool. To validate the synthesized design, the netlist and placement seed was taken into the IC Compiler (ICC) tool for optimization. The final results from ICC were within 2-3% of what DCG reported. This new flow enabled us to correlate and converge on timing in an ASIC flow where the complete back-end implementation was done by the vendor.

Synopsys Tools Used:
Design Compiler Graphical, IC Compiler.

Target Audience:
Intermediate users of DCG and ICC-DP.


MC03
MC3-A Hardware Redundancy and Design Fault Tolerance and their Applicability to Chip Design
Kurt Baty - WSFDB Consulting
Some hardware redundancy in regular structures is commonly used in chip design, for example, spare rows in memory structures. Hardware redundancy techniques used for random logic are rarely, if ever, used in chip design. There are, however, methodologies for producing hardware redundancy in random digital logic. Normally, these methodologies are used to achieve fault tolerance during operation. It is possible, however, with the use of these techniques, to generate a chip design, which, because of its redundancy, has statistically much higher yields. This paper will outline these redundancy and fault tolerance techniques, present examples of their use, and show how they could improve yields on chips. This paper will outline these redundancy and fault tolerance techniques, present examples of their use, and show how they could improve yields on chips.

Synopsys Methodologies Used:
Verilog, synthesis, scan/test

Target Audience:
ASIC designers concerned with chip yields


MC03-B
MC3-B Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification
Don Mills - Microchip Technology; Stuart Sutherland - Sutherland HDL, Inc.
SystemVerilog is not just for Verification! When the SystemVerilog standard was first devised, one of the primary goals was to enable creating synthesizable models of complex hardware designs more accurately and with fewer lines of code. That goal was achieved and Synopsys has done a great job of implementing SystemVerilog in both Design Compiler and Synplify-Pro. This paper examines the synthesizable subset of SystemVerilog and presents the advantages of using these constructs over traditional Verilog. Readers will take away new RTL modeling skills that will enable modeling with fewer lines of code, while at the same time reducing potential design errors and achieving high synthesis quality of results.

Synopsys Tools Used:
Design Compiler, Synplify-Pro, VCS

Target Audience:
Engineers involved in RTL design and synthesis, targeting ASIC and FPGA implementations - Advanced


MC04
MC4-A VISA: A State-Based, Hierarchical, Architecture-Independent Random Test Generation Environment for High-Performance Multiprocessors
Neil McKenzie, Michael Sedmak, Adam Snay, Chris Weller - Advanced Micro Devices, Inc.
VISA (Verification tool for an Instruction Set Architecture) is an architecture-independent random test generation (RTG) environment based on the Ruby scripting language and C++. VISA contains an embedded instruction set simulator (ISS) to keep track of the current state of each thread. VISA input templates are hierarchical: they can recursively include other VISA templates, and template code can make decisions regarding instruction generation on-the-fly, based upon the simulator state. After test generation is complete, VISA can create assembly language files for the standard directed test flow, or optionally it can directly output binary files for execution in co-simulation using Synopsys VCS. We discuss the current status of VISA, templates under development and future directions.

Synopsys Tools Used:
VCS

Target Audience:
CPU verification engineers who are interested in random stimulus generation of assembly language testcases and anyone interested in learning Ruby - Introductory.


MC04-B
MC4-B Random Stability in SystemVerilog
Doug Smith - Doulos, Inc.
A common problem that arises with constrained random verification is reproducing random stimulus for verifying RTL bug fixes and locking down test stimulus for regressions. In SystemVerilog, this is referred to as random stability, which is both a function of thread locality and hierarchical seeding. This paper discusses random stability, especially the use of good random seeds and locking down random number generator (RNG) seeding for test reproducibility. In addition, the RNG seeding employed in the leading verification methodologies like VMM, OVM, and UVM will be examined, tested, and critiqued highlighting strengths and gotchas.

Synopsys Tools Used:
VCS.

Target Audience:
Users interested in reproducing test cases in an environment with a continually improving testbench - Intermediate.


MC05 UVM Best Practices
UVM Best Practices
Synopsys
Functional verification tends to be the most resource-intensive phase of the design cycle. Adopting an industry-standard verification methodology like Universal Verification Methodology (UVM) can play a significant role in speeding up the verification process, paving the way for faster time to market. The sometimes steep learning curve and uncertainty about the best approach to implementing certain functionality can discourage the adoption of UVM. In this tutorial we will outline the best practices that will enable you to quickly put together a reusable UVM testbench. We will start off by describing the UVM template generator, then summarize key coding guidelines for reuse and faster compile turnaround time and finally delve into coverage plan integration.

Synopsys Tools Used:
VCS

Target Audience:
Verification Engineers and Managers


MC06 Extraction for New Transistor Nodes and Technologies
Double Patterning Aware Extraction Flows For Digital Design Sign-Off in 20/14nm
Adrian Au Yeung, Steven Chan, Hendrik Mau, Rick Monga, Tamer Ragheb, Venkat Ramasubramanian, Richard Trihy - GLOBALFOUNDRIES
Due to the use of double patterning (DPT) in 20nm and below technologies, mask misalignment modeling is an important capability in parasitic extraction. StarRCXT offers two different flows to model mask misalignment: the first flow changes the equivalent intra-level dielectric constant as a function of conductor spacing while the second flow performs a “virtual mask shift.” Upon validation of these ”DPT-aware” extraction results on simple structures, we use the flows on a high-frequency SIMD multi-media engine from a CPU core. Both the parasitic from the DPT-aware extraction and the timing results from STA analysis are examined. Variants of the SIMD engine with differing number of DPT metal layers and routing density are examined to determine under what circumstances does mask misalignment warranty increased vigilance during design sign-offs. Based on this extensive analysis, we then provide use models and recommendations on DPT-aware extraction and STA sign-off flows for 20nm and below technologies.

Synopsys Tools Used:
StarRC, PrimeTime, ICC

Target Audience:
CAD and design engineers/managers - Intermediate

Planar MOSFET to FINFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3
Tom Mahatdejkul, Ling Chien, Sreenivas Aluru- ARM
ARM's early engagements with technology developers and foundries positions ARM IP to be ahead of the curve. This early access to industry-leading technology also provides for a steep learning curve with currently available Synopsys tools which include HSPICE for SPICE simulation, FineSIM for characterization and StarRC with Rapid3D for layout parasitic extraction. In this paper, experiences in development stages from layout, to parasitic extraction, to simulation will be discussed as well as some comparisons and benchmarking parametrics of tool performance of FinFET technology vs. planar technology will be presented.

Synopsys Tools Used:
HSPICE, StarRC, FineSim.

Target Audience:
Engineers running SPICE simulation and extraction, validation and resource planning - Introductory to Intermediate Level


MC07 Hybrid Prototyping
Hybrid Prototyping 101
Synopsys
This tutorial provides practical advice and techniques for the integration of virtual and FPGA-based prototypes. Learn how the combination--a hybrid prototype—allows earlier software development by enabling prototype engineers to freely mix model abstractions that are readily available and have the best processing performance. Case studies will illustrate host workstations running both compiled user applications based on C++ and SystemC exchanging data with a Synopsys HAPS FPGA-based prototype. Expert prototyping engineers will discuss incremental bring-up techniques and illustrate by example an ARM Cortex based SoC with integrated SoC block hosted by the FPGA prototype. Tutorial attendees will leave with a good understanding of how hybrid prototypes can benefit development schedules and when it is best to apply them.

Synopsys Tools Used:
VDK Family for ARM Cortex™ processors

Target Audience:
Engineers and engineering managers responsible for ASIC/SoC verification, emulation, and prototyping who are seeking ways to make high-performance prototypes available sooner in the development process and learn about the latest technology to link the TLM to RTL model domains


MC08 Circuit Simulation Release Update
Getting ready for the next technology node
Synopsys
This tutorial will discuss the latest innovations in Synopsys’ market-leading simulators and introduce new features available in the latest release of HSPICE, FineSim and CustomSim. The updates will cover technology advances in device modeling, simulator performance and capacity, and advanced circuit analysis features designed to help you meet the challenges of smaller geometry nodes and changing process models.

Synopsys Tools Used:
HSPICE, FineSim, CustomSim

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers


Monday, March 25, 2013
4:00 PM - 8:00 PM
Designer Community Expo
The Designer Community Expo offers a unique opportunity to meet Synopsys and its design community partners from across the electronics industry to see the latest design solutions spanning seven designer communities. Over 60 companies will be exhibiting this year.

Network with your colleagues while enjoying food, drinks and some great prize drawings held throughout the evening.


Tuesday, March 26, 2013
9:00 AM - 10:00 AM
Keynote Address 2
“From Crystal Ball to Reality – The impact of Silicon IP on SoC Design”
Sir Hossein Yassaie, PhD, Chief Executive Officer, Imagination Technologies Group
SoCs have transformed the semiconductor and electronics industries, integrating staggering breadth of functionality and performance into highly cost-effective, low power but complex single-chip solution platforms. However, there has been another transformation: many of the major functional blocks on today’s SoCs are provided by Silicon IP providers rather than designed in-house. Hossein will review some of the important technological and market trends in key segments and discuss how the IP industry is helping to create the ability to translate vision into reality , and to constantly enhance it. He will touch on key functional blocks in modern SoCs explaining how the GPU is becoming the new driving force not only for modern applications but also for design methodologies and process technologies, and how heterogeneous processing is transforming the way SoCs handle key user applications such as UI’s, gaming, multimedia and more.


Tuesday, March 26, 2013
10:30 AM - 12:00 PM
TA04
TA4-A Transaction Based Assertion for Transaction Level Coverage, Property and Protocol Checking
Sakar Jain, Thinh Ngo - Freescale Semiconductor, Inc.
In this paper we propose transaction-based assertion (TBA) that works on transactions instead of signals. Transaction-based cover assertions can be used for transaction-level coverage to detect various transactions of interest with logical (i.e. and), structural (i.e. equal) or temporal (i.e. concurrently, after) relationships. Transaction-based property assertions can be used for transaction-level protocol checking (i.e. a cache miss must be consecutively followed by a cache fetch of same cache line). Transaction-based assertions can be implemented using SystemVerilog class. Transaction class encapsulates associated signals as its properties and self-monitors the associated DUT logic for its triggering. Transaction types are uniquely defined by triggering properties (i.e. a hit-valid for cache-hit transactions). Additionally, transactions can structurally associate with each other by their compare properties (i.e. transformed address). Transaction-based cover assertion class monitors triggered transactions for their required relationships structurally, logically or temporally. Transaction-based property assertion class checks temporal implication between two structurally related triggered transaction-based cover assertions.

Synopsys Tools Used:
VCS

Target Audience:
All verification engineers - Intermediate


TA04-B
TA4-B Sub-cycle Functional Timing Verification using SystemVerilog Assertions
Anders Nordstrom - Verilab
This paper describes a novel, more complete approach to functional verification of sub-cycle timing using SystemVerilog assertions in an OVM verification environment. This approach found many bugs otherwise missed in OVM-only simulations. This functional sub-cycle timing behaviour includes maintaining fixed delays and phase relationships between inputs and outputs and ensuring there are no glitches on clocks or delayed signals.

SystemVerilog assertions are evaluated on successive occurrences of an event or timing expression. This presents a challenge for sub-cycle timing verification, where there is no obvious reference clock suitable for triggering the assertions. Assertions sample their expressions in the preponed region of the simulation timestep, but the requirements called for sampling both before and after each triggering point. Examples of assertions showing how to overcome this and many other issues will be shown along with recommendations on how to write assertions for functional timing verification.

Synopsys Tools Used:
VCS

Target Audience:
Users applying assertions for verification either on its own, or in an OVM/UVM environment - Advanced


TA06 Maximizing Signoff Productivity
PrimeTime HyperScale - Hierarchical STA
Synopsys
Learn how PrimeTime HyperScale can help designers increase productivity for STA signoff and reduce turnaround time during ECO phase.

This tutorial will cover the following topics:
  • Introduction to HyperScale technology
  • Key HyperScale innovations
  • HyperScale usage for STA and ECO
Synopsys Tools Used:
PrimeTime

Target Audience:
PrimeTime users and managers responsible for design, implementation, and signoff

Simultaneous Multi-Voltage Analysis for Faster Timing Signoff
Synopsys
Learn how PrimeTime’s multi-voltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how RenesasEL has successfully deployed this technology to reduce signoff turnaround time by 5X. This tutorial will focus on achieving faster timing signoff for multi-voltage designs, while avoiding the risk associated with margining-based approaches.

Topics will include:
  • How voltage variations increase signoff corners for multi-voltage designs
  • Technical overview of the PrimeTime multi-voltage aware timing analysis solution
  • RenesasEL case study outlining how this new technology has been adopted
Synopsys Tools Used:
PrimeTime

Target Audience:
Designers and managers responsible for multi-voltage SoC and ASIC design, implementation and signoff


TA07 Network Software Development using Virtual Prototypes
Ease Debug and Control of Network Software Using Virtual Prototypes to Do Full System Simulation
Robert Kaye - ARM, Tom De Schutter - Synopsys
The software communication overhead in networking applications continues to grow. This makes it imperative to bring up the software as early as possible in the context of a full system to both reduce the overall development and debug cycle and to make sure that the setup can be tested in a realistic setting. In this tutorial we will show how you can use a virtual prototype with a DesignWare Gigabit Ethernet model and ARM processor models to simulate a network application like e.g. a server farm. We will show how the virtual prototyping methodology not only enables software development before hardware availability, but also helps reduce the actual development and debug cycle. We will go on to show how virtual prototypes allow software developers to keep an overview of what software tasks are going on at any given time and create predictable test suites for this type of complex design.

Synopsys Tools Used:
VDK Family for ARMv8 processors

Target Audience:
Software Developers and System Architects


TA08 Verification using Verilog-AMS
Analog and Mixed-signal Verification Methodology Using Verilog-AMS
Synopsys
The majority of today's designs contain significant analog and mixed-signal content. Even SoCs that are designed for essentially digital functions still require PLLs for timing control, digitally-controlled power management circuits, and high-speed I/O devices. In this tutorial we discuss how the Synopsys analog/digital co-simulation methodology can be used for logic and timing verification of mixed-signal designs that contain digital place-and-route, custom digital and analog circuits. The first part of the tutorial will focus on the use of Simulation and Analysis Environment in Custom Designer to netlist and simulate a mixed signal design using CustomSim-VCS and then post process the results using WaveView.

The second part will discuss behavioral modeling techniques for improving simulation performance and enabling top-down design. This includes comparing Verilog-AMS with Real Number Modeling and creating different models for some mixed-signal blocks.

Synopsys Tools Used:
CustomSim, VCS

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers


Tuesday, March 26, 2013
12:00 PM - 1:30 PM
TA10 Lunch and Learn
Design Compiler Overcoming the Challenges of Shrinking Design Schedules vs. Increasing Complexity
Attend this special lunch event to hear your peers discuss how they are utilizing DC Explorer and Design Compiler Graphical to tackle the challenges of ever-increasing design complexities and shrinking schedules. The panelists will discuss how DC Explorer helps generate high-quality design data quicker by providing early visibility into design problems and results while producing a netlist that provides a head start to tasks such as physical exploration. You will hear about some of the recent advancements in DC Explorer that enable floorplan creation and design connectivity analysis at a very early design stage. Additionally, the panelists will share how Design Compiler Graphical is helping them attain their design goals by delivering superior quality of results and tighter correlation to layout. Join us to see how these technologies are enabling your fellow Design Compiler users to achieve a faster, convergent early-RTL exploration to GDSII flow.

Target Audience:
RTL design, CAD and back-end Engineers and Managers


TA11 Lunch and Learn
TA11 - Lunch and Learn: Optimization exploration of ARM® Cortex™ Processor-based Designs with the Lynx Design System
Optimized processor-specific flows play a critical role in achieving ARM® processor performance and power goals. To help designers meet these goals, Synopsys has expanded the availability of pre-optimized high performance and low power Lynx flows for ARM Cortex™-A7, -A9 and -A15 processors to accelerate core-hardening. In this session, you will learn how these flows and new chip level optimization methodologies in the Lynx Design System accelerate design closure.

Using a design example based on a Cortex-A15 processor with ARM POP™ technology, we will demonstrate:
  1. Design-specific customizations that leverage the latest tool features such as placement bounding, magnet placement and CTS latency modeling to help achieve performance and power goals
  2. Data-driven engineering trade-off analyses to realize optimal design performance
  3. Final Stage Leakage Recovery (FSLR) and PrimeTime Signoff-Driven Leakage Recovery using multi-channel libraries to recover leakage power late in the design cycle
Target Audience:
You should attend this session if you are a front-end or back-end design engineer, CAD engineer, flow developer or project lead


Tuesday, March 26, 2013
1:30 PM - 3:30 PM
TB01 - Implementation Flows for ARM Cortex-A7 and Cortex-A15 cores
Power-Centric Timing Optimization of an ARM® Quad Core Cortex™-A7 Processor
ARM and Synopsys
Learn how to optimize the Quad-Core ARM® Cortex™-A7 MPCore™ processor for the best power efficiency targeted for entry mobile and other power-sensitive products. This tutorial will highlight the latest technologies in Design Compiler Graphical and IC Compiler that can be used to achieve challenging power/performance targets. Shared best practices leverage Synopsys' high-performance core (HPC) methodology, including optimizations for power as a primary requirement to be managed at each step in the flow; from synthesis, placement, clock and routing, to post-route timing closure. Low power capabilities introduced here are augmented with aggressive power management of library VT classes and timing targets. The power-centric high-performance core methodology will be illustrated through a reference implementation of a quad core Cortex-A7 processor with ARM POP™ technology for core-hardening acceleration on TSMC 28HPM process. The final product is a strong starting point for designing the 'LITTLE' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for cost-sensitive markets.

Engineering Trade-Offs in the Implementation of a High Performance Dual Core ARM® Cortex™-A15 Processor
ARM and Synopsys
Learn about the engineering trade-offs and flow development process to balance gigahertz+ performance and low power on a dual-core Cortex-A15 MPCore™ processor implementation. This tutorial will highlight best practices and technologies from the Galaxy Implementation Platform to meet challenging performance targets, while minimizing leakage power. Synopsys' high-performance core (HPC) methodology will be demonstrated through a reference implementation of a dual-core ARM Cortex-A15 processor with ARM POP™ technology for core-hardening acceleration on TSMC 28HPM process. Technologies featured include physical guidance for a predictable implementation flow, transparent interface optimization for faster top-level closure, and final-stage leakage recovery for reduced leakage power.  The final product is a strong starting point for designing the 'big' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for high-end mobile markets.


TB02 Physical Verification of a Production FinFET SoC with IC Validator
Advancements in Density Management at 20nm and below with IC Validator
Synopsys
At the 20nm process node and below, maintaining optimal design density for lithographic accuracy and yield is impacting physical design more than ever before. The introduction of double patterning, reduced layer thickness and near-zero depth of focus tolerance have led to increasingly complex design restrictions. In addition, timing closure of state-of-the-art designs requires designers to carefully analyze and optimize the density of each mask layer. In this session, we will discuss how manufacturing challenges at 20nm and below are mandating advancements in density management technology. We will then present innovative technologies in IC Validator and IC Compiler that ensure optimal manufacturing compliance at advanced nodes.

Synopsys Tools Used:
IC Validator, IC Compiler

Target audience:
Design and CAD Engineers and Managers responsible for physical implementation and verification.


TB03 Meeting Test Quality Goals
Meeting Quality Goals for Gigascale Designs: Trends and Solutions
Synopsys
This tutorial will highlight leading-edge capabilities in the Synopsys synthesis-based test solution for maximizing productivity, increasing test quality, and lowering test cost. First we will discuss how standards-based DFT has evolved within DFTMAX compression to save time and effort when implementing test for extremely complex designs. Next we will examine several advanced detection mechanisms in TetraMAX ATPG for improving defect coverage. Finally we will show new features in the tools that lower the cost of testing ARM processor-based designs and other multicore SoCs.

Synopsys Tools Used:
DFTMAX, TetraMAX

Target Audience:
Designers and managers interested in test, quality, and manufacturing


TB04
TB4-A Challenges with Design and Verification of State Retention in a Complex Low-Power SoC
Yushi Tian - Broadcom Corp.; Amir Nilipour, Ajay Thiriveedhi - Synopsys
State retention is a widely-used, low-power technique to achieve significant power savings, while maintaining system performance. Retaining state value does come with additional silicon area cost, however. In today’s low-power SoC platforms, an optimal design could have sub systems with and without retention registers which could introduce various design and verification challenges. Various retention schemes are analyzed and the challenges associated with design and verification of such systems are discussed in the paper. Different retention schemes can be captured in power intent file through UPF. Using MVSIM-NLP as the simulator, the authors demonstrate how the Retention features can be verified early in the design flow in a comprehensive manner. All aspects of the verification process, from retention specification to final debug using MVSIM-NLP will be discussed.

Synopsys Tools Used:
VCS, MVSIM-NLP

Target Audience:
Engineers concerned with power retention verfication - Intermediate


TB04-B
TB4-B Formal Verification of Floating-Point Arithmetic Datapath Block
Leonard Rarick - Imagination Technologies, Inc. Ajit Limaye - Synopsys
In 2011, MIPS Technologies, Inc. initiated the development of a new IEEE-compliant floating point unit (FPU), to be offered as an optional addition to the new AptivTM generation of processor cores. Since this core performs operations with one, two and three operands in single and double precision, the input space can contain up to 2192 possibilities (for double-precision, 3-operand instructions). Recognizing that random methods alone would be inadequate for verifying this design, MIPS evaluated formal verification tools and selected the Hector high-level equivalence software from Synopsys to verify the arithmetic data path. This was the first use of Hector at MIPS, and this paper describes MIPS’ experience with it and the results that were achieved – over 200 bugs were found, and proofs were obtained for most operations. This paper also discusses lessons learned and describes some tools that were developed to supplement Hector and thereby streamline its use on future projects.

Synopsys Tools Used:
Hector (C++ to RTL Equivalence Checker)

Target Audience:
Users implementing computations such as CPU arithmetic or filters in hardware - Intermediate.


TB04-C
TB4-C A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests
Richard Tseng - Qualcomm
An SoC design in a company usually would have evolved over many product generations. There are many software tests recognized as “golden” regression suites that have been used for design tape out. While the design verification community moves toward UVM, engineers have been facing a big challenge to reuse or import those golden C tests in a UVM testbench. In this paper, a generic UVM testbench architecture that overcomes this challenge will be demonstrated. The testbench allows engineers to reuse high-level verification components, and C and UVM test sequences for future design generations. It also allows users to run multiple C and UVM mixed test sequences concurrently. Test writers can use those existing API tasks and UVM reporting macros, such as `uvm_info and `uvm_error in C and UVM interchangeably. The integration of the UVM register layer will also be addressed.

Synopsys Tools Used:
VCS

Target Audience:
Intermediate/advanced UVM users


TB05 Integrating Virtual Platforms into Hardware Accelerated RTL
Introduction to Integration of Virtual Platform Technologies with Hardware Accelerated RTL
Synopsys
This tutorial will provide an introduction to the verification and validation use cases afforded by the integration of Virtual Platform technologies with hardware accelerated RTL under emulation. These use cases will cover verification/validation of standalone processors as well as full blown SoCs. The tutorial offers specifics of how to architect the split between virtual platform and emulator and how to implement the transaction-based interfaces between the two. The focus will be on how to optimize this transaction-based interface in a scalable and efficient manner.

Synopsys Tools Used:
ZeBu Server, Virtualizer

Target Audience:
Hardware/Software Validation Engineers, Verification Engineers, Model Developers


TB06 Leakage Recovery with PrimeTime
Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction
Synopsys
PrimeTime’s 2012.12 release builds on top of Synopsys’ Galaxy low power flow and adds signoff based leakage recovery to existing ECO guidance capabilities. This tutorial will review PrimeTime’s latest enhancements to final stage ECO timing closure and how to use these capabilities together effectively. You will learn how PrimeTime’s ECO flow compliments IC Compiler’s new Minimal Physical Impact (MPI) capability to achieve fast, convergent ECOs.

Tools Used:
PrimeTime

Target Audience:
This tutorial is for all designers responsible for timing convergence and signoff.

Leakage Recovery across Multiple Timing Scenarios
Russell Vickers - Intel
This presentation discusses a methodology for leakage recovery across multiple scenarios.. Concurrent fixing across all modes and corners has become increasingly demanding as process technology advances towards 12/14nm. With these more complex technologies, leakage power can be very significant and also needs to be addressed in the context of all the signoff scenarios. We will assess how leakage recovery capabilities can be used to reduce the leakage power of a design, see how it fits into a signoff flow, and examine the impact leakage recovery has on silicon performance.

Target Audience:
Customers interested in signoff-based ECO-guidance for leakage recovery


TB07 SoC Architecture Optimization
Low Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs
Synopsys
For many mobile devices, low power video processing is critical to product success. To enable a great experience with long battery life, designers are offloading demanding video processing tasks from the CPU and mapping them to embedded GPUs that work in parallel. But how many GPUs are needed? Which mapping is best? This tutorial features Synopsys Platform Architect to explore HW-SW partitioning and mapping of a real-time video encoding algorithm for optimal system performance and power.

Synopsys Tools Used:
Platform Architect MCO

Target Audience:
SoC Architects, System Designers, Product Architects and Project Managers

SoC Architecture Analysis and Optimization Using Synopsys Platform Architect MCO
Tom Ajamian - Analog Devices, Inc.
As SoC complexity continues to increase, the number of design and architectural trade-offs required for a product grow as well. With this complexity comes the need to make the trade-offs early in the design cycle, helping to improve time-to-market. While RTL integration is typically not available early on, there are alternative methods to measure performance and compare architectural trade-offs, including those based on SystemC TLM2.0. This presentation describes several projects utilizing Platform Architect MCO — a SystemC TLM2.0 design, simulation and analysis environment — along with specific methodologies and custom tools we designed and implemented. These projects include a cache sizing analysis, an effort to understand multicore communications overhead for a programmable processor, and an interconnect analysis utilizing Platform Architect MCO's IMPO flow.

Synopsys Tools Used:
Platform Architect MCO, IMPO Solution Methodology

Target Audience:
SoC Architects, System Designers, Product Architects, and Project Managers


TB08
TB8-A A Practical Look at Current Analysis in FastSpice
Synopsys
With smaller process geometries, detailed Current Analysis has become more crucial, highlighting the challenges of obtaining reliable Current results through circuit simulation. This presentation will be a practical discussion of these challenges and how they are handled in FastSpice, including analysis of real examples. We will examine how simulator accuracy, measurement methodology and circuit state can impact the reliability of Current Analysis results in FastSpice. Additional topics include methods to improve the user’s confidence in their Current Analysis results and available XA features to further improve Current Analysis results.

Synopsys Tools Used:
CustomSim/XA

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers


TB08-B
TB8-B Transistor Level Static Circuit Analysis to Tackle ERC & ESD Challenges
Synopsys
With semiconductors delivering faster speeds at reduced operating voltages, ERC (electrical rule check) to address issue such as power leakage is critical. A transistor level static circuit analysis solution, such as CircuitCheck, can apply circuit topology and connectivity to efficiently discover potential design errors that might be missed with traditional full-blown simulation methods. Join this tutorial to learn new ERC & ESD analysis approaches available in CircuitCheck and the advantages in coverage, capacity, and stimulus independence CircuitCheck provides. Discover how the transistor level static analysis, combined with Custom Explorer Ultra, can be used to visualize ERC/ESD violation and then conduct further circuit debugging.

Synopsys Tools Used:
Circuit Check

Target Audience:
Analog, Custom Digital, Memory and Mixed-Signal Design Engineers, CAD Managers and Engineering Managers


Tuesday, March 26, 2013
3:45 PM - 5:15 PM
TC01
TC1-A Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High Performance Mobile SoCs - Technical Committee Award, Honorable Mention
John Biggs, David Flynn, James Myers - ARM
Technical Committee Award Honorable Mention!
Power gating is now a mainstream leakage mitigation technique in all modern applications processor cores, but saving away program state and actually shutting down is an energy gamble left to the operating system. A more energy optimal approach is to use hardware state retention registers but the associated area and performance penalties have prevented wide adoption to date. This paper describes an advanced state retention scheme which builds upon power gating with minimal additional area and performance impact, discusses application to an ARM processor implemented using Design Compiler and IC Compiler tools with a UPF-based flow and 28nm library.

Synopsys Tools Used:
Design Compiler, IC Compiler, VCS, PrimeTime-PX

Target Audience:
Implementation engineers with knowledge of low-power design, multi-voltage tools and power intent, and anyone interested in low-power chip design - Intermediate


TC01-B
TC1-B Panel – Achieving Optimum Results on High Performance Processor Cores
Broadcom, MediaTek, Samsung and STMicroelectronics
In this interactive two-part session, designers with hands-on experience implementing high performance processor cores will share insights and best practices for achieving optimum performance and power. Each panelist will highlight a design challenge and solution in the implementation process – from synthesis to placement, CTS, routing and signoff STA closure - featuring techniques and technologies available with the Galaxy Implementation Platform. The second part of the session will be an interactive “ask the experts” panel discussion where audience members can dig deeper into the insights and best practices shared. For example, have you wondered when to use mesh and when to use traditional CTS on your high performance design? Or, whether and where to use structured placement to get better results? Don’t miss the opportunity to hear responses to these and other challenges and experience what your peers and Synopsys experts have to say about optimizing high performance cores.

Target audience:
High performance core designers, back-end and front-end implementation users


TC02 Design Environments using Lynx
Using the Lynx Design System to Lower the Cost of Bringing up a New Flow on a New Node
Simone Borri, Christian Eichrodt, Pierre-Marie Signe - Abilis Systems; Riccardo Giordani - Synopsys
Competitive performance and schedule pressures often drive semiconductor companies to migrate to smaller technology nodes. These migrations are usually expensive in terms of time and resources and pose risks to critical projects because they require specialized skills and flow development in parallel with chip development.

In this paper, we will take you through the process of migrating to a full Synopsys-based, RTL-to-GDSII flow from the perspective of a company focused on controlling design costs, evaluating different process technologies, quickly integrating third-party IP, getting to a stable flow deployed to the design team as quickly as possible, and maximizing the performance of the design.

We will discuss the key aspects of Lynx that allowed us to achieve our goals on a recent digital TV chip project, including the integration of analog tools such as Custom Designer into the flow.

Synopsys Tools/Systems Used:
Most Galaxy Implementation Platform tools, Synopsys IPs (ARC cores, Virage memories, std. cells), Custom Designer; Lynx

Target Audience:
Physical design engineers, project leaders, project managers looking for solutions to optimize time-to-tapeout and minimize risks associated to a technology switch - Intermediate

Standardized Design Environment and Methodologies Enable Simultaneous Implementation of 28nm Designs on a Single Flow
Cyrille Thomas - Bull SAS
Using a configurable, pre-validated standardized flow and integrated GUIs in Synopsys’ Lynx Design System, we were able to quickly deploy a new 28-nm RTL-to-GDSII flow. This environment allows our geographically distributed engineers to simultaneously work on multiple projects targeting different technologies. In addition, the new visualization capabilities in Lynx provide us with dynamic access to project metrics and trends such as execution profile reports, licenses usage, metrics vs. metrics, enabling us to make the data-driven decisions on design constraint changes and designer re-allocation to help meet schedule. In this paper we will talk about a few of the features in Lynx such as job distribution optimization, third-party tool adoption and improved ramp-up that helped us achieve our goals on a recent tapeout.

Synopsys Tools/Systems Used:
Lynx, Design Compiler, IC Compiler, IC Validator, PrimeTime SI

Target Audience:
Implementation engineers, managers interested in design productivity improvement on designs moving to new technology nodes, with distributed teams - Intermediate


TC03 Small Delay Defect Model and Advanced Debugging Test
Improving At-Speed Test Quality with the Small Delay Defect Model
Jon Colburn, Dheepakkumaran Jayaraman, Bala Tarun Nelapatla, Arvind Vinod - NVIDIA
The importance of testing for timing-related defects continues to increase as devices are manufactured at smaller geometries. Because of this it is increasingly important to have high-quality delay tests for delay defects. Transition fault testing is the standard method for delay fault testing, but its effectiveness can suffer because faults may not be tested along an optimal path for detecting the smallest detectable timing variation. Path delay testing provides tests along the ideal for testing delays but suffers because of extremely large pattern counts and run-times which make it an impractical technique for testing all possible transition fault locations. The Small Delay Fault model attempts to blend some of the benefits from both techniques, but there are still runtime and efficiency trade-offs. We describe some flows designed to balance the needs of pattern delivery schedules, ATPG efficiency and improved test quality.

Synopsys Tools Used:
TetraMAX, PrimeTime.

Target Audience:
Users interested in higher-quality testing - Intermediate

Advanced TetraMAX Debugging Techniques for AMD's High-Performance Cores
Martin Amodeo, Thomas Clouqueur, Jan Ness - Advanced Micro Devices, Inc.; Tim Ayres, Lori Schramm, Tim Yuan - Synopsys
The demand for higher-performance microprocessors continues to grow. Smaller feature sizes, higher clock speeds, and low-power demands are only some of the challenges facing designers today. Several of the AMD cores in production today support multiple scan compression tools in order to get access to the latest capabilities of leading EDA ATPG tools. This paper describes some of the unique design-for-test (DFT) challenges for today’s microprocessor cores as well as several of the enhancements and advanced debugging techniques used with TetraMAX ATPG on a next-generation x86 core.

Synopsys Tools Used:
TetraMAX, VCS

Target Audience:
DFT, test and implementation engineers - Advanced


TC04 Transaction-level Verification with ZeBu-Server
Transaction-level Verification with ZeBu-Server - What, When, How
Synopsys
In this tutorial you will learn what transaction-level verification means in general and specifically how it applies to the ZeBu-Server emulation platform. Transactors offer a unique combination of performance, accessibility, flexibility and scalability, while providing a realistic system-level test environment for the DUT. Transactors allow you to quickly build a high-speed system-level Virtual Platform by surrounding your emulated DUT with Virtual Components that interact with its various interfaces.

The tutorial will describe the inner workings of a transactor with emphasis on the advantages and tradeoffs compared to alternative approaches, including the traditional in-circuit emulation (ICE) approach. Step-by-step instructions for creating a transactor will be provided, including an introduction to a high-level SystemVerilog behavioral language/compiler, called ZEMI3, conceived for automating the generation of a transactor. Closing the session, a practical application in the wireless space will be described in detail including steps to compile a design into the ZeBu-Server.

Synopsys Tools Used:
ZeBu-Server, ZEMI3

Target Audience:
Design Verification Leads and Managers


TC05 Low Power Verification Debug
Can You Tell Your ISO from LS? – A Methodology for Low Power Debug
Synopsys
With the widespread adoption of advanced low power design and implementation techniques in SoC designs, the role of low power verification is more critical than ever. While even the simplest power management architectures pose a tough verification and debug challenge, the more complex architectures require a complete re-think of the verification paradigm. This tutorial provides insight into debug solutions that adequately address efficient debugging of the range of low-power techniques - from simple power-gating to retention technique to low power sequences in dynamic simulations. It also discusses how low power coverage and its visualization can help determine the completeness of the verification effort.

Synopsys Tools Used:
VCS, DVE and Verdi3 low power debug platform

Target Audience:
Verification Engineers and Managers. Covers advanced low power techniques.


TC06 Mode-Merging using PrimeTime
Using Mode-Merging to Reduce Scenarios Required for Timing Closure and Signoff
Synopsys
Learn how PrimeTime mode merging reduces scenarios for timing analysis and implementation to improve turn-around-time and resource requirements. This tutorial will focus on using PrimeTime mode merging to reduce multiple mode constraints into a smaller set of merged constraints, while reducing run time and memory, and maintaining signoff QoR. Topics will include:

  • PrimeTime mode merging – a technical overview
  • Using PrimeTime mode merging to reduce scenarios for ECO and signoff
Synopsys Tools Used:
PrimeTime

Target Audience:
Designers and managers responsible for multi-scenario SoC and ASIC design, implementation and signoff

Automated Mode Merging of Timing Constraints using PrimeTime
Harish Aepala, Nick Oleksinski, Bruce Zahn - LSI Corp.
One of our challenges in managing LSI's STA environment has been the continued increase in modes and corners that need to be run for signoff. This paper will discuss how we used PrimeTime’s automated Mode Merging to merge constraints from different design modes. Several examples will be provided on how feedback from the mode merging capability allowed us to modify our constraints to achieve better mode reduction. We will also show how we have been able to easily adapt our existing PrimeTime STA setup to add automated mode merging.

Synopsys Tools Used:
PrimeTime

Target Audience:
Designers who manage timing constraints for multiple modes and perform ECO using PrimeTime STA - Intermediate


TC07 Power Management Software Development using Virtual Prototypes
Using Virtual Prototypes for the Early Bring-Up and Test of Power Management Software
Synopsys
The regulation of frequencies and voltages has become a major aspect to operating system bring-up on new hardware. An analysis of complexity on recent commercial embedded application processors has shown that the drivers and configuration for the clocks and voltage regulator alone make up 50% of the device software code. In this tutorial, we will demonstrate how virtual prototypes enable the early bring-up of power-related software aspects without running into the danger of harming the hardware through overvoltage or other software defects. The tutorial will also cover the functions of major software power management frameworks within different layers of embedded software stacks. We will highlight how Virtualizer Development Kits (VDKs) are used to optimize system wide power management by simulating and analyzing power at the system level driven by real world scenario data.


TC09 Increasing ARC Performance and Reducing Power
Increasing Performance and Reducing Power through Memory Request Optimization
Gregg Recupero - Performance-IP
Memory latency limits performance in many of today's multi-client SoC designs. As CPU performance has continued to increase at almost exponential rates, memory performance has struggled to keep up with that pace. Memory prefetch engines have been used as a technique to reduce memory latency. With the vastly divergent request patterns of today's multi-client SoCs, yesterday's prefetch engines struggle to achieve high efficiency rates. Coupled with today's green design requirements, every false fetch can negatively affect your power budget. This paper demonstrates how system-level SoC performance can be improved using a next generation prefetch engine with ARC processors. This simultaneously reduces the number of read requests that reach the external memory system and reduces power consumption through Memory Request Optimization. As an example a modern design with a Synopsys ARC Processor is used to illustrate the results.

Synopsys Tools Used:
ARC Audio Processor, VCS

Target Audience:
Synopsys IP users who wish to improve the performance of their memory sub-system - Intermediate


Tuesday, March 26, 2013
4:45 PM - 7:00 PM
SNUG Pub
Stay and play - Silicon Valley’s largest pub is back and better than ever! Enjoy a fun evening with colleagues and Synopsys R&D, Executives and support staff. Challenge them on the micro-racetrack, the foosball or air hockey table and work up an appetite for some good food and drinks. Don’t forget to stick around for the drawings for some terrific prizes. See you at the Pub!


PrimeTime SIG
Featuring PrimeTime ADV - Advanced Timing Technology

PrimeTime SIG Dinner Registration Walk-ins are welcome. Synopsys hosts worldwide annual events for the PrimeTime Special Interest Group, providing an opportunity for PrimeTime users and design engineers to stay connected with the latest developments in the field of Static Timing Analysis (STA). We are pleased to host this PrimeTime SIG event at SNUG Silicon Valley 2013.

Synopsys' R&D team will unveil new technologies that extend PrimeTime static timing analysis to address some of the toughest problems found on the most advanced technology nodes. Key customers will share their experience on qualifying PrimeTime ADV for use in their design flows.

There will be a Question and Answer session at the end of the presentations for direct speaker-audience interaction. This event is open to Synopsys PrimeTime users and engineering managers.



Wednesday, March 27, 2013
9:00 AM - 10:00 AM
Keynote Address 3
Collaborate to Innovate – A Foundry's Perspective on Ecosystem
Dr. Cliff Hou, Vice President, Research & Development, TSMC
Ecosystem refers to a symbiotic, co-dependent, co-evolutionary and multiplicative relationship among its constituents. The semiconductor industry represents one of the largest business ecosystems in the world where the collective diversity and creativity has fundamentally reshaped the human society. As process scaling continues toward the atomic level, challenges abound and stakes are never higher. In this talk, we will offer a foundry perspective of the semiconductor ecosystem and how, through close collaboration, we combine individual specialties and resources to innovate and move the industry forward. Specifically, we will discuss how the collaboration with EDA is becoming ever closer, earlier and wider to enable designs concurrently with process development, even especially at the advanced nodes.


Wednesday, March 27, 2013
10:30 AM - 12:00 PM
WA01 Advanced CTS Features and Methodologies
Achieving Higher Frequencies for Your Design with Early Clockgating Optimization and Comprehensive Useful Skew
Synopsys
This tutorial introduces new ICC features targeting higher frequencies and improved ease of use. We’ll describe enhancements to the placement and optimization of the clockgating elements prior to CTS, which deliver improved timing and convergence of the flow. The new features use improved clockgate restructuring and CTS latency estimation for more accurate clockgate placement and clock enable path timing optimization. The session will also cover new skew features in IC Compiler which use techniques including multi-stage slack borrowing and on-the-fly clock tree adjustment. These features will enable you to meet frequency goals using a simple flow, without resorting to complex multipass approaches.

Synopsys Tools Used:
IC Compiler

Target Audience:
IC Compiler users targeting high frequency solutions


WA02 Custom Design Using Laker
Laker 3 Custom Layout System - “An advanced process node custom layout tutorial”
Synopsys
In this technology session you will learn about the new layout challenges introduced by 20nm and below process technology. You’ll also see the advanced features in the Laker Custom Layout Solution that help with these issues. Laker is extremely fast and has unique automation features that are ideal solutions for those seeking to improve layout productivity.

Technologies that will be covered in this tutorial include Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features — which have been all fully updated for process nodes at 20 nanometers and below.

Target Audience:
Layout Designers/Engineers & CAD Managers


WA03 STAR Memory System
Embedded Memory Test, Repair & Diagnostics: DesignWare STAR Memory System Updates
Synopsys
The DesignWare STAR Memory System is a comprehensive, integrated memory test, repair and diagnostics solution that supports both Synopsys and third party embedded memories. The tutorial will provide an overview of the solution and updates on the fifth generation STAR Memory System, which adds a new hierarchical embedded memory test and repair architecture, resulting in a 30% area reduction compared to the previous generation, as well as new test and repair algorithms that target designs on advanced technology nodes.

Synopsys IP Used:
DesignWare STAR Memory System

Target Audience:
Designers, DFT Engineers, Test Engineers, Product Engineers and Foundry Engineers who are, or will be, designing or characterizing the SoCs. The tutorial will provide introductory as well as advanced content.


WA05 High Performance Computing
High Performance Computing for Silicon Design
Shesha Krishnapura - Intel
Silicon design technical complexity increases every year due to new features and the shrinking of process technology. Intensifying the trend are business drivers including shorter product development time and the pressures for reduced headcount and lower cost. These factors combine to require a focus on pre-silicon verification, a high degree of design automation and global multi-site design teams. These technological and business issues have astronomically increased demand for computing and storage, which in turn drives the need for product development to be engineered in an optimal computing environment. Intel IT has implemented an HPC solution with 50,000 globally distributed compute systems. This presentation will cover Intel’s most-recent innovations in their use of HPC for electronic design automation.

Target Audience:
IT and CAD personnel who manage compute resources for EDA applications


WA06 Noise Analysis
Digital->Analog Noise Detection (DANDy)
Jason Rziha, Vardhini Muralidaran - Microchip Technology
The risk of crosstalk onto analog nets is a constant concern in digital designs that is often not analyzed in traditional flows. This paper examines a technique using PrimeTime-SI to generate an upper limit of the crosstalk on analog nets caused by the digital signals. If this technique reveals potential issues, further analysis via HSPICE can then be used.

Synopsys Tools Used:
PrimeTime-SI, HSPICE.

Target Audience:
Users concernced with crosstalk on analog nets - Advanced

Transistor-Level Timing and Noise Analysis of Peripheral Logic of High Speed Memory Design
Johnie Au, Sunilkumar Koduru, Jun Li - Cypress Semiconductor; Sahil Bargal - Synopsys
This paper describes static timing and cross-coupled noise analysis at the transistor level for peripheral logic of high speed and high bandwidth memory design. The paper will present NanoTime setup and usage guidelines for static timing and noise analysis including a discussion on the setup of advanced differential and self-timed circuits. Parasitic extraction and back annotation methodology for NanoTime will also be discussed. Our crosstalk analysis methodology, which avoids timing delay pushout due to signal coupling, will be discussed as well. Finally, recommendations for improving NanoTime will be covered, including tips for modeling behavioral resistors, explanations of special warning messages, and suggestions for resolving issues.

Synopsys Tools Used:
NanoTime

Target Audience:
NanoTime users interested in "self-timed" circuits - Introductory


WA07 Designing with Xilinx 7 Series FPGAs
The Essentials for an Integrated Synplify-Vivado Design Flow Targeting Xilinx 7 Series FPGAs
Synopsys
This tutorial is for FPGA designers targeting Xilinx 7 Series FPGAs (Virtex-7, Kintex-7, Artix-7 and Zynq) using Synplify synthesis and Vivado place & route. You will learn how to easily run Vivado via the Synopsys provided TCL scripting templates as well as how to drive synthesis and place and route to achieve maximum efficiency and quality of results for your 7 Series designs. Key topics that will be discussed include constraints setup, forward annotation of information to place & route, IP handling and incremental design flows. The tutorial is designed to provide practical knowledge that may be used right away on 7 Series FPGAs.

Target Audience:
FPGA Designers looking for practical knowledge to gain maximum efficiency and quality of results targeting 7 Series designs


Wednesday, March 27, 2013
1:00 PM - 2:30 PM
WB01 Multi-Bit Banking Solution
Introduction of Multi-Bit Banking Solution
Synopsys
Optimization for power is one of the most important objectives in nanometer IC design. Reducing power consumption in chips enables better, cheaper products to be designed and power-related chip failures to be minimized. Clock trees are one of the biggest contributors to power consumption. By keeping the actual length of the clock tree short, we can immediately reduce the overall power consumption. This session will describe how IC Compiler was used to reduce the clock tree length by grouping registers together in banks of registers (the so-called multi-bit banks). By ensuring that several registers are inside one macro, the length of the clock net is reduced, resulting in power savings.

Synopsys Tools Used:
IC Compiler

Target Audience:
IC Compiler and DC Compiler users who are considering usage of multi bit registers


WB03 Multi-Die Memory Test for 2.5D Interposer
Multi-Die Memory Test in a 2.5D Silicon Interposer-Based Design
Synopsys
With 2.5D interposer and 3D die stacking innovations, logic-and-memory systems gain dramatic bandwidth and performance over traditional discrete packaging. Higher cell density and process complexity associated with 2.5D/3D ICs place increasing demands on manufacturing test. Through-silicon-via (TSV) based designs create unique multi-die test challenges, increase the complexity of testing, and can impact yield significantly. This tutorial focuses on the implementation of multi-die memory test using Synopsys DesignWare STAR Memory System along with multi-die logic test using DFTMAX on a small interposer example design containing a CPU and a memory die with DDR3 technology.

Synopsys tools used:
IC Compiler, SMS, DFTMAX

Target audience:
Designers interested in 2.5D silicon interposer design and testability


WB04 VCS for Best Debug
VCS Technologies for Best Debug and Analysis
Synopsys
This tutorial will focus on several technologies recently added to VCS that dramatically improve debug productivity. Checkpoint and interactive rewind enable the user to quickly step back in simulation time without having to restart and rerun the simulation. Dumping and browsing of dynamic/testbench objects is now possible using the DVE Object browser which allows complex object relationships to be displayed. Recent improvements to the DVE Constraint GUI allow graphical constraint debug, what-if analysis and distribution-debug to be performed. Finally UVM and VMM specific debug topics will be covered.

Synopsys Tools Used:
VCS, DVE

Target Audience:
Verification Engineers and RTL Designers who want to debug SystemVerilog testbenches more effectively using the latest tools, tips and techniques.


WB05 Managing and Optimizing Compute Infrastructure
HP’s Common Engineering Environment for VLSI design
Jeff Quigley - Hewlett Packard
This presentation describes Hewlett Packard’s first attempt at designing and deploying a common engineering datacenter for all VLSI design in HP worldwide. It will cover the motivations for moving to a common datacenter, a profile of the users and user applications and the original datacenter architecture. It will then describe the user experience through implementation and deployment, lessons learned and modifications made. The presentation will also describe the real benefits VLSI design engineers have experienced in the centralized EDA datacenter as well as some of the challenges.

Target Audience:
IT and CAD personnel who manage compute resources for EDA applications

Advanced Load Balancing and Resource Sharing Solutions
Robert Veltman, Vikash Tyagi - SanDisk
When it comes to managing licenses and computing resources, load balancing solutions are the de facto standard. Balancing EDA workloads to achieve the highest level of resource utilization is a compelling business objective. This paper discusses how we maximize license utilization across international regions and business organizational divides. We’ll explain how some of the traditional local balancing concepts fall short and how we arrive at selecting a new commercial load-balancing tool combined with in-house developed solutions to meet our business requirement. Topics covered by this paper include pre-emption, fast fairshare, multi-queue, defining workload priority, interactive workloads and tiered licensing challenges.

Synopsys Tools Used:
Analog circuit simulation and logic verification tools

Target Audience:
Those burdened with load balancing implementation - Intermediate


WB06 Characterization Solutions
SiliconSmart Flow for Characterization Production Runs
Beibei Ren - NVIDIA; Manjunath B Thimmachary - Synopsys
As we scale down the technology, the process variations increase and this has led to a drastic increase in the number of PVT corners to be characterized. Advanced low-power design techniques and the ever increasing push for optimization has led to larger libraries with more complex cells such as multi-voltage level shifters, retention logic, synchronizer cells, etc. Advanced modeling constructs that support timing, noise and power analysis are required for DSM nodes. Hence, the characterization production runs need to be efficient, reliable and scalable. This paper describes the characterization environment at NVIDIA including the validation flow. Strategies adopted to improve throughput without compromising accuracy will also be highlighted.
Synopsys Tools Used:
SiliconSmart

Target Audience:
Users interested in characterization validation - Intermediate.

CCS Noise Characterization Solution
Synopsys
As technology nodes shrink, the effects of noise are getting more pronounced and an accurate representation in the Liberty model is crucial for static noise analysis. Designers can characterize and add accurate noise models to their Liberty libraries using SiliconSmart’s built-in noise characterization solution with fast turn-around time. SiliconSmart is a comprehensive characterization solution for standard cells, I/O and memory. It generates accurate model libraries tightly correlated with Synopsys' digital implementation tools. This presentation will focus of how to use SiliconSmart to quickly generate CCS noise models for standard cells, IO’s and memories.

Target Audience:
Library Characterization Teams, IP providers


WB07 Maximizing Productivity on Large FPGA Designs
Methodologies and Techniques for Maximizing Productivity on Large FPGA Designs
Synopsys
FPGA designs have become very large. As a result the traditional top-down approach to implementation can be problematic due to long tool runtimes and the massive number of design files that must be managed. This tutorial is for designers of large FPGAs who need to reduce their overall design turnaround time and still hit aggressive performance targets. Key topics that will be discussed include: hierarchical design with a mixed top-down/bottom-up approach; techniques for incremental design; runtime improvement; and IP handling. Features to facilitate TCL scripting make it easy to search large databases, create customized reports and extract a plethora of other useful information will also be discussed. Participants in this session will learn how to take advantage of these features to achieve efficiency and enhance the design process for your FPGA designs.

Target Audience:
FPGA Designers assembling designs that include large IPs or significant amounts of reused code, wishing to stabilize designs quickly and improve runtime


Wednesday, March 27, 2013
2:45 PM - 4:15 PM
WC01 Compiler ECO Flows
IC Compiler ECO Flows for Minimal Physical Impact
Synopsys
With ever-increasing design complexity, a fast, convergent ECO flow is a prerequisite for today’s high performance design flows. This tutorial will outline the latest IC Compiler ECO capabilities, focusing on the new Minimal Physical Impact (MPI). Also discussed will be the latest IC Compiler-PrimeTime ECO signoff flow considerations.

Synopsys Tools Used:
IC Compiler, PrimeTime

Target Audience:
Experienced users of IC Compiler and PrimeTime who are familiar with existing ECO flows in both tools


WC03 Physical Failure and Yield Analysis
Successful Volume Diagnostics in a Fabless/Foundry Ecosystem
Synopsys
This tutorial will provide the latest updates to Yield Explorer, including advanced yield correlations with diagnostics data, static timing correlation to timing related defects, and yield-ramp collaboration between fabless and foundries. The full Synopsys Physical Failure Analysis flow will also be demonstrated, going from Volume Diagnostics to PFA.

Synopsys Tools Used:
Yield Explorer, TetraMAX, PrimeTime, Camelot

Target Audience:
DFT, Product, Yield, and Failure Analysis Engineers and Managers


WC05 Storage Optimization
VCS Acceleration Enabled by Storage Optimization
Ravi Poddar/ Bikash Roy Choudhury - NetApp
VCS application performance can be limited by shared storage devices in highly concurrent VCS deployments. This paper will outline VCS application acceleration achieved by architecting the underlying NetApp storage infrastructure to perform optimally in these environments. Significant reductions in VCS run time were observed for real customer test cases in the build and simulation phases of VCS, thereby positively impacting time-to-market, design quality and ROI on design tools and infrastructure. Storage optimization guidelines will be presented, although actual performance gains will vary based on design type and type of simulation being run. This work was a result of joint collaboration between NetApp and Synopsys.

Target Audience:
IT and CAD personnel who manage storage resources for EDA applications


WC06 Memory and Custom Digital Block Analysis and Charaterization
Analysis and Characterization of Memories and Custom Digital Blocks using NanoTime
Synopsys
As memory content in System-on-Chip (SoC) continues to increase, so does silicon area in the form of embedded SRAM, ROM, multi-port register files. On top of that, shrinking layout geometries have been responsible for a steady increase in the complexity of designs and in the verification challenges. This has required improvements in analysis and modeling to better represent complex custom macros and memory blocks for full-chip static timing sign-off. This tutorial will cover how to use NanoTime to create accurate models for embedded SRAMs and custom digital blocks through concurrent timing and SI crosstalk delay/noise analysis.

Synopsys Tools Used:
NanoTime, SiliconSmart

Audience:
Memory and custom digital block designers


WC07 Synthesis Methods for FPGA-Based Prototyping
Synthesis Methods for FPGA-Based Prototyping
Synopsys
This tutorial is for design and verification engineers who are synthesizing FPGAs that will be used for prototyping an ASIC or SOC device. It focuses on how to quickly bring RTL code written for an ASIC or SOC device into an FPGA(s). Techniques for getting the design into the prototype quickly such as DesignWare synthesis, automated gated and generated clock conversion, HDL code checking with continue on compile error capability, and fast synthesis mode with multi-processing will be discussed in detail.

Synopsys Tools Used:

Target Audience:
FPGA Designers assembling designs that include large IPs or significant amounts of reused code, wishing to stabilize designs quickly and improve runtime


Optimum Design Planning with DC-Graphical and ICC-DP
Gan Chong Gim - Altera

Could Simulation Run Faster and Faster?
Roman Wang & Karl Whiting - Advanced Micro Drvices, Inc

Partition-based Scan Compression Approach for Large Pin Limited Designs
Bhagavathi Mula, - Juniper, Richard Lee, - Synopsys, Jim Hulings, - Avago

Exploiting Parallelism in Serial DFT Simulations
Ivor Ting, Saghir Shaikh, - Broadcom Corporation, Amir Nilipour, Ajay Thiriveedhi, - Synopsys

Clock Path ECO with PrimeTime DMSA fix_eco_timing
Anne Yue, Rajeev Srivastava, - Synapse Design