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SNUG Silicon Valley |
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Santa Clara Convention Center
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Santa Clara, CA
March 26-28, 2012
Join more than 2,000 of your fellow Synopsys technology users for Silicon Valley’s largest technical conference. SNUG features an outstanding program that is focused on delivering practical information you can immediately apply to your current project or use to jumpstart your next design. |
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| | SNUG is committed to making the best possible use of your time and delivering practical information you can take away and apply to your current project as well as future designs. |
| Required Templates | |
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| Dates to Remember |
| September 19, 2011 |
Call for papers opens |
| November 4, 2011 |
Call for papers closes |
| November 7-11, 2011 |
Technical Committee Review |
| November 11, 2011 |
Preliminary acceptance notification |
| December 9, 2011 |
Draft paper due |
| January 13, 2012 |
Final paper due |
| January 20, 2012 |
Final acceptance notification and presentation spots awarded |
| February 20, 2012 |
Draft slides due |
| February 20-March 12, 2012 |
Reminder to practice your presentation |
| March 12, 2012 |
Final slides due |
| March 26-28, 2012 |
SNUG Silicon Valley 2012 | |
| SNUG San Jose
March 28-30, 2011
Conference Schedule | SNUG San Jose 2011 reached a new milestone in the user group’s 21-year history: It was the largest EDA user’s group ever, with 2,375 customer users engaging on a wide range of technical challenges and solutions at the Santa Clara Convention Center. This year’s sessions included in-depth presentations and analyses of a range of technology topics, including IC design and verification, cloud computing, FPGAs, compute and design Infrastructure, system level design, IP and more. We hope to see you at SNUG San Jose 2012. |
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| SNUG San Jose Proceedings | Check out the proceedings library to locate user papers or tutorials that contain solutions you can apply to your own design challenges. View Session Abstracts
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| 1st Place - Best Paper | A Methodology for Creating Reusable Design Blocks Targeting FPGA Devices
Phil Simpson, Jennifer Stephenson [Altera Corp.]
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| 2nd Place - Best Paper Technical Committee Award Honorable Mention | A Case for Adopting Galaxy Constraint Analyzer
Richard Bishop [Advanced Micro Devices, Inc.]
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| 3rd Place - Best Paper | Implementing a High-Speed, Low-Power ARM Cortex A9
Bob Turner [Broadcom Corp.], Nish Balaji [Synopsys, Inc.]
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| Best First-Time Presenter | Implementing JTAG using the CHIPit UMRBus
Gary Gibson [Cray Inc.]
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| Technical Committee Award Honorable Mention | AMD Latch-based Design Methodologies with TetraMAX ATPG
Martin Amodeo, Dwight Elvey [Advanced Micro Devices, Inc.], Aurelia De Colle, Tim Ayres [Synopsys, Inc.]
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| Technical Committee Award | Advanced OCV Timing Derating Experience
Alexander Tetelbaum , Rich Laubhan [LSI Corp.], David Keyser [Synopsys, Inc.]
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| Proceedings | Download 2011 proceedings
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| | The Designer Community Expo is a unique opportunity to meet Synopsys and its design community partners from across the electronics industry. Over 60 companies exhibited in 2011 as users networked with colleagues while enjoying food, drinks and some great prize drawings that were held throughout the evening. |
SNUG thanks the members of the Technical Committee who volunteer their time and expertise to ensure SNUG’s technical quality, local perspective and value to the users of Synopsys tools and technology.
User Technical Chairperson
John Busco, NVIDIA Corp. Technical Committee Members
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Ajay Bavle Microchip Technology
Al Czamara, Test Evolution
Alex Tetelbaum, LSI
Andy Copperhall, ARCH Design
Anwar Hasan, STMicroelectronics
Avishek Panigrahi, Xilinx
Brian Kane, Northrop Grumman Corp.
Chris Kiegle, IBM
Cliff Cummings, Sunburst Design, Inc.
David Flynn, ARM
Don Mills, Microchip Technology
Frank Szorc, Linear Technology
Jack Donovan, SystematIC
John Dickol, Samsung
John Wei, Alchip
Jonah Probell, Consultant
Karthik Rajan, Microchip Technology, Inc. |
Krishna Vittala, Microchip
Leah Clark, Broadcom Corp.
Mark Sprague, AMD
Mike Bartley, Test Verification and Solutions
Neil Johnson, XtremeEDA
Paul Lungu, Ciena
Paul Zimmer, Zimmer Design Services
Priyank Parakh, AMD
Raj Varada, Intel Corp.
Rick Furtner, Consultant
Ron Goodstein, First Shot Logic Simulation & Design
Ronald Kalim, Consultant
Sachin Parikh, Broadcom Corp.
Stu Sutherland, HDL Sutherland
Tom Mahatdejkul, ARM
Victoria Kolesov, Intel
Zafar Hasan, NVIDIA |
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