|Monday, March 26, 2012|
9:00 AM - 10:30 AM
|Critical Mass, Systemic Complexity and Innovation: Catalysts for Designing Change|
Aart de Geus, CEO & Chairman of the Board [Synopsys, Inc.]
In a design ecosystem increasingly influenced by software and systems development, massive verification demands, and the boundaries of physics, engineers have a wonderful new set of problems to solve! Yet the principles they will use to innovate their way to exciting solutions and products remain as fundamental and universal as the reality of the Golden Ratio itself. With the aid of some of these principles, Aart will talk about what new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem complexity that surpasses anything seen yet in human history. View the Keynote
|Monday, March 26, 2012|
11:00 AM - 12:30 PM
|Galaxy RTL: Design Compiler Family Update|
Sal Tiralongo, Erin Hatch [Synopsys, Inc.]
This tutorial presents the latest advancements in the Design Compiler family of products including DC Explorer, Design Compiler Graphical and Formality to help you achieve best-in-class quality-of-results in the shortest possible time. See how you can speed-up the development of high-quality RTL & constrains with DC Explorer for a faster design implementation and generate an early netlist to start physical exploration in IC Compiler even when your design data is incomplete. Learn methodologies to achieve superior design results while streamlining the flow for a faster, more predictable design implementation using physical guidance technology (SPG) in Design Compiler Graphical. Hear about how you can complete verification quickly with Formality equivalence checking without sacrificing quality-of-results.
|IC Compiler Custom Co-Design|
Ed Lechner, Denis Goinard [Synopsys, Inc]
In attending this tutorial you will learn how the IC Compiler Custom Co-Design solution enables design teams to easily move between digital and custom implementation flows, while maintaining design data integrity. The unified solution accelerates the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development, including the time-critical tape-out phase. See how Galaxy Custom Designer, with tight integration to IC Compiler, enables higher productivity through advanced features such as DRC/LVS correct interactive mixed-signal auto-routing and DRC-aware custom editing.
|MA3 User Session: UVM Factories and USB 3.0 Verification|
|The OVM/UVM Factory & Factory Overrides - How They Work - Why They Are Important|
Clifford Cummings [Sunburst Design]
Factory patterns are not new to the software world, and OVM/UVM have incorporated the factory into its primary methodology. But what does the factory really do and why is it important? This paper will explain fundamental details related to the OVM/UVM factory and explain how it works and how overrides facilitate simple modification to the testbench component and transaction structures on a test by test basis. This paper will further demonstrate that OVM/UVM environments can mostly ignore the factory but will explain why the factory should be used.
|Integrating DesignWare USB3.0 Device Controller In a UVM-Based Testbench|
Ning Guo [Paradigm Works]
DesignWare core USB3.0 Controller (DWC_usb3) can be configured as a USB3.0 Device Controller. When verifying a system that comprises a DWC_usb3 Device Controller, the verification environment is responsible for bringing up the DWC_usb3 Device Controller to its proper operation mode to communicate with the USB3.0 Host.
This paper describes the process for configuring and driving the DWC_usb3 Device Controller in a UVM-based verification environment.
Although the UVM-based environment presented in this paper uses specific CPU and external memory interfaces of the DWC_usb3 Device Controller, the flow of the configuration and operation is applicable to the cases when different CPU and external memory interfaces are used. This paper also shows that a UVM-based sub-environment can be setup to make the DWC_usb3 Device Controller integration process more reusable.
|MA4 User Session: Advanced Analysis with HSPICE & CustomSim-VCS|
|Statistical Margin Sensitivity to RNG option for Monte Carlo Simulations with HSPICE|
Tom Mahatdejkul, IngMing Chang, Ling Chein [ARM]
Global Process variation and local device variation continues to have ever greater impact on ARM circuit performance and functionality margins. ARM Designers are often forced to reduce performance targets in order to reign in the tails at the edge of the Gaussian distributions. Design margin sensitivities to Random Number Generator (RNG) settings are presented to help users to determine the appropriate usage of HSPICE for statistical analysis on designs. New quantile feature in HSPICE is used for better qualification of data extremes from Monte Carlo simulation results. HSPICE results for simple RNG settings are applied to ARM margin analysis methodology spanning 20nm to 65nm are presented with usage of new quantile HSPICE feature.
|Universal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure|
Ravi Ram, Warren Anderson, Shyam Sivakumar [Advanced Micro Devices, Inc.], Vijay Akkaraju [Synopsys, Inc.]
This paper describes application of RTL verification methodology in analog mixed-signal designs. Given the increasing complexity of these circuits, it is important to increase the volume and variance in stimulus to ensure functional correctness. Because lengthy run times of SPICE-based simulations are a significant bottleneck and Verilog only models are non-analog, alternative flows are needed. Our approach takes a granular representation of low-level analog blocks in Verilog-AMS and builds circuits that can be instanced in a System Verilog test bench for mixed-signal simulations through VCS and CustomSim. We achieved more than an order of magnitude decrease in simulation time.
|MA6 User & Tutorial Session: Signoff-Driven Design Closure|
|PrimeTime DMSA ECO Fix: a Case Study|
Bo Gao, Khoan Truong, Shankar N, Hong Chen [Cypress Semiconductor]
PrimeTime DMSA provides an efficient environment to manage and analyze large number of timing signoff scenarios in a distributed server farm. PrimeTime 2011.06 DMSA Signoff-Driven ECO Guidance technology is evaluated on a design where prior versions of Prime Time were not able to find ECO solutions to timing violations. The design in this case study has a complex configurable IO matrix supporting 27 IO modes. The total number of timing signoff scenarios expands to 108 with PVT and RC corners. The Signoff-Driven ECO Guidance technology shows significant improvement in performance and timing fix rate in this case study. This paper will present the results of this case study. Current limitations and future improvements to PrimeTime will also be discussed.
|ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing|
Vivek Ghante [Synopsys, Inc]
PrimeTime’s 2011.12 release extends the production-proven ECO technology from earlier releases to multiple new areas of design rule constraint (DRC) fixing. Together, PrimeTime ECO enables you to perform ECO fixing for timing and DRC across multiple scenarios in parallel using CPU resources efficiently from your compute environment. New enhancements in DRC fixing include trade-offs for timing costs and a flexible approach to utilizing compute resources for multi-scenario fixing. This tutorial is for designers responsible for timing convergence and signoff and will show how users are effectively using PrimeTime’s ECO solution with the latest ICC flows.
|Monday, March 26, 2012|
12:30 PM - 1:45 PM
|Lunch and Learn|
|Leading Semiconductor Companies Discuss Move from In-Design to Signoff with IC Validator|
Ed Roseboom [AMD], Ryoji Ishikawa [Renesas], Kiyohito Mukai [Panasonic], Atsuhiko Ikeuchi [Toshiba], Julia Lau [Infineon]
Learn from industry experts at leading semiconductor companies how success with In-Design has led them to adopt IC Validator for signoff DRC, LVS and Double Patterning at leading edge nodes. IC Validator’s physical verification suite is a complete signoff solution with proven success at the most advanced process technologies. IC Validator is supported for all production nodes at 40nm and below by leading foundries including TSMC and ISDA/Common Platform.
Target Audience: Back-end, physical design engineers, physical verification engineers, project leads, physical design, physical verification and CAD team managers.
|Monday, March 26, 2012|
1:45 PM - 3:15 PM
|MB1 User Session: Design Correlation|
|Improving Virtual Route Correlation on Advanced Process Nodes|
The conventional challenges of Automatic Place and Route (APR) - Optimizing Quality of Results (QoR), obtaining reasonable correlation of timing paths between pre- and post-route, and minimizing the number of redundant inverters and buffers in the design – increase in complexity with each new process node on a smaller geometry. Place and route engines are no longer able to find optimal solutions without substantial guidance. In this paper, we review the process trends that contribute to this challenge, and present various techniques available to the designer and new capabilities in APR tools to guide the tools to overcome these challenges.
|The Impact of Correlation on Design Quality, Design Closure Loops, and Design Turn Around Time|
Modern SoC designs use advanced EDA and innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at leading-edge process nodes though the design convergence cycle has been slowing and elongating. Many constraints and complexities accompanied the sub-20nm process, such as parasitics, crosstalk effects and non-linear behavior that have greater effects on smaller discrepancies. But another major contributor is the correlation between design and verification engines as well as across all design phases, increasingly impacting design closure loops (effort) and overall RTL to Physical Layout TAT (schedule). We present our efforts to reduce the these correlation gaps.
|Accelerating Manufacturing Closure at 28nm and below with IC Validator and In-Design Technology|
Ron Duncan [Synopsys, Inc.]
At leading geometries, lithography has become extremely difficult as feature sizes are produced at a fraction of the illumination wavelength. Managing density of material becomes crucial for improving planarity of wafers and ensuring adequate lithographic margin. Late detection of issues too often leads to unpredictable design iterations and tapeout delays.
In this tutorial, we will discuss manufacturing challenges at leading geometries driving the need for more effective design solutions. Attendees will learn how in-design technology with IC Validator and new capabilities, such as Pattern Matching and Fill-to-Target, are enabling faster manufacturing closure – all within IC Compiler.
|MB3 User Session: Minimizing RTL-to-Netlist Simulations Mismatches|
|X-Propagation: An Alternative to Gate Level Simulation|
Adrian Evans, Julius Yam, Craig Forward
Gate simulations are onerous and many of the risks targeted by gate simulation can be mitigated by RTL lint, static timing and logic equivalence tools. One risk that remains, is the potential for optimism in the X semantics of RTL simulation. VCS X-Prop is a new feature in VCS which attempts to more accurately model X behaviour at the RTL level. In this paper, we review the behaviour of Xs in simulation and then describe our experience using VCS X-Prop on a large design. We conclude by proposing how VCS X-Prop can be used to reduce gate-level simulations.
|Yet Another Latch and Gotchas Paper|
Don Mills [Microchip Technology, Inc.]
Unique Case and Priority Case were added to the SystemVerilog language to alert designers of potential latch conditions. These constructs provide built in assertions that can indicate potential latch generation. This paper will explore these constructs and explain where they break down. The paper will also show solutions that will always work to prevent latches. This paper will also present updated solutions for the SRFF model that simulate one way but synthesize into a different design. Finally, this paper will discuss and clarify the use the “logic“ key word as is specified in the IEEE 1800-2009 standard.
|MB4 User & Tutorial Session: Testability for Custom Logic & 28nm Cell Characterization Challenges|
|Enabling DFT Logic and Timing Verification in Mixed-Signal Designs with XA & VCS Cosim|
Bing Chuang [Rambus], Sumit Vishwakarma [Synopsys, Inc.]
The majority of today's designs contain significant analog and mixed-signal content. Even SoCs that are designed for essentially digital functions still require PLLs for timing control, digitally-controlled power management circuits, and high-speed I/O devices. In this paper we discuss how we used Synopsys analog/digital co-simulation methodology to complete DFT logic and timing verification of mixed-signal designs that contain digital place-and-route, custom digital and analog circuits.
|Standard Cell Library Characterization Flow using Liberty-NCX and HSPICE|
Sheela Shreedharan [Synopsys, Inc.]
This tutorial provides an overview of the advanced characterization, modeling and validation system deployed in Synopsys, for development of highly-accurate library models in 28nm and smaller geometries. The flow supports SPICE models provided by most foundries. Characterization flow uses Liberty-NCX with HSPICE embedded within, for foundry-certified, highly-accurate SPICE simulation. Characterization is done using a Makefile-based automated system, for quick and accurate development of CCS, ECSM & NLDM models with features that support complex design flow requirements such as CCS Scaling and MCMM. The flow ensures robust characterization turnaround time for all PVTs corners. Quality assurance flow includes syntax check, accuracy checks, consistency checks, trend checks, equivalence check and methodology checks.
Target audience: Analog/mixed-signal design engineers, CAD managers & engineering managers.
|Design Reliability Challenges for 28nm and Beyond|
Meera Srinivasan [Synopsys, Inc.]
Small (28nm and below) geometries combined with core voltage as low as 0.85V and high data rates (Gigabit transceivers) are making FPGA designs more susceptible to influences of process variation, natural radiation and noise. The possibility of design failures due to radiation and SEUs is no longer an issue confined to avionics/space applications but is also an important consideration in diverse FPGA applications in automotive, communications, finance, medical, military (defense), networking and other industries. This tutorial will cover the basics of how faults occur, the types of mitigations techniques available and what Synplify Premier can do to help designers with their high reliability requirements. The tutorial will also provide guidance on which techniques to apply taking cost/area and timing requirements into consideration based on the various application segments.
Target audience: Informative session for Engineers/Managers to understand the basics of error detection and correction techniques and for Synplify Pro/Premier users designing FPGAs with high reliability for smaller geometries.
|Monday, March 26, 2012|
3:45 PM - 5:15 PM
|MC1 Tutorial Session: Design Correlation and Flipchip Package Design|
|Intelligent and Automated Layer-Aware Pre-Route Optimization for Improved Post-Route Correlation for Advanced Technology Nodes|
Shoukyou Wang, Changge Qiao [Synopsys, Inc.]
At 28nm and below, wire resistance varies significantly across routing layers. Layer average pre-route parasitic estimation is too pessimistic for long nets which lead to over buffering and poorer post-route correlation. In this tutorial, we shall describe the use of net patterns and layer-awareness throughout the implementation flow for more accurate pre-route parasitic estimation that avoids over buffering and results in tighter post-route correlation.
|A Chip-Package Design Flow Using Zuken and Synopsys Tools|
Kazunari Koga [Zuken], Frank Malloy [Synopsys, Inc.]
The transition from traditional wirebonding technologies to flip-chip packaging is being driven by growing design I/O complexity and performance. While flip-chip packages enable very high I/O counts, successfully integrating the chip and package technology presents the design team with new challenges. This tutorial will demonstrate IC Compiler’s built-in design planning capabilities in concert with Zuken’s package design tool. Together, they can help you create a package-friendly flip-chip floorplan and design the package and a prototype – ultimately leading to reduced integration time and avoided package-chip design iterations.
|MC2 Usertorial Session: IC Validator|
|Enabling DRC+ Pattern-Based Physical Verification with IC Compiler and IC Validator|
Luigi Capodieci [GLOBALFOUNDRIES]
At the geometrical scaling limits of the semiconductor IC roadmap, traditional design rules, which define constraints on linear dimensions for physical design layouts, are not sufficient to guarantee manufacturability and yield. DRC+ is a novel verification methodology, introduced by GLOBALFOUNDRIES, for augmenting traditional DRC with two-dimensional multi-shape based pattern-matching. This presentation will discuss physical design and manufacturing challenges at advanced nodes and highlight key aspects of DRC+ vs. traditional design flows. Our new design flow architecture will illustrate how DRC+ pattern-based verification is fully supported by IC Validator‘s ultra-fast Pattern Matching engine and seamless integration with IC Compiler.
|Optimizing Design Fill at 28nm and below using In-Design Physical Verification with IC Validator|
Norma Rodriguez [Advanced Micro Devices]
IC designers are familiar with metal fill as a requirement for improving the planarity of wafers and die and enhancing overall lithographic error margin. In this session, we will discuss manufacturing challenges driving the need for more sophisticated analysis and intelligent shape insertion during the fill process. Attendees will learn how in-design physical verification with IC Validator makes it possible for AMD engineers to insert foundry quality fill earlier in the design cycle, improving turnaround time. We will present how new Fill-to-Target (FTT) technology can be used to manage constraints at leading geometries, along with observed benefits at AMD.
|MC3 User Session: Enhancing Self-Checking Testbenches|
|Snooping to Enhance Verification in a VMM Environment|
Joseph Manzella [LSI Corp]
In an ideal world, a verification environment will be independent of the RTL coding; however, situations often arise where this ideal cannot be met. This paper discusses situations in which a verification environment may have to peek at internal RTL states and signals to enhance results, and provides guidelines of what is acceptable practice.
|A Unified Self-Check Infrastructure - A Standardized Approach for Creating the Self-Check Block of Any Verification Environment|
John Sotiropoulos, Matt Muresan, Massi Corba [Draper Laboratories]
This paper presents a structured approach for developing a centralized Self-Check block for a verification environment. The approach is flexible enough to work with various testbench architectures and is portable across different verification methodologies. Under this solution, all of the design’s responses are encapsulated under a common base class, providing a single Self-Check interface for any checking that needs to be performed. This abstraction, combined with a single centralized scoreboard and a standardized set of components, provides the consistency needed for faster development and easier code maintenance.
|How to Get the Most from Your Circuit Simulation|
Szekit Chan, Tom Hsieh [Synopsys, Inc.]
Do you ever
* Wonder what the latest news is for Synopsys Custom and AMS solution? * Wish you had insight into the latest advances in HSPICE & CustomSim solutions? * Want to know how to get the best performance out of your circuit simulator?
This tutorial provides useful tips and tricks to reduce simulation time without compromising accuracy. Starting with HSPICE, the tutorial will cover tuning for better performance using the Runlvl command, convergence, RC reduction and other good practices. Then, for CustomSim (XA), we’ll reveal performance and ease of use enhancements targeted for simulation of memory designs.
Target audience: Analog/mixed-signal design engineers, CAD managers & engineering managers.
|MC5 User Session: FPGA Design|
|Efficient FPGA Implementation of Microprogram Control Unit Based FIR Filter using Xilinx and Synopsys Tools|
Syed Manzoor Qasim, Mohammed Sulaiman BenSaleh, Abdulfattah Mohammad Obeid [King Abdulaziz City for Science and Technology]
Finite impulse response (FIR) filter is one of the most common type of digital filter used in digital signal processing (DSP) applications. Field Programmable Gate Arrays (FPGAs) have been widely used for the implementation of digital FIR filters using different techniques. However, in this paper, we used Microprogram Control Unit (MCU) to orchestrate the operation of the FIR filter. To demonstrate the proposed technique, parallel and serial architecture of 4-tap FIR filters are presented. The architectures are implemented in Virtex-5 FPGA using Xilinx® ISE and Synopsys® Synplify pro tool and the performance is analyzed by evaluating the FPGA resource utilization.
|MC6 Tutorial Session: Static Timing Technology|
|Performance and Productivity Improvements in PrimeTime 2011 Releases|
Jayant Joglekar [Synopsys, Inc.]
The performance and productivity improvements in PrimeTime 2011 releases enable users to address signoff challenges more efficiently. This tutorial will cover new capabilities, including best usage methodology to take advantage of improved runtime and ease-of-use in debugging timing issues. The topics presented are suitable for all users of PrimeTime.
|Galaxy Constraints Analyzer: Comparing Multiple SDC Constraints Files|
Lionel Corbet [Synopsys, Inc.]
Today’s SoC designs are extremely complex with tight design schedules. Any change to timing constraints can have a significant impact on timing results and time to tapeout. This tutorial will demonstrate how to quickly debug constraints changes and identify discrepancies using Galaxy Constraint Analyzer. After providing some background information on the technology, we will demonstrate how to analyze the differences between two SDC files for unintended behavior changes.
The tutorial is for design implementation engineers and managers looking for a solution to drastically reduce the time needed to provide clean constraint definitions.
|MC7 User & Tutorial Session: UVM for ESL and HLS for Multi-Rate Communication Designs|
|Does UVM make sense for ESL?|
David C Black [Doulos Inc.]
The Universal Verification Methodology is a huge win for the Hardware Verification community, but does it have anything to offer Electronic System Level design? This paper explores the potential behind using UVM with ESL. Benefits exist for hardware verification, software design, and importantly architectural design. The paper considers UVM and SystemVerilog enhancements that could make the proposal even more enticing.
|Using High-Level Synthesis to Streamline ASIC Multi-Rate Communications Design|
Doug Johnson [Synopsys, Inc.]
Many communications systems use multiple sample rates in their signal processing paths. It can be challenging to efficiently implement these algorithms in ASIC or FPGAs because of the complexity in supporting multiple clock domains and because of the many architectural tradeoffs between area, speed, and power that can exploit the multiple sample rates in the design. This tutorial shows how high-level synthesis optimizations can be used to more easily create efficient hardware architectures and also explore tradeoffs while keeping the multi-rate algorithm development simple. Wireless communications designs for FPGA and ASIC will be used to illustrate the concepts.
|Tuesday, March 27, 2012|
9:00 AM - 10:00 AM
|Partnering for Low Power|
John Cornish, Executive VP [ARM]
To fully exploit the next generation of process technology, a system approach to low power is needed. The challenge is to avoid 'dark silicon’ which is prohibitively expensive to 'light up' from an energy point of view. To mitigate this, all aspects of system design have to be optimized, even though each may only make a small contribution to energy efficiency. What matters is the product of all of these improvements, from transistor level through SoC architecture and up in to the software stack. By working in partnership, engineers from across the industry can apply new techniques to reduce power in all parts of the system. This presentation will describe work ARM is doing in physical IP, interconnect, and processor sub-systems to enable energy efficient systems. It will also discuss the importance of system profiling and analysis, and definition of new industry standards. View the Keynote
|Tuesday, March 27, 2012|
10:30 AM - 12:00 PM
|TA1 User Session: Low Power Design|
|PCIe Power-Gating Implementation Using Synopsys Low-Power Tool Flow|
Jason Tan, Santosh Singh, Kedar Kulkarni, Anand Iyer [Advanced Micro Devices, Inc.]
We implemented power gating with the IEEE 1801 UPF standard using Design Compiler (DC) and IC Compiler (ICC) for a high-performance PCIe® controller design. Some of the new templates available in ICC were used to implement a daisy chain-based power switch stitching. We also applied some of the best practices to designing power-gating designs. This paper will discuss in detail the implementation and approaches used to design power gating in our high-performance PCIe® controller design.
|An ARM Cortex-M0 for Energy Harvesting Systems: A Novel Application of UPF with Synopsys’ Galaxy Platform|
Jatin Mistry [University of Southampton], James Myers [ARM Ltd.]
In energy harvesting systems, energy is effectively infinite but output power is severely limited. In this paper we first present a novel state retention power gating technique, called Sub-Clock Power Gating, which addresses this ultra-low power budget. It works in synergy with voltage and frequency scaling and power gates combinational logic within the clock cycle to reduce active power. Secondly, we describe how the technique was implemented on an ARM Cortex-M0™ microprocessor for fabrication and discuss our experience of using UPF with Synopsys' Galaxy Platform to achieve the required power gating. Finally, silicon measured results are given.
|TA2 Vision & Tutorial Session: Advanced Design Integration – 2.5DIC and 3DIC|
|A Silicon Interposer-Based 2.5D-IC Design Flow - Going 3D by Evolution Rather Than by Revolution|
Michael Jackson [Synopsys, Inc.]
While the entire industry is working hard to sort out the manufacturability, cost, and heat/power issues of full 3D-IC integration, there is an intermediate step well within our reach. In his talk, Dr. Jackson will present a silicon interposer-based 2.5D-IC design flow that Synopsys is working on. The proposed solution, developed in close collaboration with Synopsys semiconductor partners, represents the first, evolutionary step towards 3D-IC integration and addresses the implementation and verification aspects of the 2.5D-IC integration flow, yet proposing what the next steps might be.
|TA3 User Session: UVM RAL and Solution for X Propagation|
|Easier RAL: All You Need to Know To Use the UVM Register Abstraction Layer|
Doug Smith [Doulos]
UVM provides the framework to create register models referred to as the register abstraction layer (RAL). Describing a register model can be quite tedious and rather burdensome to maintain; hence, the need for an Easier RAL. In this paper, UVM RAL concepts like register blocks, address maps, adaptors, predictors, front-door/backdoor access, built-in sequences, and register coverage are explained. Likewise, the use of free register generators is shown. Using generators to build and maintain the register model along with some simple guidelines for integration, provides the essential knowhow to quickly and effectively benefit from UVM’s Register Abstraction Layer.
|X-Optimism Elimination during RTL Verification|
Robert Booth [Freescale], Bruce Greene, Arturo Salz [Synopsys, Inc.]
Verification of complex chips suffers from X-optimism issues that often conceal design bugs. The deployment of lower power techniques such as power-shutdown in today’s designs exacerbate these X-optimism issues. To address these problems we used a new simulation semantic that more accurately models non-deterministic values in logic simulation. In this paper we discuss how X-optimism can be eliminated during RTL verification. We also present results from a recent project.
|TA5 User & Tutorial Session: FPGA Prototyping|
|Slow Dancing with Memories - Sometimes it's Harder to Go Slow|
Manoj Agarwal [SanDisk], David Castle [Synopsys, Inc.]
Usually we try to make FPGA rapid prototyping run as fast as possible, but sometimes it needs to go slow, and sometimes this can be a real problem. For a design that is supposed to run at 800 MHz and supposed to interface with SDRAM at 667 MHz, to run in an FPGA at 25 MHz and interface with memory at 50 MHz, seems impossible. This is way below manufacturer's minimum operating frequency specifications. This is way below normal PHY operating frequencies. But, it can be done! This paper presents a cookbook approach to making it work and includes a simple reference design that proves it is possible.
|Determining Optimal FPGA System Connectivity|
Joseph Marceno [Synopsys, Inc.]
Configurable FPGA-based prototyping systems offer great flexibility and portability. However, each design imposes unique connectivity requirements. This tutorial focuses on how to determine the appropriate optimal FPGA connectivity for a HAPS system and pass the correct hardware model to Certify, the partitioning software.
Target audience: FPGA-based prototyping managers and engineers, HAPS and Certify users of all experience levels looking to improve multi-FPGA prototype bring up time.
|TA6 User Session: MultiVoltage and Low Power Analysis Technologies|
|28nm ETM Generation with Multi-voltage Domain(UPF compliant) and Embedded IO|
Anne Yue, Bill Griesbach, WeiMun Chu [LSI Corp]
HardMacro Extracted Timing Model (ETM) is one of the major deliverables for SOC level applications. About 70% of LSI DDR Physical Interface (PHY) HardMacros are used with multi-voltage domains and embedded IO, which introduce issues not covered by native Synopsys ETM generation tools. This paper addresses the issues and solutions for Unified Power Format (UPF) flow support & multi-voltage domains inside DDR IP as well as Pad/IO attributes and VREF in ETM. This paper also discusses how to verify ETMs, and how to use ETMs at the SOC level.
|Early Leakage Power Estimation for Use Cases Across PVT|
Hwisung Jung [Broadcom Corp.]
With the increasing demand for mobile applications in today’s mobile devices, extending battery life has become a daunting, yet vital task. Typically mobile devices spend most of time in idle mode, where leakage power is a significant contributor to battery life. In this paper, we present an early leakage power estimation methodology with Synopsys Primetime-PX to estimate leak-age power across process, voltage, and temperature (PVT). Specifically, our scaling factors-based leakage estimation technique captures leakage change behaviour across PVT precisely for every type of cell in a library, which results in great accuracy in estimating leakage power com-pared to silicon measurements.
|TA7 User Session: Designing Custom Processors as an Alternative to Fixed HW Blocks|
|Programmable Accelerator for a Mobile SoC|
Christopher K Wolf [Audience, Inc.]
This case study will review the analysis, justification, and implementation metrics for a custom programmable accelerator that significantly improves the power consumption of a System on Chip (SoC) used in mobile devices. After a brief overview of the SoC hardware, an analysis will identify key software functions and accompanying power reductions if a hardware accelerator is included. A comparison of design methodologies for hardware accelerators will be presented. Finally, metrics from three projects will demonstrate that using a custom processor creation tool such as Synopsys Processor Designer can improve development productivity while lowering technical risk.
|Deploying Processor Designer for a Custom Super Scalar Processor for Software Defined Radio|
Makoto Mouri [Fujitsu]
A Software Defined Radio (SDR) enables support for multiple and evolving wireless communication standards. In this paper we discuss how to use a model based design flow to create a three-way super scalar custom processor that has branch prediction unit and special instructions with seven stage pipeline for such an SDR. The overall design period took only seven months despite the complexity of the processor architecture. In this period, we also generated the RTL from a high level processor description and completed the RTL verification and lint tool checking to achieve production quality. The resulting synthesized RTL achieved a performance of 250 MHz with an area of 172k gates. Besides reducing the design time, the advantage of using a processor design tool is the generation of the software tool chain for the resulting processor as we will explain in this paper.
|Tuesday, March 27, 2012|
12:00 PM - 1:15 PM
|Lunch and Learn|
|Managing Power Intent on Hierarchical Designs using UPF with the Lynx Design System|
Most system-on-chips have to address power consumption and dissipation whether the design is targeted for a desktop or a mobile application. However increased product performance and functionality with each new product generation is making minimizing for power dissipation increasingly difficult. In this presentation, we will demonstrate the silicon-proven methodologies within the Lynx Design System to manage power consumption on a hierarchical design. We will walk through some of the key steps in implementing and analyzing a hierarchical design containing UPF for both bottom-up and top-down flows based on Synopsys' Galaxy Implementation Platform. You will also hear how your peers are using advanced visualization capabilities to track progress towards achieving power goals.
|Your Peers are Benefiting from Latest Design Compiler Technologies, Are You?|
John Busco [NVIDIA], Bob Turner [Broadcom], Ed Bender [AMD], Eyal Odiz [Synopsys]
Join us for this special lunch event to see how recent advances in Design Compiler are helping your peers complete their complex, demanding designs faster than ever before. Panelists will discuss how DC Explorer helps them develop high-quality data for a faster implementation while Design Compiler Graphical helps them tackle their toughest design targets. See how the combination of DC Explorer & Design Compiler Graphical is helping your colleagues get a head start on physical exploration and achieve a predictable RTL-to-GDSII flow.
Target audience: RTL design, CAD and physical design engineers/managers.
|Tuesday, March 27, 2012|
1:15 PM - 2:45 PM
|TB1 User & Tutorial Session: Automated Design Planning and Design Closure|
|Hippo Lake: A Case Study of Automated Design Planning in High Speed Designs|
Automated design planning solutions bring efficiency to full chip floorplanning, assembly, and integration. High speed designs represent a unique set of challenges: Stringent timing, power and quality specs require many iterations for fine grained optimization, including hand-crafted optimal port placements, routing topologies, and buffering solutions. Can automated design planning tools achieve a similar level of TAT here as ASIC design without compromising on frequency, power and quality? We examine how the latest advances in EDA capabilities such a x-boundary timing optimization, and relative placement for block/top level co-design, can be used to implement a production high speed CPU design.
|Faster Top Level Closure With Transparent Interface Optimization (TIO)|
Radhika Shankar [Synopsys, Inc.]
Transparent Interface Optimization (TIO) in IC Compiler is a new capability that addresses the challenges of gigascale design and enables faster top-level closure. This tutorial will provide designers technical information on TIO, its usage, current capabilities and roadmap.
Target audience: Design and CAD engineers and managers responsible for physical implementation and verification.
|TB3 User Session: Simultaneous C/Assembly/RTL Debug with DVE & SimpleTest Writer Interface with SystemVerilog|
|Integrated RTL and Software Code Debugger in DVE for Verification of an ARM-Based SoC|
Noumaan Shah [Broadcom Corp.]
This paper describes the typical difficulties encountered during the debug phase of embedded processor System-on-Chip (SoC) development. The paper goes on to explain a solution de-ployed inside the Synopsys® Discovery Visualization Environment (DVE) that significantly shortens the debug process. This paper also discusses how the solution was deployed and a re-view of the user experience. The paper closes out with suggestions on improvements, which are forthcoming in the next release of this solution from Synopsys.
|Mechanism to Allow Easy Writing of Test Cases in a SystemVerilog Verification Environment, Then Auto-Expand Coverage of the Test Case|
Ninad Huilgol [VerifySys]
In a verification project involving an environment built with VMM or UVM, many times, one finds that the design engineers, who aren?t verification experts, are fearful of using a class based environment. Moreover, the directed test cases they might write need to be converted into scenarios with constraints, in order to use the power of a constrained random test bench. To address this issue, a tool was created, using Synopsys VMM, to automatically expand the scope of the original test to cover a larger verification space, based on a user friendly API that looks like Verilog, hiding the complexity underneath.
|TB5 User & Tutorial Session: FPGA Prototyping|
|Functional Coverage for FPGA Prototype Validation Offers a New Verification Paradigm|
This paper describes a methodology for an FPGA prototype to achieve software like SystemVerilog functional coverage with all the performance and benefits one would expect from a Silicon prototype. It defines the use of SystemVerilog coverage assertion synthesis and a method to connect coverage assertions to a host machine for real time and post processing. New features such as XMR synthesis support, SystemVerilog coverage synthesis, and a SCE-MI based host interface make this methodology a reality. It opens up a new verification space that allows gathering coverage metrics with the use of in-circuit stimulus, and real time software, while reaching hard-to-hit deep state sequences that are not measurable in any traditional solution.
|Effective Strategies for Bringing Up and Debugging an FPGA-Based Prototype|
Nathan Henderson [Synopsys, Inc.]
Timely achievement of functional prototype can be a difficult and imposing task. Each stage of design bring-up imposes unique requirements and challenges. This tutorial will focus on how to ease the bring-up and debug process by (a) defining the goals and requirements of each bring-up phase and (b) demonstrating the corresponding bring up and debug techniques that best meet the requirements. Target audience: Current or potential FPGA-based prototypers looking for efficient ways to debug their platform.
|TB6 Tutorial Session: Parasitic Extraction for Emerging Technologies|
|Dealing with Metal Fill in 28nm ECO Extraction Flows|
Vishal Kedia [Synopsys, Inc.]
Design teams are facing increased schedule and tapeout pressures due to the increasing ECO time to close their complex system-on-chip designs. The situation is exacerbated at 28-nm as metal fill insertion has become a must-have step in IC design. Designers use physical verification tools to insert sign-off metal fill. Metal fill insertion and post metal fill extraction runtimes are critically important in overall ECO turnaround-time (TAT) and reducing them can accelerate the signoff analysis. This tutorial discusses new ways to reduce metal fill insertion run time and metal fill handling in StarRC to significantly improve ECO TAT.
|Double-Patterning Aware Extraction and Timing Signoff at 20nm|
Baribrata Biswas [Synopsys, Inc.]
Double patterning technology (DPT) has become an impending reality at advanced 20-nm and below process nodes. DPT provides an attractive alternative to more expensive lithography options, but it introduces new challenges in parasitic extraction and timing signoff analysis due to increased variation. This tutorial provides an overview of the double patterning technology and discusses StarRC’s latest parasitic modeling and extraction features to help designers signoff their 20-nm designs with increased confidence as before.
|How do FinFETs Impact Parasitic Modeling and Extraction?|
Baribrata Biswas [Synopsys, Inc.]
The emergence of FinFET or Multi-gate field effect transistors (MuGFETs) ushers in a new era of CMOS process scaling. The non-planar FinFET transistors provide higher performance and lower leakage but significantly change the flows from circuit design to simulation. This tutorial discusses the motivation behind FinFETs and how Synopsys is driving the collaboration with major foundries to enable next-generation designs. It describes StarRC’s advanced 3D process modeling as well as extraction solutions for cell characterization and signoff analysis of designs using FinFETs.
|TB7 User Session: Early SoC Architecture Performance Analysis|
|SoC Architecture/ Performance Modeling using SystemC/TLM 2.0, a Case Study using Synopsys Platform Architect|
Ali Poursepanj [LSI Corp.], Anthony Fama [Synopsys, Inc.]
SystemC/TLM2.0 has attracted a number of SoC design companies for architecture and software modeling in the recent years. Developing architecture models at an early stage of the design cycle and re-using them for software and verification reference models can increase productivity and reduce product development time. One of the challenges in architecture analysis is modeling the application workload with reasonable accuracy during the architecture exploration and design trade-off analysis. Synopsys Platform Architect allows modeling of hardware topologies and application workloads using a SystemC-based platform. This presentation discusses some of the basics of SoC modeling, and presents a case study for architecture analysis using Synopsys Platform Architect.
|Architecture Analysis of a Multi-Mode Base-Station Chipset|
Dr. Andrea Kroll, Qiang Wang [Futurewei Technologies, Inc.]
Complex processing, dynamic multi-user scenarios, complex system architecture with many DSP cores, HW accelerators, clustered interconnects as well as hard latency constraints are the challenges we face in today’s multi-core chip design for multi-mode base-station base band chipsets. This paper presents our experience using Synopsys Platform Architect MCO for a next-generation base station design. Traditional spreadsheets cannot reliably predict performance and utilization for these systems. The new flow uses a task graph to capture application parallelism, synchronization, process timing. We show how to create an architecture model and then map the task graph for analysis. Latency is measured under different user scenarios and architecture choices. The focus of this paper is on:
- Model the workload of a complex multi-user application scenario for a many-core SoC
- Optimize a many core architecture with hierarchical interconnect
- Deal with many-core architecture challenges like partitioning, load balancing, and synchronization
|Tuesday, March 27, 2012|
3:15 PM - 5:15 PM
|TC1 Tutorial & Panel Session: Optimized Implementation for High Performance Cores|
|Techniques for High Performance Cores using Synopsys Galaxy Platform-ARM® Cortex-A15 Case Study|
Daniel Biset, Man-Fai Shek [Synopsys, Inc.]
Learn how to predictably achieve high performance while minimizing power. We will present an optimized implementation methodology for an ARM Cortex™-A15 processor core based on Synopsys’ Galaxy™ Implementation platform. This session will highlight the latest technologies/techniques in Design Compiler and IC Compiler used to achieve challenging performance/power targets. These include physical guidance, delay performance vs. area tradeoffs, leakage optimization, innovative methods to reduce slack across register stages during final timing closure, and more. We will examine benefit/cost tradeoffs of each technique; performance/ease of convergence and impact on schedule/turnaround time. We will also share results obtained using this combination of optimized methodology, tools and physical IP.
|TC2 User Session: Clock Tree Design|
|Gater Expansion with a Fixed Number of Levels to Minimize Skew|
David Chinnery, Shitanshu Tiwari, Peter Osler, Michael Scott, Hai Vo-Ba [AMD], Ron Halliwell [Synopsys, Inc]
Automatic insertion of clock distribution logic to achieve low skew in high frequency digital designs faces many difficulties. Decisions on using a clock mesh or tree, restricting the number of clock tree levels to reduce skew, and gater and flop placement constraints, must be made early in the design process.
These decisions greatly impact the quality of results, but the trade-offs are difficult to analyze accurately. Steiner tree wire load estimates are increasingly inaccurate, necessitating routing congestion-aware timing analysis.
AMD and Synopsys collaborated on a new placement restriction aware clock tree splitting command that significantly reduces clock skew and power.
|TC3 Tutorial: ARM AMBA 4 ACE VIP and Low-Power Simulation Debug|
|Achieving Rapid Verification Convergence with ARM(R) AMBA(R) 4 ACE(TM) VIP|
Tushar Mattu [Synopsys, Inc.]
Over the last couple of years, new interface protocols have been added to the ARM AMBA standard, including the AXI Coherency Extensions (ACE) for system-level cache coherency across multicore processors in SoC designs. Traditionally, cache coherency management has largely been performed in software, adding to the software complexity and development time. With AMBA 4 ACE, system level coherency is performed in hardware, providing better performance and power efficiency for complex SoC designs. This additional capability increases the complexity of functional verification for such complex designs. In this tutorial, you will learn how the latest generation AMBA AXI Verification IP (VIP) from Synopsys can help accelerate and simplify the adoption of the ACE protocol.
Target audience: Design & verification engineers and managers.
|Debugging Low-Power Simulations|
Ajay Thiriveedhi [Synopsys, Inc.]
Low power designs are complex to verify and very time consuming to debug. Shortening the debug time for low power simulations helps to increase overall verification productivity. With the help of examples, this session will cover the common failure signature of low-power simulations and recommended approach on how to debug typical failed low-power simulations. The goal of this session is to provide users an introduction on debugging LP simulations.
Target audience: Basic familiarity with low-power simulations and UPF.
|Test Updates, Yield Improvement, and the Importance of Standards|
Adam Cron Yervant Zorian, John Kirkland [Synopsys, Inc.]
This tutorial will provide the latest updates to DFTMAX Compression, STAR Memory System, TetraMAX ATPG and Yield Explorer. We will highlight how adding physical attributes improves yield and diagnostics debug, and the importance of standards in facilitating various process methodologies. Examples of characterization and debug using simple IEEE Std 1149.1 access will be shown.
|TC5 User & Tutorial Session: FPGA Design|
|Unleashing the Power of the Command-Line Interface|
Jeremy Webb [Centellax, Inc.]
The development of complex ASIC or FPGA designs involving multiple teams and loosely integrated tools is an arduous process. There is an inherent challenge in maintaining coherency and separation of source and generated files throughout the build process, particularly through different tool versions and vendors. These aspects of the development process make results hard to reproduce, reuse, and share. This paper highlights the benefits of a command-line-based build environment as an alternative to using graphical user interfaces (GUIs) for RTL development. A well-reasoned directory structure for projects is proposed, as well as a template for command-line integration of ASIC or FPGA development tools.
|Solving P&R Challenges on High Density Xilinx FPGAs|
Chris Dunlap [Xilinx]
Proper constraining of FPGA place & route tools is crucial for solving implementation challenges, thereby enabling faster bringup. This Xilinx tutorial will cover methods of solving both area and timing problems as well as discuss the implication of common implementation errors during place & route. Target audience: FPGA designers and managers, HAPS, Xilinx FPGA and Synplify Pro/Premier users of all experience levels.
|TC6 Tutorial Session: Signoff using Formal Equivalence Checking|
|Formality Low Power Equivalence Checking with UPF|
Erin Hatch [Synopsys, Inc.]
This tutorial presents advanced topics associated with low-power equivalence checking using UPF. Learn information and techniques that help you understand and efficiently debug low-power UPF verifications in Formality. See how you can provide the required setup to obtain a complete verification that covers all power states. Hear about common issues that may be encountered during low-power verification and how you can easily resolve them.
Target audience: Formal equivalence checking users of low-power designs.
|ESP Memory Redundancy Verification|
Dave Hedges [Synopsys, Inc.]
ESP-CV uses symbolic simulation to verify Verilog and SPICE designs, usually in an equivalence checking context. This tutorial gives a quick introduction to ESP-CV and how recent redundancy verification features are used to verify various types of redundancy circuitry used in full-custom or compiler memory blocks.
Target audience: Full-custom or compiler memory block designers.
|TC7 Tutorial: Enabling Early Software Development for ARM-Based Designs|
|Developing Software for ARM big.LITTLE Based Designs Running Android|
Robert Kaye [ARM], Tom De Schutter [Synopsys, Inc.]
As devices get more and more complex, developing software for those devices becomes increasingly complex. While big.LITTLE processing offers a way to balance high performance through the use of the ARM Cortex-A15 MPCore processor with power efficiency by switching to the ARM Cortex-A7 to extend battery life, these processors challenge software developers to keep up and both utilize the available compute power while being power conscious. With the right set of models, virtual prototypes offer a unique platform view to the software developer to ease the software development for these multicore designs. Moreover, they provide unique capabilities to make sure that software developers correctly utilize the available Android control functions to deliver a smooth user experience while minimizing power consumption.
Target audience: Software developers (intermediate and advanced).
|SoC FPGA Virtual Target: An Application of Virtual Prototyping|
Charu Khosla [Synopsys, Inc.]
SoC FPGAs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. It combines the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. In this tutorial you will be introduced to the Altera SoC FPGA Virtual Target for the Altera Cyclone V and Arria V SoC FPGA devices which are ARM-based designs. The SoC FPGA Virtual Target enables electronic products companies to develop software today in a more productive manner through a higher level of visibility and controllability. This tutorial will cover how to accomplish common software development and test tasks using a virtual target, as well as highlight the specific use of Synopsys’ virtual prototyping technology.
Target audience: Software engineers (beginner to advanced).
|Wednesday, March 28, 2012|
9:00 AM - 10:00 AM
|3D FinFET - New Structure Extends the Life of the Transistor!|
Chenming Hu, Professor Emeritus & Former CTO TSMC [UC Berkeley]
MOSFETs are undergoing the most drastic transformation in nearly 50 years. What’s driving this change and how will the move to 3D FinFET impact IC technology? What are these new transistors? What demands will they place on EDA tools and the design community? Professor Hu will provide insight into the driving factors behind these new transistors and how these transistors will enable the continued use of existing infrastructures of circuit and system designs, as well as device fabrication, for decades to come.View the Keynote
|Wednesday, March 28, 2012|
10:30 AM - 12:00 PM
|WA1 User Session: Design Planning|
|Powerful things you can do with Template-Based Power Network Synthesis combined with Basic Polygon Operations in IC Compiler|
Johnie Au [Cypress Semiconductor]
It is crucial for low power system-on-a-chip to have optimal power grid. Template-based power network synthesis flow provides the bells and whistles to quickly re-build a power grid. The flow creates of power plan regions with tailor fit strapping strategies. Since the flow allows parameters like width and pitch in templates, various floorplan explorations can be streamlined. As power network is mostly driven by placement coordinates of floorplan features, applying the basic polygon functions on the coordinates can derive even more complex custom power plan regions all within IC Compiler. This paper will discuss a few applications of such flow.
|Developing and Implementing a Flip Chip Interface using IC Compiler|
Prasanth Koduri, Sampath Oks, Anupam Gangopadhyay, Santhosh Pillai [Samsung], Susheel Sharma [Synopsys, Inc.]
This paper presents an in-depth study of FlipChip implementation techniques followed at Samsung Semiconductor for a 32nm large hierarchical SoC using Synopsys IC Compiler. The objective is to share considerations and challenges of bump placement, prioritizing critical interfaces, bump assignment, and RDL routing on critical signals. It also discusses various techniques for RDL routing such as differential, sneaking, and snake routing and the benefits and ease of staying within the same environment.
|WA2 User Session: Optimizing Test Time with SerDes and Manufacturing Data Analysis with Yield Explorer|
|Commonality Analysis with Yield Explorer|
Bharath Seshadri, Puneet Gupta, Vishal Mehta, Bruce Cory [NVIDIA Corp.]
A fast yield ramp enables a company to be competitive. To achieve our logic yield ramp goals for new technologies, NVIDIA developed a commonality analysis tool which leverages data from an existing volume logic diagnosis flow. The most important goals of our analysis tool flow are:
1. Identifying the systematic components of logic yield loss from the diagnosis data
2. Classifying the die based on different systematic signatures
3. Narrowing down the possible locations of the systematic defects
This paper describes the flow we developed at NVIDIA using the YieldExplorer(YE) tool as the main database and analysis engine.
|Optimizing Test Times using a Scan Deserializer/Serializer Architecture|
Milind Sonawane, Jonathon E Colburn, Amit Sanghani [NVIDIA Corp.]
We present the details of our SerDes (Serializer / Deserializer) Scan Architecture targeting NVIDIA’s GPU (Graphics Processing Unit) chips, and the ATPG pattern generation flow this architecture. This scan architecture has been used on several generations of GPU chips, along with the in-house pattern processing, verification and diagnosis flows, to improve the test time for ATPG based patterns in production test. Native support is now available in Synopsys TetraMAX® ATPG for SerDes scan. This support reduced the engineering overhead for the custom flows. We describe the customized architecture, logic design, protocol files, DRC, pattern verification and diagnosis flows.
|VCS Technologies and Testbench Methodologies for Achieving Higher Video Throughput|
Kiran Maiya [Synopsys, Inc.]
Verification engineers always face the challenge of meeting the ever reducing time to market and always growing list of corner cases to verify. There are new technologies that can help elevate some of these challenges. They can be in the form of simulator features or by using new methodology in building the testbenches.
This paper introduces concept of designing testbench using verification components in parallel and demonstrate how SystemVerilog language constructs and VCS technology allows higher throughput of video frames than the traditional approach. The topics discussed apply to testbenches involving protocols like HDMI and MIPI.
Target audience: Verification engineers, verification managers and team leads.
|WA4 Tutorial Session: Compute Farm Infrastructure for EDA|
|Optimizing Scale Out for Synopsys EDA Tools using a Common Distributed Processing Framework|
Ramki Balasubramanian [Synopsys, Inc.]
Distributed processing (DP) is a great way to scale out EDA workflows across many nodes. Traditionally, EDA has used GRID and custom workflows to manage scale out. However, future TAT optimization and scaling requires tighter coupling between the tool and infrastructure. Synopsys has built a DP infrastructure that works identically across GRID and non-GRID environments - CDPL (common DP library). Using CDPL within our tools, gains of 1.5X to 100X have been achieved in TAT. In this session, we will explore this technology, show some results across our tools and highlight key considerations to optimize your IT infrastructure for DP.
|Rightsizing EDA Infrastructure & Impact of Low Power Processors on EDA|
Venkata Ravella, Amit Sogani [Synopsys, Inc.]
Rightsizing infrastructure for EDA tools (focus on verification) for optimal throughput. We will discuss models to help determine what the “best” processor is given data-center constraints but at the same time not compromising on EDA job requirements. We will also discuss the trend of lower-power processors + SSDs, which are migrating from the mobile space into data centers. They come with a promise of cost reductions and are getting widely adopted. Do they work for EDA needs? We will share results of an early study of one low-power processor for verification jobs.
|Wednesday, March 28, 2012|
12:00 PM - 1:15 PM
|Lunch and Learn|
|The Scaling Factor: The Impact of Process Migration on IP Design|
Suk Lee, Director of Design Infrastructure Marketing Division [TSMC]
Designs are migrating to ultra deep sub-micron process technologies to meet the high performance and low power requirements of today’s consumer electronic devices. This migration significantly impacts IP development and SoC design, due to the stringent requirements on design for manufacturing capabilities, power consumption, area and performance. Join us at this special luncheon to hear how TSMC, a leading technology and foundry services provider, collaborates with its ecosystem partners and customers to understand challenges of today’s complex designs and offer insights on how to ensure successful design implementation in advanced processes.
|Wednesday, March 28, 2012|
1:15 PM - 2:45 PM
|IC Compiler: Achieving Design Success at 20nm|
Rajiv Dave, Zugang Li [Synopsys, Inc. ]
Advanced technology nodes present a whole new set of design challenges in achieving Timing and Place and Route closure. This tutorial discusses the 20nm design closure techniques available for IC Compiler. It covers post route optimization flow for addressing hold, transition and signal EM optimization techniques. Second session we covers challenges such as advanced technology design rules (DRC), double pattern technology (DPT), optimal standard cell library layout and demonstrate how IC Compiler will help you achieve design closure.
Target audience: Physical designers and managers.
|WB2 User Session: Power Efficient Clocking for Test and Custom Scan Chain Stitching with DFTC|
|Power-Efficient Functional and Scan Clocking for High Performance Cores|
Martin Amodeo, Dwight Elvey [AMD], Aurelia De Colle, Lori Schramm, Tim Ayres [Synopsys, Inc.]
As the popularity of mobile devices and the need for massively threaded cloud computing farms increase, power consumption metrics and efficient parallelism become nearly as important in microprocessor design as single thread performance. This paper presents new test challenges but also new capabilities for TetraMAX ATPG tool to leverage. Precise control of active clock regions and fine-grained clock gating are hardware features which can be used by ATPG to reduce test switching activity, thereby reducing test voltage droop and power consumption during test.
|Scan Stitching Separate Groups of Mux-D or LSSD Flops|
David Chinnery, Kedar Kulkarni, Tejinder Jaswal, Umesh Chejara, Pawan Panday, Nethra S Gopal, Girish T Prabhakara [Advanced Micro Devices, Inc.]
Mux-D flops are slower than LSSD flops, but they have lower area and lower power. An advantage of LSSD flops is that they are not subject to races on the scan data paths because they have two separate scan clocks. Separate groups of mux-D or level-sensitive scan design (LSSD) flops need to be stitched across multiple scan chains.
We detail a generic approach for grouping flops and scan stitching both flop types. User specified groups of flops are identified to DFT Compiler by separate scan clocks for the LSSD flops and by separate scan enables for the mux-D flops.
|Getting X Propagation under Control|
Bruce Greene [Synopsys, Inc.]
The X-optimism semantics of standard RTL simulation can lead to incorrect behavior which often conceals design bugs. These bugs lead to passing simulations and creating problems that are difficult to correct later in the flow.
This tutorial explores a new method to address this problem that changes the X semantics in order to remove the incorrect results dues to X-optimism.
Target audience: Design & verification engineers and managers.
|WB4 Tutorial Session: Compute Farm Resource Usage and Optimization|
|Business Rules Monitoring - Automated Resource Policy Implementation|
Chris Sooy [Altera], John Mincarelli [Synopsys, Inc.]
Business Rule Monitoring (BRM) is a fully automated system for enforcing compute farm resource-usage policies based on business requirements. The policies utilize rules to specify and detect situations in which the policy is violated and associated corrective action rules can specify situations in which to apply corrective action. During operation, the BRM system receives resource-usage information which includes job monitoring data and process monitoring data, determines a resource-usage violation by applying the resource-usage rules to the resource-usage information, notifies and escalates alerts to users and management, and in the event of a rule violation, applies corrective action.
|Leveraging Adaptive Resource Optimization with Lynx|
John Mincarelli [Synopsys, Inc.]
Adaptive Resource Optimization (ARO) is a closed loop system which collects the required “Predictors” of an element being processed by the DRM. ARO applies adaptive predictive techniques to the Predictors to algorithmically determine trending of the job resources and the future processing requirements for Memory and/or CPU runtime within a controlled acceptable level of reliability. ARO as implemented with Lynx is a general solution on a project or multi-project basis. ARO enables the designers to do their work without having to build/modify/create scripts and utilities while benefitting from a completely automated and transparent system for maximum productivity and job throughput.
|Wednesday, March 28, 2012|
3:30 PM - 5:00 PM
|WC1 Tutorial Session: Advanced Multichip Design|
|Design of a 2.5D Silicon Interposer using IC Compiler|
Frank Malloy [Synopsys, Inc.]
3D IC is an exciting new technology which offers lower-power designs, higher-speed interfaces, and dramatic improvements in performance and logic density never seen before - all without having to move to smaller, complex technology processes. Silicon interposers are ushering in 3D technology by mounting multiple chips on a high-speed, inexpensive silicon die to create a system on silicon. This tutorial will demonstrate Synopsys’ silicon interposer implementation solution through the creation of a multi-chip stacked 3D design.
|Creating Multi-IO Ring Die Using IC Compiler|
Sufyan Khan [Synopsys, Inc.]
As technology nodes continue to shrink, often die size is limited by the size required to form a single, perimeter ring of IO drivers. To minimize die size, most design teams faced with pad limited die sizes are turning to multi-IO ring layouts. This tutorial walks through how to create multiple IO rings on a die, and how to populate the rings with both general purpose IO drivers and IO macros. The multi-IO ring layouts can be used for both wire bond and flip chip packaging. The tutorial is targeted for physical design engineers and managers.
|VCS Technologies for Efficient Development and Debug of UVM Testbenches|
Srivatsa Vasudevan [Synopsys, Inc.]
The Universal Verification Methodology (UVM) is a standard developed by Accellera for the purpose of improved interoperability and reduced cost of rewriting IP for each new project or EDA tool. In this tutorial you will learn about VCS technologies that can help in developing and debugging UVM testbenches.
Target audience: Design & verification engineers and managers.
|WC4 Tutorial Session: Management of High-Performance Compute Resources|
|Understanding the Impact of NFS Overhead|
Glenn Newell [Synopsys, Inc.]
At previous SNUGs we discussed methods for measuring NFS latency; however they required root access and did not reveal storage volume level information. Newer Linux kernels now have counters that allow users to see per mount NFS latency. We will discuss how to access the counters and demonstrate scripts that will be useful in identifying network/storage bottlenecks and help Engineers and CAD managers see the impact of storage load during EDA tool runs in a more meaningful way.
|Monday, April 23, 2012|
1:00 PM - 2:00 PM
|TA8 Lunch and Learn Session|
|Your Peers are Benefiting from the Latest Design Compiler Technologies, Are You?|
John Busco, [NVIDIA]; Bob Turner, [Broadcom]; Ed Bender, [AMD]
|Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking|
Kesava R. Talupuru, Sanjai Athi [MIPS Technologies]
|Oh Boy, Chip Area Blows-Up Again!|
Keith Duwel [Altera]
|SoC performance evaluation using high performance SystemQ and TLM models for communications SoCs|
Rocco Jonack [Sonics, Inc.], Bernhard Keppler, Dr. Renate Henftling [Lantiq GmbH]
|Analyzing AOCV GBA Pessimism Reduction and AOCV Block Based Derate in 2011.12 PrimeTime|
Alexander Tetelbaum [LSI], David Keyser [Synopsys, Inc.]
|Clock gating: Comparing Effectiveness of Manually Inserted versus Power Compiler Inferred|
Nanda Lekkelapudi, Maya Mohan [MIPS Technologies]
|Using IC Compiler for Signal EM Fix in 28nm|
Kevin Huang, James Deng [Altera]
|Efficient implementation for multi-channel FIR filters using Synplify Pro for the new mid-range Lattice FPGA devices|
Nilanjan Chatterjee, Asher Hazanchuk [Lattice Semiconductor Corp], Hariharan Sankaran Ph.D., Amit Roy, Madhav Chikodikar [Synopsys (India) Pvt. Ltd.]