Abstracts

Monday, March 29, 2010
11:00 AM - 12:30 PM

MA1 Tutorial

PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure
[Synopsys, Inc.]

In-design Rail Analysis provides accurate signoff level power network metrics from within the traditional place and route flow. With the recent release of IC Compiler (2010.03), Synopsys has extended In-Design to support dynamic rail analysis. This tutorial covers the following: early incremental power network fix guidance within ICC based on PrimeRail’s rail checking capability, PrimeRail’s inrush analysis capability for switch architecture control design during the IC Compiler design planning phase, and finally an ECO placement link after routing using PrimeRail’s decoupling capacitance analysis and insertion.
Target audience: Digital IC and SoC designers, CAD engineers, Galaxy physical implementation users.

MA2 User - Constraints and Power Challenges in Verification

Generating Microcode Stimuli Using VCS Constraint Solver
Rajat Bahl, Greg Tang [Advanced Micro Devices, Inc.], Padmaraj Ramachandran, Alexander Wakefield [Synopsys, Inc.]

Generating microcode stimuli using constraint solver is an effective technique for random verification of microprocessor designs. We explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while still providing optimal distribution and biasing to hit corner cases. This paper presents and analyzes the proposed method and discusses its effectiveness in today’s verification environment.

Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster
Kesava Talupuru [MIPS Technologies, Inc.]

With shrinking process technologies, static and dynamic power are increasing rapidly, forcing designers to use a variety of implementation techniques to control power. Power gating is commonly used to shutdown non-operating blocks and voltage/frequency scaling is applied to reduce dynamic power by reducing voltage to parts of an SoC that don't need to operate at high speed. Complete verification of these power-aware designs has become increasingly complex and challenging. This paper focuses on the verification of the low power manager in the context of MIPS Technologies 1004K Coherent Processing System (CPS) consisting of four cores and one coherency manager.

MA3 User - XA

XA for Read Channel IC Design
Gangqiang Zhang, Vineet Tiwari [STMicroelectronics], Felix Ruan [Synopsys, Inc.]

With the decrease of device geometry and the increase of circuit operating speed and complexity, simulation time has become a major bottleneck for designers. This paper shows how using XA simulator in our design flow has allowed us to have faster turnaround time, which in turn allowed us to verify more chip functions and avoid silicon re-spin. The circuits used for XA are common analog blocks for read channel.

Simulation of the Global Clock Distribution Network in a High-Performance 40nm, 850-MHz Discrete GPU
Tony Todesco, Victor Ma [Advanced Micro Devices, Inc.]

This paper describes the simulation of a low-skew tree-grid global clock distribution network implemented successfully in a high-performance large 40nm, 850-MHz discrete GPU. The simulation challenges of large netlist size with inductance and output short with a clock mesh are addressed. The requirement of a daily ECO, extraction, and simulation turn-around on the clock distribution network was met using a fast SPICE simulation tool. Final signoff with a direct-method SPICE simulator confirmed the desired results.

MA4 User - Design Methodologies

Designing Hierarchically Reusable Digital IPs Using DC-T/ICC Flow
James Deng [Altera Corp.]

Designing reusable IPs is challenging with multiple levels of hierarchy and multiple instantiated modules (MIM). The traditional DC/Astro flow used for the tape-out of digital IPs in our 45nm S4GX FPGA device has issues about correlation, handling multiple hierarchies, and timing closure in MCMM. This paper presents a working DC-T/ICC design flow for designing digital ASIC IP blocks. It compares the QoR and the capability of addressing major issues of the new flow with the former DC/Astro flow. The result shows the new flow can achieve better QoR. The capability of handling MIM and nested ILM models is also examined.

A Case Study – Hierarchical Design 2.0
Vivek Rajan [Intel Corp.]

Full-chip physical design and integration methodologies often limit the creation and parallel convergence of LTP (layout, timing, power) constraints during early design phases, while in the later stages they dictate the ease-of-assembly and final convergence. In large hierarchical designs, APR results depend on the completeness and accuracy of LTP constraints. Providing consumable LTP constraints while architecture and RTL are evolving is very challenging. This paper highlights key challenges faced by SoC systems and make suggestions for next-generation EDA ecosystem.

MA5 Tutorial & User - StarRC

Tutorial: Design Signoff Beyond 45nm: Addressing Next-Generation Challenges with StarRC Extraction Solution
Bari Biswas [Synopsys, Inc.]

IC design and signoff analysis are facing significant challenges past the 45nm process technology node due to the increasing impact of new parasitic effects. This tutorial explores the various challenges of nanometer scaling including the effects of new device structures, planar vs non-planar transistor architectures, context-specific parasitics, lithography and chemical-mechanical-polishing process variations. It discusses how StarRC’s advanced parasitic extraction solution addresses these challenges through a close collaboration with leading foundries that delivers accurate parasitic modeling and enables IC designers to signoff on their stringent criteria with increased confidence.

Target audience: IC Design and CAD engineers/managers responsible for parasitic extraction and timing/SI signoff.

User: Using StarRC Open Access Interface for Accurate and Productive Custom IC Design
Mahesh Kondajji [Tabula, Inc.], Lalit Gajare [Synopsys, Inc.]

Open Access (OA) interface is gaining rapid adoption in custom IC design flows due to some basic advantages. However, designers are facing the challenge of transitioning their existing tools and infrastructure to an OA based flow/methodology. StarRC’s easy-to-use OA interface addresses key interface issues for post-layout simulation and custom implementation flows. This paper describes the many challenges faced such as circuit topology, setup related and discusses the advantages of StarRC – its seamless integration, flexibility and above all industry proven accuracy.

MA6 Vision

The Programmable Imperative - Next Steps
Moshe Gavrielov, President & CEO [Xilinx, Inc.]

Through the years, Programmable Logic has evolved considerably from a time where it was once viewed as a technology that was well suited primarily for ASIC prototyping. Today PLDs are a viable solution for higher volume production requirements. For most of today’s designs, programmability has transitioned from being an option to an imperative. As the world’s largest custom logic supplier, ahead of any PLD or ASIC company, Xilinx holds a unique vantage point in being able to understand the future challenges and needs of the logic designer. In this session, Moshe Gavrielov will share his views of the new dynamics and capabilities that will be realized as Xilinx ushers in a new era of logic design leveraging advanced semiconductor process technologies, Targeted Design Platforms, Industry Open Standards, leading edge software tools and methodologies that have been tuned to address the unique personas and needs of today’s and tomorrow’s designers.

Monday, March 29, 2010
1:45 PM - 3:15 PM

MB1 Tutorial

In-Design Physical Verification for Faster Time to Tapeout
Paul Friedberg, Ron Duncan [Synopsys, Inc.]

In-design physical verification, enabled by seamless integration of IC Validator within IC Compiler has proven to accelerate time to tapeout and manufacturing compliance at a range of customers, designing at 65nm and below. In-design physical verification with IC Validator eliminates late stage surprises by enabling “staged-verification” throughout the physical design process. This tutorial will demonstrate ease of setup and execution of in-design physical verification to help accelerate time to tapeout.
Target audience: Physical design and verification engineer and managers.

MB2 User - Verification with Magellan

A Reusable Magellan Formal Verification Environment
Nantian Qian [Broadcom Corp.], Mandar Munishwar [Synopsys, Inc.]

One of the challenges in widely deploying formal tools is their isolation from a mainstream verification flow. Mainstream verification flow abstracts the tool details via layering of scripts that are common to a project or company. This paper describes the development of a reusable formal verification environment for Magellan. The environment hides the tool details from users through common makefiles and tcl scripts of three layers: common for Magellan projects, project specific and session specific. The directory structure of the environment is organized accordingly.

RAM Models Verification Using Magellan
Dan Smith, Amy Yen [NVIDIA Corp.], Mandar Munishwar [Synopsys, Inc.]

Various phases of a chip design flow involve different views of a RAM. Since these models are derived from different sources, verifying equivalence of these different views is a challenge. As there are more than two models involved and some have different RTL structure, traditional equivalency checking tools are not useful. Magellan provides a hybrid-formal verification engine that can be effectively used to verify all models simultaneously and check for equivalency among them. This paper compares our earlier verification methodology with the new flow with Magellan, lists the benefits introduced with using Magellan.

MB3 Tutorial

HSIMplus CircuitCheck for Low Power Transistor Level Error Detection
[Synopsys, Inc.]

In this tutorial, we will demonstrate how HSIMplus CircuitCheck applies its vectorless approach to validate the design for the potential connectivity error due to its multi-voltage domain configuration, which is typical for low power design. The tutorial will cover the ESD protection topic covered by CircuitCheck's pattern matching capability, together with a demonstration of its static voltage propagation approach to identify the potential voltage bias issue. In addition, HSIMplus CircuitCheck can also be used to conduct the on-the-fly or post-processing waveform analysis, which is typically applied to meet the designer or foundry's SOA (safe-operating-area) requirement.
Target audience: Analog, memory and custom digital designers, CAD engineers and engineering managers.

MB4 Tutorial

Galaxy RTL: Design Compiler Family 2010.03 Update
[Synopsys, Inc.]

Design Compiler 2010.03 includes many new innovative technologies to improve designers’ productivity by accelerating synthesis runtimes and cutting physical implementation time. This tutorial presents the latest features and methodologies of the Design Compiler family of products, including power optimization and equivalence checking. The discussion will cover highlights of the release for improved quality of results, faster runtimes with multicore platforms, added controllability for leakage optimizations and usability enhancements. The session will also include enhancements to topographical technology for faster design closure such as passing physical guidance to IC Compiler & seamless integration with design planning. Additionally, new features in Formality and a recommended methodology for getting the best verifiable quality of results, fastest with DC Ultra and Formality will be discussed.
Target audience: This is an informative session for all existing and new synthesis users.

MB5 User - Signoff Correlation

Crosstalk Delay and Noise Correlation Flow between PrimeTime SI and HSPICE
Tariq El Motassadeq [Dubai Circuit Design]

Signal integrity between adjacent lines is becoming increasingly significant as IC dimensions enter the very deep submicron region. This has forced the static timing analysis tools to add more pessimism to face crosstalk delay and noise challenges in the design. Although this added pessimism, designers resort to SPICE analysis for critical paths to boost their signoff confidence. In this paper, we present a complete automated flow to correlate crosstalk delay and noise between PrimeTime SI and HSPICE.

Power Correlation with Silicon - A PrimeTime PX Evaluation
Steve Griffith [Aeroflex]

In today’s environment, customers are demanding higher performance and reliability along with lower system cost. Efficient use of power is a major factor in meeting these demands and accurate analysis is essential to achieve design success. This paper describes the Primetime PX methodology used in our evaluation. The test vehicle was a LEON 3FT microprocessor device, which is currently in production. Starting with a mismatch of more than 30%, we made improvements to the process and achieved final correlation results within 10% of silicon. Strategies for identifying problem areas along with solutions will be presented for each issue encountered. Findings and recommendations are summarized in the concluding remarks.

MB6 Tutorial

Tips and Tricks for FPGA Synthesis QoR, Debug, and Faster Turnaround Time
Will Cummings [Synopsys, Inc.]

With FPGA densities doubling every two years, the need for performance, fast debug cycles and faster implementation has never been greater. In this SNUG Tutorial, FPGA designers will learn how to resolve everyday design challenges using advanced project flow and design analysis techniques, tips and tricks for achieving better quality and more predictable results along with constraints set up and tuning for best QoR.
Target audience: FPGA design managers and engineers looking for high quality and predictable implementation results.

Monday, March 29, 2010
3:35 PM - 5:05 PM

MC1 Tutorial

Vertically Optimized 32/28nm Solution for Mobile SoC Design
Ana Hunter, Vice President of Foundry, [Samsung], Dr. Dipesh Patel, Vice President of Technology [ARM],

Dr. Jaga Jagannathan, Director, Semiconductor Technology, Marketing & Business Dev. [IBM],
Glenn Dukes, Vice President of Design Consulting [Synopsys, Inc.]

This session, hosted by ARM, IBM, Samsung and Synopsys, introduces a new level of collaboration necessary to address the cost and technical challenges associated with advanced mobile SoC design and manufacturing. As semiconductor technology approaches fundamental physical limits and design complexity reaches unprecedented levels, a deeper type of technical alignment is essential Learn how this extended collaboration enables customers to deliver optimized ARM based 32/28LP mobile SoC designs while achieving faster time-to-market at reduced risks and design costs. We explain how this collaboration is enabling a proven turnkey design solution for optimizing innovation and accelerating your design with best-in-class technology, physical and processor IP and tool/flow solutions for the IBM and International Semiconductor Development Alliance (ISDA) 32nm/28nm high-k metal-gate (HKMG) process technology.

MC2 User - TLM and VMM

Exploiting the TLM-2 Features of VMM 1.2
John Aynsley [Doulos]

VMM 1.2 introduces a set of features for transaction-level communication inspired by the SystemC TLM-2.0 standard. At the same time, the VCS TLI has been upgraded to support the TLM-2.0 standard. This paper, co-authored by the author of the TLM-2.0 standard itself, explains the significance of these new features to VMM and gives ideas on how best to exploit these features for communication between a SystemC reference model and a SystemVerilog test bench.

Interoperable Testbenches using VMM TLM
Asif Jafri [Verilab Inc.], Nasib Naser [Synopsys, Inc.]

SoCs are getting larger all the time and so is the challenge to verify these designs in a short period of time. This paper presents transaction level model (TLM) based methodology in VMM to standardize development of various pieces of a verification environment and the communication between them. This methodology promotes reuse and helps integrate modules from various sources to interact together seamlessly.

MC3 User - HSPICE

Multi-Threading & Multi-Processing HSPICE
Tom Mahatdejkul [ARM Physical IP]

HSPICE is the golden standard for simulation of electronic circuit performance. The addition of multi-threading (-mt) and multi-processing (-mp) extends the usability of HSPICE from development of individual electronic circuit blocks to the realm of full circuit instance characterization for real world test chips. This is made possible by the increase in simulation speed by utilizing all the CPU’s on the run machine. This paper reviews some basic concept of running –mt and –mp as well as reviewing practical applications of its usage in IP development and verification. Benefiting HSPICE multi threading and multi processing features are ARM standard cell library testchips and memory compilers.

Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design
Alvin Loke, Dru Cabler, Chad Lackey, Tin Tin Wee, Bruce Doyle [Advanced Micro Devices, Inc.], Zhi-Yuan Wu [GLOBALFOUNDRIES], Reza Moallemi [Synopsys, Inc.]

We present a substantially enhanced HSPICE feature that extracts MOSFET threshold voltage (VT) based on the constant-current definition universally adopted by fabs to measure, specify, and monitor VT. With simulated VT now conveniently correlated to measurement, this capability enables faster design of robust analog circuits in cutting-edge CMOS technologies where voltage margins are critically limited and only predictive models, subject to periodic retargeting, are available during design. The full feature was developed and evaluated using a 32-nm technology model and subsequently introduced in the 2009.09 HSPICE release. Operating point, DC, AC, and most importantly transient analyses are supported for industry-standard BSIM4, BSIMSOI4, and PSP MOSFET models.

MC4 Vision

The Evolution of Synthesis - From the Telephone to Logic Synthesis - to Smartphones, and Beyond
Eyal Odiz [Synopsys, Inc.]

Smartphones and Design Compiler have more in common than one can imagine! In order to understand how close relatives they are, Eyal Odiz will bring us back 170 years, and will show how telephony has led to logic synthesis, and conversely, how Design Compiler has led to smartphones. Eyal will also show how telephony and logic synthesis have both followed the same evolution path: that of convergence! The journey is not concluded: there is a great deal of new technology ahead, that will allow synthesis to keep contributing to the development of even “smarter phones”, and beyond. Target audience: Front and back end designers, design managers and anyone interested in RTL synthesis.

MC5 Tutorial

Using NanoTime for Improving Design Predictability and Productivity at Transistor-Level STA
Chirag Patel, Sahil Bargal [Synopsys, Inc.]

NanoTime is a transistor-level static timing analysis tool. It can be used to verify timing of a stand-alone block or can be integrated in the full-chip timing methodology for mixed analysis using transistors and timing models for lower-level blocks. This tutorial session provides some of the "Best Practices" to obtain the desired results from NanoTime along with details of things to look for and ways to improve productivity in each analysis phase.
Target audience: NanoTime user who desires tool usage techniques to achieve better QoR.

MC6 User & Tutorial - High Level Synthesis and Enabling Hierarchical Design Flow

User: Bridging the Gap between Advanced Image Processing and Hardware Design
Richard Cagley [Toyon Research Corp.], Nicholas Hogasten [FLIR Commercial Vision Systems]

We present the use of Synopsys M-synthesis for the rapid prototyping and production of advanced image processing algorithms. Design flow is illustrated from the perspective of a typical researcher who has little or no exposure to classical hardware description languages. The work presented here stresses the use of high level simulation and verification with direct translation to hardware. By bypassing classical translation of algorithms to hardware designers and dispensing with low-level simulation, we illustrate orders of magnitude reduction in design time. We will also illustrate how such a design flow is more maintainable and significantly less prone to implementation error.

Tutorial: Enabling Hierarchical FPGA Design Flow
Frederic Rivoallon [Xilinx, Inc.]

Maintaining repeatable results is critical in the FPGA timing closure phase and when making those inevitable last minute design changes. In this tutorial we will discuss effective RTL hierarchical design techniques, Synplify Pro and Synplify Premier’s Multi-Point Incremental capability and Xilinx’s Design Preservation flow allowing synthesis and implementation results to be preserved between design iterations.
Target audience: FPGA design managers and engineers.

Tuesday, March 30, 2010
9:00 AM - 10:00 AM

Guest Speaker

The Innovation Imperative: Defining a New Model for Semiconductor Manufacturing and Technology
Doug Grose, Chief Executive Officer (CEO) - GLOBALFOUNDRIES

As the market for advanced semiconductor technology continues its endless march forward, the industry faces increasing challenges to sustain the current pace of innovation. Leading-edge process technology is becoming more cost-intensive while design companies are developing chips with extraordinary complexity. From media convergence in the home to cloud computing in the data center, the next generation of technology will require an unprecedented level of performance, power efficiency, and cost-effectiveness to deliver on its full potential. The intersection of these factors will require a new model in the semiconductor industry a model in which chip design companies must redefine relationships with their manufacturing and technology partners. This presentation will explore the current model for innovation and how it must evolve to meet the growing challenges of today's global market realities.

Tuesday, March 30, 2010
10:15 AM - 11:45 AM

TA1 User - IC Validator and UPF

Reusable UPF for Multi-Voltage Design & Handling Analog Macros in Power Subsystem
Krishna Vittala [Microchip Technology Inc.]

These days almost every semiconductor chipset uses multiple voltage domains, either to cut leakage or for dynamic power reduction. A common method in multi-voltage designs is to completely shut down entire portions of RTL to save power. The power behaviour of these designs is captured in what is referred to as power intent file, commonly defined using the industry standard IEE 1801 (UPF) format. This paper describes a hierarchical UPF approach, which will allow you to reuse the UPF files for sub-modules across different products. This paper will also describe how to handle analog macros in the power subsystem in the context of a UPF flow.

Design Rule Check Classification System with IC Validator for Sub-45nm Designs
Pavel Rott [Intel Corp.]

Designs used in silicon manufacturing technology development test proposed design rules by skewing physical dimensions of drawn structures. These skews generate massive amounts of error data that needs to be properly classified. This paper describes requirements and design of a practical system for design check error classification and filtering. This system can be applied for tracking intended violations in novel designs and for waivers given during design rule check development.

TA2 Tutorial

Low Power Verification
[Synopsys, Inc.]

Low power designs are a necessity now for a product to be competitive at smaller process geometries. Power-saving architectures range from simple on/off designs with a few power domains to increasingly complex ones involving 10s of power domains and employing a combination of low-power techniques. While there is considerable verification impact for even the simplest power management architectures, the more complex architectures require a complete re-think of the verification paradigm. This tutorial presents a verification solution that adequately addresses basic and advanced low-power techniques. It also outlines a verification methodology based on industry best practices that brings structure and repeatability to an otherwise ad-hoc process.
Target audience: Engineers responsible for low power design and verification, engineering managers.

TA3 Vision

The Future of AMS Verification
Warren Wong [Synopsys, Inc.]

The convergence of computing, consumer and mobile applications necessitates integrating complex mixed-signal functions with sophisticated digitally adjusted analog circuits, multiple supply domains, and thousands of interface signals between the digital and analog blocks. Smaller nanometer process introduces layout dependency which affects functional and electrical yields as well as simulation accuracy and speed. We will look into how these change the state of AMS verification, the methodology and analysis requirements, and the direction of tools needed.
Target audience: Analog, memory and custom digital designers, modeling and CAD engineers and engineering managers.

TA4 Tutorial

Increased Productivity and Higher Predictability with the Lynx Design System
[Synopsys, Inc.]

Synopsys’ Lynx Design System is a unique, production-ready IC development platform, that allows designers and managers to increase designer productivity, enhance schedule predictability and lower overall cost of design. In this session, a technical expert will focus on a few of the many advanced capabilities of Lynx that address: 1. Global collaboration using Lynx’s unique design development infrastructure 2. Design exploration and tracking of design execution strategies with Lynx’s Runtime manager 3. Leverage Lynx’s Management Cockpit on-demand reporting to improve schedule predictability and new project planning
Target audience: Design engineers, project/program managers and design managers involved in the implementation of complex designs.

TA5 User - Scripts, Tricks and Setup

Hold is Not Setup (Derate is Not OCV)
Gerard M Blair [LSI Corp.]

The use of timing derate for margining against hold violations is re-evaluated drawing a distinction between the maximum variation of the sum of variables (as in setup) and the variation of the difference of two sums (as in hold). With a little math - common sense is used to show that hold and setup violations result from (and in) totally different factors. This argues that a hold-specific strategy is needed in the design of derate factors. A practical approach for implementation margining is suggested.

"There’s a better way to do it!" - Simple DC/PT Tricks That Can Change Your Life.
Paul Zimmer [Zimmer Design Systems]

If you spend a lot of time with Design Compiler and PrimeTime, every once in a while you stumble onto a tip or trick that makes you think, “Gee, why didn’t I think of that before?”. This paper is a collection of handy tricks that can make your life a whole lot easier. Having trouble making your scripts work when PD changes the hierarchy? Need a value in your script that isn’t available as an attribute? Having trouble keeping your scripts working with multiple netlists in various stages of the flow? This paper can help! Sure, you’ve muddled through before somehow, but, maybe, just maybe, there’s a better way to do it.

TA6 Vision

Science Fiction or Semiconductor Roadmap?
Mike Keating, Fellow [Synopsys, Inc.]

Carbon nanotubes, graphene transistors, extreme-ultraviolet lithography – these and numerous other technologies seemed like science fiction a few years ago. Today, they are on the verge of migrating from the lab to the manufacturing floor. This session will review some of the most interesting advances in technology, from semiconductor technology to IP design and software.

TA7 Tutorial

A Thumbs Guide to Specifying and Understanding System Trade-Offs for Data Converter IP
Navraj Nandra [Synopsys, Inc.]

This tutorial presents the key specifications of data converters (analog-to-digital and digital-to- analog converters) that are integrated into SoC applications such as audio CODECS, video front ends, high resolution sensor interfaces and advanced communication systems. Having provided a foundation or a “thumbs guide” for understanding the key specifications, practical examples will illustrate the trade-offs that impact system performance in terms of power, resolution, input bandwidth and sampling rate. Other key performance metrics will be given for the above applications.
Target audience: Design engineers that are involved in specifying analog front/back ends, SoC developers for consumer/prosumer devices, system architects writing specs for audio, video, high speed communication devices.

Tuesday, March 30, 2010
1:00 PM - 2:30 PM

TB1 User - Design Rules and Methods I

LeSa Lowers Leakage
Bruce Zahn [LSI Corp.]

This paper describes an evaluation of the new Synopsys LeakSaver (LeSa) technology. LeSa performs signoff aware leakage optimization by performing cell swaps of high leakage cells to lower leakage cells on paths with positive timing margin. This evaluation was performed on various 40nm blocks from networking and storage designs using a prototype flow. Using post-layout signoff parasitics and highly accurate timing models, LeSa achieves much greater leakage recovery over current optimization tools.

High Performance Design Using Zroute on 65nm Process Technology
Ramy Gamal [Dubai Circuit Design]

Today, Design for Manufacturing (DFM) has become an important mission and one of the most critical parameters for any ASIC design, especially with 65nm, 45nm and below. Zroute is the new routing methodology of IC Compiler produced by Synopsys, delivers high QoR and improved manufacturability (DFM) during the different stages of the design. This paper describes the implementation of a high performance design using Zroute, comparing the results of using the Zroute engine verses using the classical router in different stages of the design flow for TSMC 65nm technology process, and highlighting the impact of using Zroute on QoR and DFM.

TB2 User - Verification Topics

Integrating eVCs in a VMM Testbench
JL Gray [Verilab Inc.], Adiel Khan [Synopsys, Inc.]

Modern testbenches are often comprised of components drawn from multiple languages. In many of these cases, multi-language and multi-methodology interaction is rarely well-defined. In this paper, we will demonstrate the use of e verification components (eVCs) in a SystemVerilog/VMM testbench. Several complex issues arise when using SystemVerilog as the “primary” language. Initial simulator engine synchronization, random generation ordering, timing problems caused by program blocks, determination of what to randomize in each language domain, methodology synchronization between the VMM and eRM (including push/pull semantics involving scenarios and sequences) will all be discussed.

QuickGrade: An Efficient Algorithm for Managing Coverage Grading in Complex Multicore Microprocessor Environments
Michael Sanders, James Young [Advanced Micro Devices, Inc.], Paul Graykowski, Vernon Lee [Synopsys, Inc.]

Verification of multi-core processors involves the execution of tens of thousands of tests in a typical regression. Regression can take a week or more to execute, so there is a need for designers to have a highly optimized test list maximizing line and toggle coverage. This test list must be run and graded in a matter of hours. The optimized list must be bounded by a predefined number of tests, such that the runtime of the resultant mini-regression can be modified to meet scheduling needs. This article highlights a customized coverage grading solution jointly developed by AMD and Synopsys to provide an alternative grading methodology.

TB3 Tutorial

StarRC Custom Extraction Tuned for High Performance CustomSim Simulation
Satish Venigandla, Wen-Cheng Chang [Synopsys, Inc.]

The post-layout simulation runtimes are increasing 2-4x with every new process generation as transistor counts double, parasitics increase and new process effects come into play. Balancing the accuracy and analysis turn-around time is a critical concern for the designers of sensitive custom digital and analog mixed-signal designs. StarRC Custom and CustomSim offer highly optimized links that enable 10x simulation speedup without sacrificing accuracy. This tutorial will demonstrate how Synopsys’ post-layout solution is working to address custom designers’ productivity and accuracy challenges. Technologies such as hierarchical back annotation, selective parasitic reduction, active node simulation and other innovative techniques will be presented.
Target audience: Analog/mixed-signal SoC and IP design engineers/managers responsible for parasitic extraction and circuit simulation.

TB4 Tutorial

Optimized Implementation Methodology for High Performance Low Power Processor Core at 40nm and Below
Daniel Biset [Synopsys, Inc.]

Both mobile and tethered devices require increased performance with decreased power consumption. In this tutorial, we present how the optimized methodology for processor cores at 40nm and below address these needs. This tutorial describes results using some of the latest DC Topographical and IC Compiler capabilities together with a highly tuned set of user constraints, delivering impressive performance results. Key techniques covered include: shorten wires for higher clock frequency, methodology to minimize congestion and best convergence with high utilization and high cell density, crosstalk prevention and fixing, clock tree synthesis constraints and methodology, leakage optimization, and signoff optimization.
Target audience: Experienced physical designers.

TB5 Tutorial

Getting the Most from PrimeTime 2009.12
[Synopsys, Inc.]

This tutorial will cover how to effectively use PrimeTime’s comprehensive multicore capabilities, and will highlight new support in 2009.12 which is 2X faster for threaded SI and Non-SI analysis and extends distributed analysis to PrimeTime VX. The tutorial will also review advanced on-chip variation (AOCV) and PrimeTime ECO improvements in 2009.12. In addition, new usability enhancements to simplify analysis of violating paths including new GUI options for path tracing and reporting will be covered.
Target audience: Designers responsible for timing closure and signoff.

TB6 Tutorial

How to Leverage FPGA-Based Rapid Prototyping to Debug Elusive Hardware and HW/SW Bugs
[Synopsys, Inc.]

Today, electronic system designers are in need of a new debugging approach that is fast, affordable and addresses both hardware and software errors. Rapid prototyping with FPGAs can mean a three to six month head start to an ASIC project. This tutorial will review what debug capabilities exist today and how they are used, what methodology is appropriate in each phase of a design project, and the pros and cons of the approaches.
Target audience: Systems and verification managers and engineers looking for methodologies to debug their design. Software engineers who are looking for new ways of verification and control mechanism of their hardware.

TB7 Tutorial

Understanding PCI Express 3.0 and How to Implement the New Features

The next generation of the PCI Express protocol, PCI Express 3.0, incorporates significant changes that go beyond the increase in link speed from 5 GT/s to 8 GT/s. For example, the Physical Layer encoding scheme has been completely changed and new training sequences have been added to achieve optimal equalization settings at 8 GT/s. This tutorial will present the key specification changes for the PCI Express 3.0 protocol, equalization procedure, PIPE interface and electrical interface. In addition, trade-offs and practical implementation issues will be discussed through examples and lessons learned from the development of Synopsys DesignWare IP for PCI Express 3.0.
Target audience: Designers that have already developed a high performance SoC with PCI Express 1.x or 2.0 and is looking to understand the changes to the protocol changes and its effect on the implementation of their next generation SoC using PCI Express 3.0.

Tuesday, March 30, 2010
2:50 PM - 4:50 PM

TC1 User - Design Rules and Methods II

Achieving Timing Closure Using Relative Placement Technology
Krishna Kumar Gundavarapu [Cisco Systems, Inc.]

This paper describes DCG/ICC relative placement flow used to resolve AOI/OAI’s standard cell congestion hot spots. For a typical networking design, it involves processing numerous large data bus including left/right shifters, barrel shifters and crossbars. When the design is synthesized through DC, it decomposes these data paths into AOI/OAI’s. Although AOI/OAI’s provide great design area benefits, it does have negative impact on routability due to high pin-density count. Utilizing DCG/ICC relative placement feature along with different synthesis strategy, we were able to resolve these hot spots. A script-ware was developed to automate extracting data path element’s relative position, and the relative placement is maintained throughout DCG/ICC.

Clock Power Reduction-Analysis Metrics and Power Reduction Techniques
Avishek Panigrahi, Arvind Parihar [MIPS Technologies, Inc.]

An effort to reduce power involves both detailed analysis of the design as well as using techniques available in implementation tools. Detailed metrics also help gauge the effectiveness of any particular technique in the implementation tool. This paper presents a series of metrics \x{2013} to help RTL designers make better design decisions and help implementation engineers evaluate the effectiveness of power reduction methods available in IC compiler. It then goes through the available methods in IC compiler, compares the various techniques and methods, and presents comparative results between the techniques. The final results were a dynamic power reduction of 27% and clock tree power reduction of 61%.

Accelerated Implementation TAT with In-Design Physical Verification
Kyle Peavey [Texas Instruments], Sabbir Choudhury [Synopsys, Inc.]

Physical verification turnaround time is exploding for advanced nodes. Prevailing physical verification flows are predominantly post-processing oriented, relying on post-GDSII modifications of the design. These flows can lead to suboptimal results and can induce multiple, expensive discover-then-fix iterations between the place-and-route and physical verification tools. To bridge this gap between the place-and-route and physical verification tools, the current methodology needs to evolve to deliver signoff-quality checking from within and throughout physical design. This paper will present the existing flows’ inherent challenges and illustrate benefits offered by an in-design flow using Synopsys IC Compiler physical design solution and IC Validator physical verification tool.

TC2 User - Design Project Management

Agile IC Development with Scrum
Neil Johnson, Bryan Morris [XtremeEDA Corp.] (InSync)

This paper gives an introduction to Scrum and discusses how it may reasonably be adopted in IC development. Scrum is a process for developing software based on industrial process control theory used heavily in agile software development. It employs mechanisms such as self-organization and emergence where a self-managed team incrementally develops software through a series of 30-day sprints. Scrum relies on the assumption that in committing to a set of regularly scheduled deliveries, the most effective processes will emerge from the team itself. Process imposed by the team, Scrum asserts, is more effective than defined or externally imposed process.

Release Management: A Problem You Cannot Afford To Ignore (5 Steps to an Automated Release Flow)
Jeffrey Wren [Paradigm Works]

Release management is critical to the success of every hardware development environment. However, it is typically the most overlooked and underestimated task in most development teams. In this ever increasing complex world of ASIC and FPGA designs, the ability to manage the changes made by both design and verification members in a sufficient way is needed where one can quickly determine faulty RTL, synthesis, schematic, and layout updates. This paper will address the drawbacks of a typical release flow, and will put forth a proven 5 step process a design team can implement which can be then be automated.

TC3 Tutorial & User - Custom Design and HSPICE

Tutorial: Custom Designer Demo including Presentation for Efficient Analog IP Migration
Fredrik Ivarsson, Bob Lefferts [Synopsys, Inc.]

Learn the latest information about Synopsys’ custom design solution and how it is used to efficiently migrate analog IP. This session will begin with a live demonstration of the newest release of Custom Designer - 2009.12. For circuit designers, an in-depth demo will be shown highlighting advanced analysis features available in HSPICE and fully integrated in Custom Designer. For layout engineers, new advanced design rule driven layout visualization and auto-correction features as well as the optimized link to IC Compiler will be demonstrated. The session will conclude with a presentation of how the flexibility and programmability of Custom Designer was used to create a migration flow for efficiently up-scaling 65nm analog IP to 130nm that is DRC & LVS clean and fully functional.
Target audience: Circuit and layout engineers and managers that are involved in custom design and any designer involved in process migration projects.

User: Multi-Gigabit Serial Link Analysis using HSPICE and AMI Models
Doug Burns, Barry Katz, Walter Katz, Mike Steinberger, Todd Westerhoff [SiSoft]

High-speed serial links are rapidly becoming a primary mechanism used to transfer data between ICs. However, the sophistication of these links is such that predicting their performance using traditional simulation approaches is totally inadequate. Thus, IBIS has adopted a new Algorithmic Modeling Interface (IBIS-AMI) standard to address this challenge. Many vendors are now offering AMI models. This paper describes how SerDes buffer models can be supplied as HSPICE, AMI, or a combination of both. It also describes how different combinations of HSPICE and AMI Models can be combined into the same analysis. This provides a link between today’s HSPICE flow and the future AMI flow.

TC4 Tutorial

Low Power Multi-Voltage Design Implementation Methodology using the IEEE 1801 (UPF) Standard
Jeffrey Lee [Synopsys, Inc.]

This tutorial will cover the methodology for implementing low power multi-voltage designs using Design Compiler and IC Compiler D-2010.03 release. The tutorial will highlight new, flexible techniques with enhanced usability for front- and back-end flat and hierarchical flows. The scope will cover a complete low power design flow featuring RTL synthesis and optimization, DFT, placement, clock tree synthesis, detailed routing and formal equivalence checking. It will also address methodology related best practices and tips for successful implementation of your design using the IEEE 1801™ Standard for Design and Verification of Low Power Integrated Circuits, the Unified Power Format (UPF) for capturing power intent.
Target audience: This is an informative session for all low power implementation designers

TC5 Tutorials

Faster Timing Convergence with PrimeTime ECO
Jennifer Pyon [Synopsys, Inc.]

Learn how PrimeTime ECO can help improve turnaround time for timing ECOs and boost timing convergence. After the initial integration of the design blocks into the chip level, your design may have a large number of timing violations. PrimeTime ECO allows you to quickly evaluate possible fixes within PrimeTime, and generates a list of netlist changes that can be imported to an implementation tool, such as IC Compiler. This tutorial highlights PrimeTime ECO capabilities for setup fixing and hold fixing. Design examples will be provided to demonstrate usage for best QoR.
Target audience: Designers responsible for timing closure and signoff.

Galaxy Constraints Analyzer: Constraints Debugging Made Easy
Lionel Corbet [Synopsys, Inc.]

Today’s designs are getting larger and more complex: hundreds of clocks, power management, multiple modes, and in-house or 3rd party IPs with their own set of constraints that need to be integrated at the top level. In addition, designs are being developed over geographically dispersed teams. With this increased complexity and schedules and deadlines getting shorter and shorter, finalizing the design constraints is becoming extremely challenging. This tutorial will cover the challenges that constraints present in today’s designs. It will provide an introduction to the new Synopsys Galaxy Constraint Analyzer tool, the benefits it provides, how it can be used, and an introduction to the features that allow users to quickly find and debug constraint issues for their design.
Target audience: Design implementation engineers facing constraints development and debugging challenges, who are looking for a solution to drastically reduce the time needed to provide clean constraint definitions.

TC6 User - Implementation, Advanced Verification and Debug with FPGA-Based Rapid Prototyping Platforms

SoC Emulation Methodology with Chipit Iridium
German Fabila Garcia [Intel Corp.]

System-on-chip (SoC) architectures are evolving rapidly and are becoming the focus of the mainstream semiconductor industry. In order to meet the short time-to-market requirements, it is essential to have fast, efficient and reliable architecture analysis tools for quick prototyping and trade-off analyses. This paper presents the methodology and framework we developed to emulate a baseline SoC architecture using a CHIPit Iridium system. It describes how UMRBus communication system and on-board memory modules in the platform were used in the framework and finally describes the RTL instrumentation added to facilitate debugging and verification with trace dumping capabilities.

Automated Source Level Partitioning Flow for FPGA Rapid Prototyping with CHIPit
Sunil Menon [Broadcom Corp.], David Castle [Synopsys, Inc.]

The source level partitioning flow dramatically speeds up FPGA rapid prototyping, but there are still many manual steps involved. These steps slow down turnaround time. They use detailed procedures that are hard to document, which requires passing along verbal traditions like tribal legends. And, if any step is accidentally skipped, it can leave the system in a hard to debug, never-never land. This paper documents an automated flow that encapsulates the best practices and recommendations of the source level partitioning flow with flexibility and extensibility. It also optimizes use of multiple licenses for fast turnaround—up to 5× faster.

TC7 Tutorials

Understanding HDMI 1.4 and How to Integrate the New HEAC Feature into SoCs
Manmeet Walia [Synopsys, Inc.]

This tutorial will provide an overview of the innovative additions to the HDMI 1.4 standard with emphasis on the HDMI Ethernet and Audio Return Channel (HEAC) feature. The key goal of the tutorial is to explain the challenges behind implementing HEAC into an SoC/system and review the implementation choices and trade-offs. The tutorial will also explain how the HEAC and other HDMI 1.4 features will further simplify and enhance the digital home theatre system and portable multimedia devices.
Target audience: SoC designers, ASIC designers, system architects and digital home theatre enthusiasts.

The Fundamentals of Selecting High-Quality IP
Ralph Morgan [Synopsys, Inc.]

As more functionality converges onto a single device, it naturally leads to an increasingly large number of IP blocks on a SoC. Before you consider developing or buying IP, remember not all IP is created equally and securing high-quality IP is imperative to getting your end design to market on time and on-budget. This tutorial will explore three important determinants of IP quality including functional correctness, interoperability and ease of integration.
Target audience: SoC design engineers, managers.

Wednesday, March 31, 2010
9:00 AM - 10:00 AM

Guest Speaker

Collaborating for Success – A Historical Perspective
Rick Cassidy, President - TSMC North America

The semiconductor world has changed greatly … some would say wildly … since the first SNUG Conference 20 years ago. An overview of the technology and even the music paints a much different picture of society. Different also were TSMC, Synopsys and the design challenges of the day. By 2000, it became apparent that collaboration would be the hallmark of the entire semiconductor design chain. The design challenges of a decade ago built the foundation for today’s tight collaboration between all members of the design chain who today come together to reduce design risk and produce “right the first time silicon.”

Wednesday, March 31, 2010
10:15 AM - 11:45 AM

WA1 Tutorial

Energy Efficient Processor Implementation with Synopsys’ Eclypse Low Power Solution
Alan Gibbons [Synopsys, Inc.]

Delivering the energy efficient performance demanded by today's mobile devices is the focus for many design teams and requires the integration of high performance techniques together with intelligent power management in a streamlined methodology. Concurrent optimization of power and performance is a primary benefit of Synopsys’ Eclypse Low Power Solution and this tutorial will discuss the aspects of the Eclypse solution that enable designers to meet these aggressive power and performance targets. This tutorial provides a technical case study of a 32nm Eclypse based implementation of an ARM Cortex-A5 multi-processor with IEEE-1801 UPF based power intent.
Target audience: SoC engineers working on low power implementation with specific relevance to those working on synthesizable ARM processors.

WA2 Vision

The Future of Functional Verification
Janick Bergeron [Synopsys, Inc.]

In this session, Janick Bergeron will share his vision on verification for the coming decade. Although many challenges and principals remain the same as they have for the last 20 years, the approaches to address them change due to the economics of IC design and development. By drawing upon past and current trends, future approaches to these verification challenges are highlighted and discussed.
Target audience: verification engineers, managers.

WA3 Panel

Cloud Computing and the Implications for EDA
Vijay Bollapragada [Cisco Systems], Scott Clark [Broadcom Corp.], Jeff Barr [Amazon], Todd Martin [AppliedMicro], Kishore Singhal, Hasmukh Ranjan [Synopsys, Inc.]

Cloud Computing has become a hot topic recently. But what does that mean to me? This panel will discuss several aspects of Cloud Computing, the pros and cons for running EDA tools on Clouds, and some of the challenges that Cloud Computing presents for running EDA tools. The panel will also highlight specific examples of using Cloud Computing for EDA applications.
Target audience: IT and CAD personnel who manage Compute Farms running EDA applications, and users interested in Compute Farm optimization.

WA4 User - Advanced Test and Diagnostic Techniques for Large SOCs

Using Physical Layout Information to Improve the Effectiveness of Diagnosis Algorithms
Vishal Mehta [NVIDIA Corp.]

An open net may not be accurately diagnosed by a conventional diagnosis algorithm. A stuck-at fault diagnosis algorithm may narrow down the effect of an open defect at the cell boundaries. The open could potentially be anywhere along the net. A cell (driver) can drive n other cells (receivers). If an open only affects m receivers (where m < n), then it is a subnet open. The faults on the driver and the affected receivers may get suboptimal score. This may mislead PFA efforts. If physical layout information is used during diagnosis, then the open defect can be accurately isolated.

A Core-Based ATPG Approach For a 5 Million Flop Design
Charles Njinda [Cisco Systems, Inc.], Amy Mitby [Synopsys, Inc.]

Traditional scan-based test techniques are losing ground against today's SoC designs. Scaling technology and increasing design sizes equate to an overwhelming increase in test data volume, test application time and power consumption during test. Today, it becomes almost impossible to test a complex SoC design once it reaches manufacturing. Using a core-based divide-and-conquer approach combined with scan compression and power-aware automatic test pattern generation (ATPG) helps to manage complexity, turn-around time, test data volume, test application time and power consumption during testing. This paper describes the DFT strategies combining core wrappers and scan compression, discusses the core-based ATPG results and analyzes the costs and benefits of such an approach.

WA5 Tutorial

In-System Calibration for High-Speed DDR Interface IP
Dara Hurley [Synopsys, Inc.]

Despite the reliance on classic wide, parallel, source synchronous interfaces, DDR SDRAM based memory systems are doubling their bandwidth every three years. As much of the memory system itself remains relatively unchanged, the data eye integrity is squeezed by uncertainties in delays and signal skews as well as signal integrity issues such as synchronously switching outputs, inter-symbol interference and crosstalk. Aimed at SoC and DDR memory system designers, the goal of this tutorial is to present a systematic ‘data training’ sequence, to illustrate how calibration algorithms can optimize the SoC memory interface timing circuits in the end system.
Target audience: Anyone involved in specifying or implementing DDR memory system interfaces within SoCs, as well as system designers who are designing the memory systems on their target hardware.

WA6 Tutorial

Increasing Verification Efficiency using Embedded Software Driven Verification
Filip Thoen [Synopsys, Inc.]

Embedded Software development represents a large effort in today’s project cycles and often determines when a chip will get into volume production. Significant improvements in verification efficiency can be achieved when augmenting traditional hardware verification with transaction-level processor models executing embedded software executing test benches. This class will examine where traditional development techniques fail and will introduce virtual platforms as a solution for pre-silicon, more productive embedded software development as well as for hardware verification.

Wednesday, March 31, 2010
12:45 PM - 2:15 PM

WB1 Tutorials

Feasibility for IC Implementation
Mehrang Razzaz [Synopsys, Inc.]

Incorrect and incomplete design constraints are common in the early stages of the design cycle. This can lead to multiple iterations, long turnaround times, and even worse, poor design implementation that ultimately results in poor quality of results (QoR). This tutorial addresses feasibility during the pre-route stages of the design flow. It introduces an automated way to identify and analyze problems that impact timing, routability and congestion; a very fast optimization engine that efficiently deals with dirty data, and categorized timing reports that provide a detailed analysis of the violating endpoints that can be used to short-circuit the manual intervention process.
Target audience: Physical and back-end designers familiar with IC Compiler.

IC Compiler: Planning and Implementation of Large Hierarchical Designs
Raghu S Parvataneni [Synopsys, Inc.]

Continuously shrinking process technologies and the advent of large, automatically generated gate level netlists cause a rapid increase in design sizes. On the other hand, increased time-to-market pressure dictates ever shorter timelines to complete physical implementation and tape out. This tutorial presents a number of new technologies in IC Compiler to quickly develop a floor plan and perform trial implementations for large hierarchical designs. Use of these techniques minimizes runtime and memory requirements enabling fast, efficient, and accurate what if analysis and implementation of large designs.
Target audience: New and experienced physical designers and physical design team managers.

WB2 Tutorial

VMM 1.2 for New Users
[Synopsys, Inc.]

VMM was released in 2005 and was architected with reuse, extensibility, and scalability in mind to address the toughest verification challenges. The combination of proven base classes, ease-of-use and VMM Applications has allowed VMM to be successfully deployed in 500+ tape outs globally. Learn how VMM 1.2 address the needs of all novice and expert methodology users via features including implicit and explicit phasing, data passing and communication via channels and TLM, object factories, and planning.
Target audience: Verification engineers new to VMM, engineering managers.

WB3 Synopsys Whitepapers

Key EDA Metrics and the Path to Scale out EDA Computing using Clouds
Ramki Balasubramanian, Manish Neema, Sriram Sitaraman [Synopsys, Inc.]

As the general EDA computing environment gets more complex and expensive to host and manage, IT managers are looking to provide alternative solutions to meet the ever growing need for compute and storage. This need has driven cloud providers like Amazon EC2, which provides a simple virtualized flexible cloud. The typical EDA job profile may not be applicable, but the clouds can satisfy a range of EDA work loads.

Creative Ways to Use Queuing Software to Manage EDA Tool Runs
John Mincarelli [Synopsys, Inc.]

Project-Based Allocation (PBA) is a layer of Patent Pending automation that augments a queuing system by combining scheduled resource reservation with dynamic reallocation of unused resources based on priority and demand. PBA can help improve utilization of batch compute resources in compute farms by allowing idle CPUs that have been reserved for use by a particular project to be used opportunistically by others. The system reduces the need for human intervention to manually reconfigure queuing systems to meet changing end-user demands, reducing administrative overhead and potential for human error. It also contains a full complement of automated reports that can provide proactive feedback to optimize utilization and provide predictable results.

WB4 Tutorial

Test Automation Updates
Adam Cron [Synopsys, Inc.]

This tutorial delivers Galaxy 2009.06 and 2010.03 release updates for Synopsys industry-leading DFTMAX and TetraMAX Test Automation solutions. In addition, advanced topic sections will include methods to optimize compression architectures for pin limited scenarios, improve power efficiency during test, and apply new performance and usability improvements.
Target audience: Implementation and DFT engineers, as well as managers, interested in advanced test technologies.

WB5 Tutorial

Extreme Low-Power Datapath Design with DesignWare minPower Components
Buvna Ayyagari-Sangamalli [Synopsys, Inc.]

In most SoCs, datapath circuits are usually located in modules that are powered on for long periods of time. Consequently, the power savings achieved in datapath circuits usually translate into significant energy savings. The DesignWare minPower Components introduced a unique datapath design technology that can reduce the power consumption of these circuits beyond what is achievable in modern main stream flows. This tutorial will provide an overview of this unique technology, discuss the usage model and design flow considerations and close with customer case studies that demonstrate the power improvement enabled by this technology.
Target audience: design engineers, engineering managers, chip architects (topic level: intermediate).

WB6 Tutorial

The Best of Both Worlds – Combining Virtual and FPGA Prototyping for Verification and Embedded Software Development
Frank Schirrmeister [Synopsys, Inc.]

With software development overtaking hardware development efforts, productivity improvements at the hardware/software interface are crucial. A number of techniques are available to design teams for pre-silicon software development and verification, among them previous generation chips, virtual and FPGA prototypes and emulation. This session will use real project examples to demonstrate when in the design flow the different techniques are applicable and will introduce use models for System Prototyping, the combination of virtual and FPGA prototypes.

Wednesday, March 31, 2010
3:00 PM - 4:30 PM

WC1 Tutorial

IC Compiler 2010.03 Updates
Simon Koval [Synopsys, Inc.]

A summary of the new features, enhancements, and performance improvements in the 2010.03 release of IC Compiler will be presented. This includes design planning, 2X faster place_opt feasibility, a smoother and more capable hierarchical flow, AOCV pessimism reduction, enhanced EM support, MCMM enhancements (flexible hierarchical usage model, multi-mode CTS), integrated Zroute support throughout the flow, correlation improvements, route editing, in-design physical verification for faster design closure, leakage flow improvements including signoff-driven, and new capabilities in the ECO flow.
Target audience: IC Compiler users.

WC2 Tutorial

VMM 1.2 for Current VMM Users
[Synopsys, Inc.]

VMM 1.2 adds a number of important new features to improve reusability and efficiency. Verification engineers now have important choices to make as they architect and implement their code. This tutorial aims to give a basic understanding of the major new features in VMM 1.2 and how to quickly take advantage of them. How do you use the vmm_opts, vmm_rtl_config, and the class factory to create code that is more easily reused? How do you take advantage of ‘implicit phasing’ and the associated new base classes? What do the TLM classes buy us?
Target audience: Verification engineers with existing VMM environments, engineering managers.

WC3 Tutorial

Best Practices in Infrastructure for EDA Tools
Joe Fu, John Mincarelli, Glenn Newell, Venkata Ravella [Synopsys, Inc.]

EDA tool workloads present several challenges to the typical IT infrastructure. The different phases of the chip design flow also present different loads based on the domain specific work being done. This tutorial presents some best practices gleaned both from running and optimizing the 12,000 plus machines in the Synopsys internal infrastructure, and from customer engagements around performance optimization.
Target audience: IT and CAD personnel who manage Compute Farms running EDA applications, and users interested in Compute Farm optimization.

WC4 Panel

Improving Yield: Is it a Design, Test or Fab Problem?
Leah Clark [Broadcom Corp.], Luigi Capodieci [GLOBAL FOUNDRIES], Bruce Cory [NVIDIA], Manuel D'Abreu [SanDisk Corp.], Srikanth Venkataraman [Intel Corp.]

What do you do when your IC design has low yield? A few process generations ago, the answer was obvious: call the manufacturer and complain (loudly). For today’s nanometer designs, however, systematic yield issues often stem from both design and process marginalities. Who, then, should take on the task of improving product yield? Semiconductor manufacturers have long relied on TetraMAX ATPG diagnostics to identify circuit failure candidates. Now, a growing number of companies are deploying powerful analysis tools, such as Yield Explorer, that correlate failure candidates with design- and process-specific information to rapidly pin-point the root cause of yield problems. Our panel will discuss systematic yield issues and what steps designers, DFT engineers and failure analysis engineers are taking to address the yield conundrum.
Target audience: Designers, DFT engineers, test engineers and managers seeking perspectives on systematic yield issues and automation being used to improve product yield.

WC5 Tutorial

Implementing USB 3.0 on your SoC: Soup to Nuts -- IP Instantiation to Compliance Testing
Bob Lefferts [Synopsys, Inc.]

This tutorial will cover implementation considerations for integrating USB 3.0 onto your SoC from IP selection all the way to compliance certification and production testing. Topics will include PHY instantiation, power, reference clock selection, package design, board layout considerations, and signal integrity challenges at 5 Gb/s. Included in the presentation will be a live demo of a 5Gb/s USB 3.0 link with adaptive RX equalization, on-chip diagnostic and at-speed test features.
Target audience: For project managers, chip & system design engineers, physical designers and signal integrity experts, this tutorial will provide an overview of a complete USB3 PHY implementation.

WC6 Tutorial

Extending Design Flows to the System-Level – How ESL Fits into Your Design Flow!
Andy Haines [Synfora], Brett Cline [Forte], Steve Cox [Target Compiler], Chris Jones [Tensilica], Andrea Kroll [EDA Technologies], Bill Neiffert [Carbon Design Systems] Frank Schirrmeister [Synopsys, Inc.]

The cost of design has been identified by the ITRS as they key barrier to the continuation of the semiconductor roadmap. Raising the design entry from the current Register Transfer Level (RTL) to higher abstractions has widely been seen as the inevitable and only feasible solution. This session, held in combination with key partners of the Synopsys System-Level Catalyst program, will outline a system-level design flow from idea to verified RTL.

For Publication Only

Test Protocol File (SPF) Mapping For Custom Scan Architecture
Rao Lakamsani [STMicroelectronics, Inc.], Narasimha L Vadlamudi [Synopsys, Inc]

Depending on the scan architecture, it may be necessary to independently access the scan chains of a hard macro in the SoC so dedicated ATPG patterns can be generated for the macro. The test protocol file (SPF) of the macro must be mapped to top level to achieve this. SPFGEN is a TCL batch editor utility provided by Synopsys to help with SPF mapping. This paper describes our experience with SPFGEN on macros with complex scan architectures. It also outlines the challenges faced and solutions implemented.