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Going Beyond the Waveform: Advanced Debug Techniques in Verdi - Silicon Valley, 2014
Tutorial

IC Compiler 2013.12 Release Highlights - Silicon Valley, 2014
TutorialVideo

Low-Power and Simulation Performance in Mixed-Signal - Silicon Valley, 2014
Tutorial

Low-Power Design Implementation - Silicon Valley, 2014
Tutorial

Verdi Signoff-LP: Next-Generation Low-Power Static Verification - Silicon Valley, 2014
TutorialVideo

Next-Generation Low-Power Static Checking with Verdi Signoff-LP - Austin, 2013
Tutorial

Visualization and Debug of UPF with Design Vision GUI - Austin, 2013
Tutorial

Successful Multi-Voltage Design: Using Power-aware Equivalence Checking and Static MV Analysis to Boost Tape-out Confidence - Boston, 2013
Conor Byrne, Padraig Golden, Venkatesh Jakke - Intel
PaperPresentation

Verifying Low Power ASIC Design Specification (UPF) via FPGA Prototyping - Boston, 2013
Tutorial

"Digital Supplies are Analog !" - CustomSim-VCS with UPF - France, 2013
Tutorial

Converting an Outdated Library for UPF Compliancy Prior to a Low-Power Physical Design that uses Retention Flip-Flops - France, 2013
Etienne Wouters, Ilse Vos - IMEC
PaperPresentation

Low-Power Verification using Power State Table Coverage - France, 2013
Christophe Lamard, Jean Marie Guillermin - ST Microelectronics, François Cerisier, Mathieu Maisonneuve - Test and Verification Solutions, France
PaperPresentation

Taking Advantage of UPF2.0 for Advanced Low-Power Techniques - France, 2013
Frederic Saint-Preux - STMicroelectronics
PaperPresentation

Formality 2013.03 Update and Hierarchical UPF Flow - Germany, 2013
Tutorial

Low-Power Verification using Power State Table Coverage - Germany, 2013
Christophe Lamard, Jean Marie Guillermin - ST Microelectronics, François Cerisier, Mathieu Maisonneuve - Test and Verification Solutions, France
PaperPresentation

TA2.1 User Paper: Optimization Techniques for Designing a Channel Dominated High Activity Multimillion 500+Sq mm Chip - India, 2013
Anurag Mishra - LSI R&D (India) Pvt. Ltd. Vineet Kumar Kothari - Synopsys
PaperPresentation

- India, 2013
Synopsys

TD1.3 User Paper: Handling Nested Power Domains in Complex SoC - India, 2013
Shashank Bhonge, Vaishali Huilgol, Vinod Kumar Reddy - Xilinx
PaperPresentation

TD1.4 Tutorial: Unlocking the Low Power Potential of your Chip – An Advanced Flow Methodology using UPF2.0 - India, 2013
Tutorial

WB3.1 User Paper: The Last Microwatt - Challenges in Pre Silicon Power Estimation for Low-Power SoCs - India, 2013
Kaushik Saiprasad, Pooja Saseendran, Syed S Thameem - Intel
PaperPresentation