SNUG search results 


Accelerate SoC Testing Using Synopsys' DesignWare STAR Hierarchical System and DesignWare STAR Memory System - France, 2014
Arnaud Wenzel - STMicroelectronics
Presentation

Accelerating the Validation of a Secure ROM with ZeBu - France, 2014
Gherardo Gorni, Simone Borri – Abilis Systems
PaperPresentation

Adding a Metal Fringe Capacitance to an iPDK - France, 2014
Alain Vigne - Blinksight
PaperPresentation

Advanced CustomSim-VCS Multi Core Usage - France, 2014
Tutorial

Analog-on-top AMS Verification - a Practical Approach - France, 2014
Jonathan Bradford, Gernot Koch - Micronas
PaperPresentation

Automating SoC RTL to Operational Prototype - France, 2014
Tutorial

Better Faster Stronger Diagnostic Approach with Synopsys’ Yield Explorer - France, 2014
Jean-Marc Denollet, Thomas Droniou - STMicroelectronics, Christophe Suzor - Synopsys
PaperPresentation

Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goal - France, 2014
Tutorial

Certitude Advanced Tips - France, 2014
Jean-François Vizier - Dialog Semiconductor
PaperPresentation

Configurable On Chip Clocking Controller Clock Bit Chain Length to Minimize Test Compression OCC Dedicated Scan Access at SOC Level - France, 2014
Christophe Eychenne - STMicroelectronics
PaperPresentation

Debugging System Verilog Testbench with Verdi3 - France, 2014
Tutorial

Design Compiler 2013.12 Release Highlights - France, 2014
Tutorial

DFTMAX Ultra for Squeezing Out More Test Compression with Fewer Pins - France, 2014
Tutorial

Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption - France, 2014
John Aynsley, Dr. Christoph Sühnel and Dr. David Long - Doulos
PaperPresentation

ECO Implementation Assistance Using Formality Ultra - France, 2014
Tutorial

Emulation and Prototyping of Imagination GPUs using ZeBu and HAPS - France, 2014
Colin McKellar - Imagination Technologies, Andy Jolley - Synopsys Inc.
Presentation

Engineering Change Order - France, 2014
Didier Gueze, Jyoti Kumar, Sandesh Jain, Swati Narang - STMicroelectronics
PaperPresentation

Enrich your Mixed-Signal Verification with UPF Simulation - France, 2014
Tutorial

Exploration on CPU/GPU Designs with DC Explorer - France, 2014
Choukri Saidi, Sébastien Peurichard - STMicroelectronics
PaperPresentation

Generating Pattern to Debug Chain Segments in DFTMAX X-tolerant Mode - France, 2014
Matthieu Sautier – STMicroelectronics, Salvatore Talluto - Synopsys
PaperPresentation

- France, 2014
Guillaume Thomas - Synopsys

- France, 2014
Fouad Bissane - Synopsys