SNUG search results 


A Correct by Construction and Fast Method of Physical Integration and Signoff for Test Chip - Silicon Valley, 2016
PaperPresentation

A Generic UVM Agent with Fine-Grain Command-Line Configuration - Silicon Valley, 2016
Nikhil Kikkeri, Daniel Wei, Anirban Bhattarcharjee, Sumanth Gudlavalleti, Hui Shi, Sandra Shih - Oracle
PaperPresentationSession Recording

Accelerate Your FPGA Design Schedules with Synplify Premier - Silicon Valley, 2016
Tutorial

Accelerate Your Prototyping Productivity Leveraging HAPS Integrated Prototyping Solution - Silicon Valley, 2016
TutorialVideo

Achieving Higher Performance and Productivity with Native Integration of Simulation Flows Using Verification Compiler Platform - Silicon Valley, 2016
TutorialVideo

Adapt, Port, and Integrate Quickly – Prototyping the Right Way - Silicon Valley, 2016
TutorialVideo

Address Testability Issues Early with SpyGlass DFT ADV - Silicon Valley, 2016
TutorialVideo

Address TTM by Prototyping and Validating SoC Design Using HAPS-70 System - Silicon Valley, 2016
Xin Zhao, Veena Ramamurthy - SanDisk
Presentation

Advanced Reporting with PrimeTime - Silicon Valley, 2016
TutorialVideo

Advanced Synopsys UPF-Based Flow to Perform Implementation & Verification - Silicon Valley, 2016
TutorialVideo

Applying UPF 3.0 for Early, System-Level Power Analysis of SoCs with Micron DDR Memories - Silicon Valley, 2016
Tutorial

Architecting Your Way to Acceleration in UVM - Silicon Valley, 2016
Paul Lungu, Dean Justus - Ciena
PaperPresentation

Automated Memory BIST Insertion and Validation for SSD Controller-Based SoC - Silicon Valley, 2016
Padma Nagaraja, Vaibhavi Sabharanjak, Sumanth Shantaram, Dinesh Kumar Tadepalli - SanDisk; Khachatur Armenyan - Synopsys
PaperPresentation

- Silicon Valley, 2016
Subramoni Parameswaran, Ravi Ram - Xilinx
Session Recording

Best Practices for a Performance and Area Focused Implementation of High-Performance GPUs Using Galaxy Design Platform - Silicon Valley, 2016
TutorialVideo

Best Practices for High-Performance, Energy Efficient Implementations of the Latest ARM Processors in 16-nanometer FinFET Plus (16FF+) Process Technology Using Synopsys Galaxy Design Platform - Silicon Valley, 2016
TutorialVideo

Best Practices in Library Qualification for Signoff - Silicon Valley, 2016
Tutorial

Body-Bias Scaling – New Dimension to Explore the Design Space Using Body-Bias Capability - Silicon Valley, 2016
Ramya Srinivasan - GLOBALFOUNDRIES
Presentation

Bottom-Up Reusable Timing Constraints Development and Validation Methodology in Case of Multiplexed External Interfaces - Silicon Valley, 2016
Samuel Intiso, Jonas Oxenholt, Jan Bengtsson
Publish Only

Circuit Simulators Update: HSPICE, FineSim SPICE, and Custom WaveView ADV for Signal Integrity, Analog Simulations, and Waveform Post-Processing - Silicon Valley, 2016
TutorialVideo

Clock Design Challenges in a Large, Low-Power, High-Speed Signal Processing Design - Silicon Valley, 2016
Rishi Yadav, Nimit Nguansiri
Publish Only

Complete Low Power Verification and Formality 2016.03 Update - Silicon Valley, 2016
TutorialVideo

Constraints Development and Timing Closure Benefits of Using PrimeTime Automatic MUX Clock Exclusivity Feature - Silicon Valley, 2016
Stella Matarrese - STMicroelectronics
PaperPresentation

Containerize Your Chip Development Environment Using Docker - Silicon Valley, 2016
Chris Drake - Google
PaperPresentation