SNUG Awards 

1st Place - Best Paper
France
Improving STA Productivity at 32nm/28nmFDSOI and Below
Author(s): Sébastien Marchal - STMicroelectronics
PaperPresentation


STAR Hierarchical System (SHS) Architecture Implementation in Full IEEE1500 SoC
Author(s): Cédric Escallier - STMicroelectronics
PaperPresentation


GermanyAutomotive Microcontroller Peripheral IP Verification: Applying Certitude on SystemC Models
Author(s): Jürgen Hanisch - Robert Bosch GmbH; Florian Letombe - Synopsys
PaperPresentation


IsraelComprehensive AMS Flow for Submicron SoC Design
Author(s):
PaperPresentation


Silicon ValleyReverse Gear: Re-Imagining Randomization Using the VCS Constraint Solver
Author(s): Bryan Morris, Paul Marriott - Verilab Canada Inc.; Jonathan Bromley - Verilab UK Ltd.
PaperPresentation


SingaporeUser Paper 1: Optimum Leakage Recovery using Synopsys PrimeTime ECO Leakage Recovery Flow
Author(s): Altera Corporation
PaperPresentation


User Paper 3: More than Waiver - Automating Regession of Design Rule Deck
Author(s): Altera Corporation
PaperPresentation


UKScan Insertion and ATPG for C-gate Based Asynchronous Designs
Author(s): David Lloyd, Richard Illman - Dialog Semiconductor
PaperPresentation

2nd Place - Best Paper
France
Physical Data Loading to Improve Diagnosis Accuracy
Author(s): Nelly Feldman, Vincent Robert – STMicroelectronics, Christophe Suzor, Salvatore Talluto - Synopsys
PaperPresentation


GermanyUsing ICV for Power Network ECO
Author(s): Steffen Rost - Infineon Technologies, Tobias Buschner - Chipglobe GmbH
PaperPresentation


IsraelAutomate Connectivity Validation Using Verdi's Novas Programmable Interface (NPI)
Author(s):
PaperPresentation


Silicon ValleyAdvanced Node Random Device Variability Modeling and Margining in Characterization and STA
Author(s): Tamer Ragheb, Steven Chan, Ning Jin, Richard Trihy - GLOBALFOUNDRIES
PaperPresentation


SingaporeUser Paper 4: Single Static Timing Analysis Run for Multi Mode Peripherals in SoC Design
Author(s):
PaperPresentation


User Paper 1: CMP Driven Lithography Design Optimization Using Synopsys ICC / ICV
Author(s): GLOBALFOUNDRIES Singapore
PaperPresentation


UKTransitioning from DFTMAX to DFTMAX Ultra
Author(s): Richard Illman - Dialog Semiconductor
PaperPresentation

3rd Place - Best Paper
France
Engineering Change Order
Author(s): Didier Gueze, Jyoti Kumar, Sandesh Jain, Swati Narang - STMicroelectronics
PaperPresentation


GermanyApplying an IC Compiler Flow to Address the Requirements of Automotive Mixed-Signal Designs
Author(s): Rainer Kraly - Elmos AG
PaperPresentation


Silicon ValleyUVM Transactions: Definitions, Methods, and Usage
Author(s): Clifford E. Cummings - Sunburst Design, Inc.
PaperPresentation


SingaporeUser Paper 4: Using Synopsys Asynchronous OCC IP to Target Cross Clock Domain Faults
Author(s): Lantiq Asia Pacific
PaperPresentation


User Paper 2: Novel Retention Synchronizer Flip-Flop Translation Method in Synthesis Flow
Author(s):
PaperPresentation


User Paper 2: An Advanced Approach to Optimize Hierarchical Pin Assignment
Author(s): MediaTek Singapore
PaperPresentation


UKReducing Timing ECO Loops using Physically Aware ECO
Author(s):
PaperPresentation

Best Paper Award
Austin
FB5.1 - ATPG Techniques and Methodology for Low-Power High Effectiveness Pattern Generation in a High Performance Quad-Core CPU Design
Author(s): Kelvin Ge, Vivek Ramnath - Samsung Electronics
Paper


BostonReducing Cell Placement Congestion Using Targeted Pattern Halos
Author(s):
Paper


GermanyEasier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption
Author(s): John Aynsley, Dr. Christoph Sühnel and Dr. David Long - Doulos
PaperPresentation


India

WA1.3 User: An Alternate Approach to Address Emulation of Complex Clocking Systems in FPGA Platforms
Author(s): Venkatesh Natarajan - Texas Instruments; Ashwani Sharma - Synopsys
PaperPresentation



WB1.2 User: PrimeTime Based Efficient Approach for CDC and MTBF Checks in a Complex SoC
Author(s): Saksham Pant - NVIDIA
PaperPresentation



WD1.2 User: Serializer Mechanism in Asymmetric Scan Configuration
Author(s): Mudasir Kawoosa, Rajesh Mittal - Texas Instruments
PaperPresentation



WC2.3 User: Block Level Electromigration for More Effective Reliability Check In Full Custom IPs
Author(s): Atul Bhargava, Radhika Gupta, Monika Rawat - STMicroelectronics, Mridul Sengupta - Synopsys
PaperPresentation



WD3.3 User: IP Design - Efficient and Fast Prototyping and Porting to ASIC Using Synopsys Tools
Author(s): Prasanth R I, Thomas Varghese - Mindtree Ltd.
PaperPresentation



TA2.1 User: Innovative Techniques to Achieve Optimal QoR with Faster Design Closure Cycle on a Multimillion SoC
Author(s): Sitharam Ayathu, Pranjal Tiwari, Sailesh Vanama - LSI R&D India Pvt. Ltd., Gaurav Ganeriwal - Synopsys
PaperPresentation



TD2.3 User: Efficient Static and Formal Verification Closure of Low-Power Designs
Author(s): Satyanarayana A, Rakesh Madala, Shilpi Varshney - AMD
PaperPresentation


TaiwanTA1.3 Concurrent Clock Tree OCV and Process Corner Variation Reduction
Author(s): Chien-Pang Lu - MediaTek
PaperPresentation


TA4.2 Missing Piece of Low Power Verification: UPF Code Coverage
Author(s): Shang-Wei Tu - MediaTek, Tom Lin - Synopsys
PaperPresentation


TB1.1 Leakage Power Optimization and Congestion Aware Feedthrough Methodology
Author(s): Andrew Shen, Ryan Su - MediaTek
PaperPresentation


UKHow to Write an Optimum Verilog-A Model
Author(s): Peter Grove - Dialog Semiconductor
PaperPresentation

Technical Committee Award
Austin
FB5.1 - ATPG Techniques and Methodology for Low-Power High Effectiveness Pattern Generation in a High Performance Quad-Core CPU Design
Author(s): Kelvin Ge, Vivek Ramnath - Samsung Electronics
Paper


FranceSTAR Hierarchical System (SHS) Architecture Implementation in Full IEEE1500 SoC
Author(s): Cédric Escallier - STMicroelectronics
PaperPresentation


GermanyEasier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption
Author(s): John Aynsley, Dr. Christoph Sühnel and Dr. David Long - Doulos
PaperPresentation


IsraelComprehensive AMS Flow for Submicron SoC Design
Author(s):
PaperPresentation


Automate Connectivity Validation Using Verdi's Novas Programmable Interface (NPI)
Author(s):
PaperPresentation


Silicon ValleyReverse Gear: Re-Imagining Randomization Using the VCS Constraint Solver
Author(s): Bryan Morris, Paul Marriott - Verilab Canada Inc.; Jonathan Bromley - Verilab UK Ltd.
PaperPresentation


UVM Transactions: Definitions, Methods, and Usage
Author(s): Clifford E. Cummings - Sunburst Design, Inc.
PaperPresentation


Advanced Node Random Device Variability Modeling and Margining in Characterization and STA
Author(s): Tamer Ragheb, Steven Chan, Ning Jin, Richard Trihy - GLOBALFOUNDRIES
PaperPresentation


UKHow to Write an Optimum Verilog-A Model
Author(s): Peter Grove - Dialog Semiconductor
PaperPresentation


Technical Committee Award Honorable Mention
France
Exploration on CPU/GPU Designs with DC Explorer
Author(s): Choukri Saidi, Sébastien Peurichard - STMicroelectronics
PaperPresentation


GermanyAnalog-on-top AMS Verification - A Practical Approach
Author(s): Gernot Koch, Jonathan Bradford - Micronas GmbH
PaperPresentation


IsraelLatch Base Design - Alive and Kicking
Author(s):
PaperPresentation


UKSafety 1st, Infineon implements ProtoLink's FPGA Fault Injection to Provide Safer Roads
Author(s): Martin Terry, Mike Dunk - Infineon Technologies
PaperPresentation