SNUG Awards |
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1st Place - Best Paper
Austin | Taming Testbench Timing: Time's Up for Clocking Block Confusion
Author(s): Jonathan Bromley, Kevin Johnston (Verilab)
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| | Boston | Clocks Against Variation
Author(s): Gerard M. Blair (LSI Corporation)
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| | Canada | Integrating SVN Revision Control Software with Synopsys Custom Designer
Author(s): James Cherry (Kapik Integration)
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| | France | Efficient Flow for the Debug of Compressed Scan Patterns During Serial Simulations
Author(s): Sébastien Rousset, Mathieu Thomas [Scaleo Chip]
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| | Germany | Efficient Common Derating for Synopsys Implementation Tools
Author(s): Sönke Grimpen - Infineon Technologies AG
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| | Silicon Valley | Optimizing Test Times using a Scan Deserializer/Serializer Architecture
Author(s): Milind Sonawane, Jonathon E Colburn, Amit Sanghani [NVIDIA Corp.]
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| | Singapore | Managing Test Power Consumption on complex SoC
Author(s): Shibu Menon, Santhosh Sagar Potharam (ST-Ericcson)
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| | | Circuit Check enhancements to reduce false violations for Low Power Design
Author(s): Samaksh Sinha, Ma Fan Yung, Arumugam Saravanan, Luong Nguyen (Infineon Technologies Singapore)
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| | UK | Property Checking of Datapath using Word-Level Formal Equivalency Tools
Author(s): Theo Drane [Imagination Technologies], Himanshu Jain [Synopsys, Inc] | | |
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| | 3rd Place - Best Paper
Austin | Qualcomm DSP Semi-Custom Design Flow: Leveraging Place and Route Tools in Custom Circuit Design
Author(s): Nadeem Eleyan, Patrick Szabo, Ken Lin, Paul Bassett, Masud Kamal (Qualcomm), Frank Glover (Synopsys, Inc.)
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| | Boston | Assert Your Independence! Adopting the OVL Assertion Library as an IP/SoC Standard
Author(s): John A. Thomson (Advanced Micro Devices)
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| | Canada | Insight Into Power Gating Verification
Author(s): Ashwini Chandrashekhara Holla (Advanced Micro Devices)
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| | France | Using TetraMax Top Level Protocol Generation to Extract DFTMAX Codec Information for Lifetest Pattern Generation (HTOL)
Author(s): Gerald Briat, Stéphane Guilhot [ST-Ericsson], Philippe Rossant [Synopsys]
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| | Germany | Best Practices of Hierarchical Design Implementation Strategies
Author(s): Norbert Mueller - LSI
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| | Silicon Valley | Developing and Implementing a Flip Chip Interface using IC Compiler
Author(s): Prasanth Koduri, Sampath Oks, Anupam Gangopadhyay, Santhosh Pillai [Samsung], Susheel Sharma [Synopsys, Inc.]
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| | Singapore | Leakage Power Optimization Techniques in High-Speed Design
Author(s): Chin Hsiao Chia, Chen Yung Ching (Mediatek Singapore)
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| | | Enable Advanced Custom Designer Usage Model with P-Cells Creator and SDL Translation
Author(s): Nam Nguyen, Hieu Vu, Trung Nguyen, Minh Dinh, Nhan Phan (eSilicon Vietnam)
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| | UK | Making the most of FPGA Prototyping with the Universal Multi-Resource Bus (UMRBus)
Author(s): Paul Robertson [Broadcom] | | |
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| | | | Technical Committee Award Honorable Mention
France | Design Optimization and Formal Checking with Retiming Techniques
Author(s): Philippe Maneta [ST-Ericsson]
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| | Silicon Valley | Universal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure
Author(s): Ravi Ram, Warren Anderson, Shyam Sivakumar [Advanced Micro Devices, Inc.], Vijay Akkaraju [Synopsys, Inc.]
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| | | X-Propagation: An Alternative to Gate Level Simulation
Author(s): Adrian Evans, Julius Yam, Craig Forward
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| | UK | Timing Sign-off with Statistical Variability: Advanced On-Chip-Variation Modelling (AOCVM) - the theory and the practice
Author(s): Andrew Appleby, Touqeer Azam, Sonia Caldwell, Feng Hong, Mark Scoones [CSR] | | |
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