SNUG Awards |
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1st Place - Best Paper
Austin | Fault Grading via TetraMAX
Author(s): Anirudh Kadiyala, Vibhor Mittal, Atchyuth Gorti, Roystein Oliveira, Amit Pandey [Advanced Micro Devices, Inc.]
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| | Boston | Block Level Scan Insertion and Layered Approach to Transition ATPG Vector Generation
Author(s): Zahi Abuhamdeh, Vincent D'Alessandro [Silicon DFx, Inc.], Ramon Zuniga, Wayne Fang [ClariPhy Communications, Inc.]
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| | Canada | Minimum Metal ECO Routing Tips and Tricks
Author(s): Christopher Krueger [STMicroelectronics]
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| | France | Improve Verification Coverage of an Asynchronous Microcontroller with System Verilog - HSIM Co-simulation
Author(s): Bertrand Folco [Tiempo France]
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| | Germany | STA Fundamentals
Author(s): Sönke Grimpen [Infineon Technologies AG]
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| India
| IC Verification
User: Jitter Modeling in RTL Simulation - A Way to Ensure 1st Pass Silicon
Author(s): Vidit Babbar, Arvind Kumar, Kalpesh Shah, Vikas Lakhanpal [Texas Instruments]
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| | | IC Design: Signoff
User: Enabling Accurate Timing Budget Parameter Measurements for DDR Critical Paths
Author(s): Vidit Babbar [Texas Instruments]
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| | | IC Design: Synthesis & Test
User: Launch-Off Extra Shift (LOES) Transition Fault ATPG Methodology
Author(s): Milan Shetty, Swathi G, Rubin A. Parekhji [Texas Instruments]
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| | | FPGA Design
User: High-Speed Prototyping Techniques for Multi FPGA Prototypes of Complex SoCs
Author(s): Ameet Bagwe, Kanad Kanhere [Texas Instruments]
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| | | IC Physical Design
User: A Smart Step Density Flow for SoC Design
Author(s): Madan Lal, Veerakumar Pitchiah [Intel]
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| | | Custom Design and AMS Verification
User: Enabling Efficient AMS Co-simulation of Mixed-signal SoC with Analog and Power Management Integration
Author(s): Pooja Sundar, Lakshmanan Balasubramanian, Sandeep Tare [Texas Instruments], Charles Jiang [Synopsys]
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| | Israel | DFT architecture in multimedia design
Author(s): Gil Bouganim [DSP Group]
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| | San Jose | A Methodology for Creating Reusable Design Blocks Targeting FPGA Devices
Author(s): Phil Simpson, Jennifer Stephenson [Altera Corp.]
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| | Singapore | User Paper: Nanometer Low Power Challenges and Innovative Solutions for Chip Implementation
Author(s): Elisha Prashanth Sagar Nandavaram, Tze Haw Liew, [GLOBALFOUNDRIES], Wendy Chen [Synopsys]
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| | | User Paper: Customized ILM Flow for Implementation of Multivoltage Designs
Author(s): Jonathan Kok Ka Cheung, Goh Seng Han, Cheah Yew Sang [Intel]
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| | UK | Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks
Author(s): Theo Drane [Imagination Technologies Ltd.], Himanshu Jain [Synopsys] | | |
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| 2nd Place - Best Paper
Austin | DFTMAX and TetraMAX Adoption on AMD’s Bobcat Core
Author(s): Shaishav Parikh, Vance Threatt and Andy Halliday [Advanced Micro Devices, Inc]; Glenn Boyer, Lori Schramm [Synopsys, Inc.]
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| | Boston | Deployment of Full Custom Created Timing Shell Methodology to Hand-Off Macros from CD to ICC
Author(s): Michael Wagner [Lantiq D GmbH], Oliver Baer, Kurt Haun [Synopsys GmbH]
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| | Canada | A SystemVerilog Based ASIC DV Methodology
Author(s): Botros Dalou, Abdelhalim El-Aboudi, Dennis Em, Karim Khordoc, Catherine Leung, Markus Pugi, Apurv Shah [Cisco Systems]
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| | France | Efficient Standard Cell Characterization for GLOBALFOUNDRIES 28nm Technologies using a Star-RC and Liberty-NCX-based Flow
Author(s): Robert Siegmund, Ben Gullette, Andre Schulze [GLOBALFOUNDRIES]
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| | Germany | Multi-Mode Multi-Corner Synthesis in Design Compiler - A Must or just Nice to Have?
Author(s): Bernhard Riess [Infineon Technologies AG]
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| | San Jose | A Case for Adopting Galaxy Constraint Analyzer
Author(s): Richard Bishop [Advanced Micro Devices, Inc.]
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| | Singapore | User Paper: RVM Based CPU Model
Author(s): Noeme P. Mateo [BiTMICRO Networks]
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| | | User Paper: Channel-Based HIP Design Extraction Methodology
Author(s): Lee Yoke Sun, Chong, Han Yao [Intel]
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| | UK | Improving DFTMAX Compression Results in Latch Based Designs
Author(s): Richard Illman [Dialog Semiconductor] | | |
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| 3rd Place - Best Paper
Austin | Advanced Design Closure Techniques Using IC Compiler and Zroute on High Performance Designs at 32nm and Below
Author(s): Hongda Lu, Hyon Han, Yu-Ming Chiang [Advanced Micro Devices, Inc.]
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| | Boston | Improving Functional Gate Level Simulation Performance - A Case Study
Author(s): Joe Tompkins [Cavium Networks], Prathamesh Joshi [Synopsys Inc.]
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| | Canada | Hijacking Flops for Fun and Profit
Author(s): Martin Salomon [STMicroelectronics]
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| | France | Reconfigurable Wrapper Test Access Mechanism (TAM) in a Core Based DFT Strategy to Save Interconnect Test Time
Author(s): Isabelle Delbaere, Caroline Carin and Christophe Eychenne [ST-Ericsson]
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| | Germany | Mixed-Vth Leakage Optimization in the Final Design Stage - Experience with new Final-Stage Leakage Recovery Flow
Author(s): Robert Häußler, Mihael Murković [Lantiq Deutschland GmbH], Anders Lind [Synopsys GmbH]
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| | San Jose | Implementing a High-Speed, Low-Power ARM Cortex A9
Author(s): Bob Turner [Broadcom Corp.], Nish Balaji [Synopsys, Inc.]
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| | Singapore | User Paper: Synthesizable Verification IP to Stress Test System-on-Chip Emulation and Prototyping Platforms
Author(s): Xu Bing Tao, Jayaratnam Siva Shankar, Subramanian Shiva Shankar [Lantiq]
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| | | User Paper: Fast Forward with In-Design Lithography DFM using DRC+ in Synopsys ICC / ICV
Author(s): Cristopher Magalang, Edward Teoh, Sky YEO Wee Kwong [GLOBALFOUNDRIES]
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| | UK | Creation of an Embedded Temperature Sensor for Low Geometry Nodes using Custom Designer Mixed-Signal Design Flow
Author(s): Stephen Crosher, Neil Roberts [Moortec Semiconductor] | | |
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| | | | Technical Committee Award Honorable Mention
Austin | Advanced Design Closure Techniques Using IC Compiler and Zroute on High Performance Designs at 32nm and Below
Author(s): Hongda Lu, Hyon Han, Yu-Ming Chiang [Advanced Micro Devices, Inc.]
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| | Boston | The Impulse Response - "Fingerprint" for SERDES Channel Characterization
Author(s): Johann Nittmann, Frank Corcoran [Cavium Networks]
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| | France | UPF Power State Table Verification Methodology using MVSIM
Author(s): Christophe Clavel [ST-Ericsson]
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| | Germany | Multi-Mode Multi-Corner Synthesis in Design Compiler - A Must or just Nice to Have?
Author(s): Bernhard Riess [Infineon Technologies AG]
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| | San Jose | A Case for Adopting Galaxy Constraint Analyzer
Author(s): Richard Bishop [Advanced Micro Devices, Inc.]
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| | | AMD Latch-based Design Methodologies with TetraMAX ATPG
Author(s): Martin Amodeo, Dwight Elvey [Advanced Micro Devices, Inc.], Aurelia De Colle, Tim Ayres [Synopsys, Inc.]
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| | Taiwan | An Efficient and Accurate Instance-based Power Characterization Method for Nano-meter Memory Compiler
Author(s): David Wu, Goldberg Lin, Willis Shih, Steve Tsai [Faraday]
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| | | Using VMM RAL to Effectively Verify Complex User-specific Registers
Author(s): Yung-Jen Chen [Realtek]
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| | UK | Techniques for Achieving High Test Quality using DFT Compiler/DFTMAX Compression and TetraMAX
Author(s): Derya Rutten-Eker [ST-Ericsson] | | |
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