SNUG Awards 

1st Place - Best Paper
Austin
Database Schema for Very High Bandwidth Coverage Collection
Author(s): Mike Burns, James Roberts, Ray Voith [Oracle]
PaperPresentation


BostonExperiences with PrimeTime ECO capabilities
Author(s): Bruce Zahn [LSI Corp.]
PaperPresentation


CanadaICC Tips and Tricks
Author(s): Christopher Krueger [STMicroelectronics Inc.]
PaperPresentation


FranceGenerating Low-Power ATPG Patterns using a Shift Power Budget
Author(s): Pascal BLANC [STEricsson], Saverio Graniello [STMicroelectronics], Philippe ROSSANT [Synopsys]
PaperPresentation Webinar


GermanyExperiences with ICC Black Box Flow
Author(s): Farid Labib, Herbert Preuthen [LSI, Corp.]
PaperPresentation Webinar


India
IC Verification
Verification of Mixed-Signal Designs using System-Verilog Assertions in Co-simulation
Author(s): Somasunder Kattepura Sreenath, Sandeep Tare [Texas Instruments]
PaperPresentation


IC Design: Signoff
On Analysis & Development of Sign-Off Quality Clock Gating Effectiveness Metrics
Author(s): Jairam Sukumar, Udayakumar H, Rajagopal K A [Texas Instruments], Maria Tovey [Synopsys]
PaperPresentation


Custom Design and AMS Verification
Finding Power-up Issues in Memories using ESP-CV
Author(s): Premkumar, Sanjeev Suman [Texas Instruments], Rakesh Shenoy [Synopsys]
PaperPresentation


IC Design: Synthesis and Test
Achieving massive multi-site testing without compromising on the test quality - Is Serializer the solution?
Author(s): Malav Shah, Claus kuntzsch, Nikolaus Mittermaier [Texas Instruments]
PaperPresentation


IC Design: Physical Design
Physical Implementation Challenges for a Very Large, Channel-Dominated, Multi-Clock Design in 45nm
Author(s): Namit Varma, Madhusudan Rajagopal, Veena Radhakrishnan [Achronix]
PaperPresentation


FPGA and System Design
Efficient Prototyping of Multi-Million Gate SoCs using Accelerated Synthesis Feature of Synplify Premier
Author(s): Sabyasachi Dey, Amit Siroya [Qualcomm]
PaperPresentation


San JoseConstant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design
Author(s): Alvin Loke, Dru Cabler, Chad Lackey, Tin Tin Wee, Bruce Doyle [Advanced Micro Devices, Inc.], Zhi-Yuan Wu [GLOBALFOUNDRIES], Reza Moallemi [Synopsys, Inc.]
PaperPresentation


SingaporeUser Paper 8: Making DFM Sense In Your Design
Author(s): Sky Yeo Wee Kwong [GLOBALFOUNDRIES]
PaperPresentation


UKScan Compression Without "Scan Compression"
Author(s): Richard Illman , Hans-Martin von Staudt [Dialog Semiconductor Ltd.]
PaperPresentation Webinar

2nd Place - Best Paper
Austin
Reducing Flip-Flop Power in Hexagon Core Design and use of the Flop-Merging
Author(s): Mohammed Shahid Imam, Martin Saint-Laurant [Qualcomm]
PaperPresentation


BostonAchieving Faster Turnaround Time and Better QOR using Compile Points and Design Preservation Flow for Virtex Devices
Author(s): Mike Spofford, Kate Kelly [Xilinx Inc.]
PaperPresentation


CanadaStick a fork in It: Applications for SystemVerilog Dynamic Processes
Author(s): David Long, Doug Smith [Doulos]
PaperPresentation


FranceUPF Front-End Experience on an Actual 45nm Design
Author(s): Guilhem Caubit [ST-Ericsson]
PaperPresentation


GermanyEffective Post Layout Verification of AMS Designs at 28nm by means of StarRC Extracted Views
Author(s): Hendrik Mau [GlobalFoundries]
PaperPresentation Webinar


San JoseHold is Not Setup (Derate is Not OCV)
Author(s): Gerard M Blair [LSI Corp.]
PaperPresentation


SingaporeUser Paper 5: Clocking Methodology for Performance Verification in SoC Design
Author(s): Tan Hon-Ee [Intel Corporation]
PaperPresentation


UKExploiting the TLM-2 Features of VMM 1.2
Author(s): John Aynsley [Doulos Ltd.]
PaperPresentation

3rd Place - Best Paper
Austin
Flop Clustering Algorithms to Reduce Clock Power
Author(s): Hyon Han, Hongda Lu [Advanced Micro Devices], Tom Felske [Synopsys, Inc.]
PaperPresentation


BostonThe Verilog Preprocessor: Force for `Good and `Evil
Author(s): Wilson Synder [Cavium Networks]
PaperPresentation


CanadaEnd to End Test Optimization Using IJTAG
Author(s): Mike Olson, Peter Meyer [DA Integrated] Don Skinner [Synopsys, Inc.]
PaperPresentation


FranceHow Design Compiler Graphical Can Help Solve Floorplanning Issues
Author(s): Laurent Besson [STEricsson]
PaperPresentation


GermanyHitchhikers Guide to Structural and Functional Coverage Merging and Mapping with VCS, SystemVerilog and VMM
Author(s): Jacob Andersen, Benny Andersson, Peter Jensen [SyoSil ApS]
PaperPresentation


San Jose"There’s a better way to do it!" - Simple DC/PT Tricks That Can Change Your Life.
Author(s): Paul Zimmer [Zimmer Design Systems]
PaperPresentation


SingaporeUser Paper 2: PrimeTime Advanced OCV - Another Way to Performance Confidence
Author(s): Prashanth Sagar [GLOBALFOUNDRIES]
PaperPresentation


UKScan Compression with Limited Pin Access
Author(s): Chris Dodd [Wolfson Microelectronics plc]
Presentation Webinar

Best First-Time Presenter
Boston
Achieving Faster Turnaround Time and Better QOR using Compile Points and Design Preservation Flow for Virtex Devices
Author(s): Mike Spofford, Kate Kelly [Xilinx Inc.]
PaperPresentation


San JoseConstant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design
Author(s): Alvin Loke, Dru Cabler, Chad Lackey, Tin Tin Wee, Bruce Doyle [Advanced Micro Devices, Inc.], Zhi-Yuan Wu [GLOBALFOUNDRIES], Reza Moallemi [Synopsys, Inc.]
PaperPresentation

Best Paper Award
Israel
Clock Tree implementation techniques - a comparative analysis
Author(s): Ina Shtarkberg [Intel Corp.]
PaperPresentation Webinar


TaiwanLow power CTS technique using optimal ICG placement
Author(s): 陳軍, Dhaval Bhatia,王孝誠, 張裕東 [Mediatek]
PaperPresentation


Scan Test Power Reduction Using Power-aware ATPG
Author(s): Pei-Ying Hsueh, Shuo-Fen Kuo, Ying-Yen Chen, Jin-Nung Lee, Chi-Feng Wu [Realtek]
PaperPresentation


ESL Virtual Platform for System Performance Enhancement
Author(s): Jen-Chieh Yeh [ITRI]
Presentation

Technical Committee Award
Canada
ICC Tips and Tricks
Author(s): Christopher Krueger [STMicroelectronics Inc.]
PaperPresentation


FranceHierarchical Adaptive Scan Synthesis and Core Wrappers Methodology Combined to Reduce Power During Scan Test
Author(s): Christophe Eychenne, Isabelle Delbaere, Caroline Carin [ST-Ericsson]
PaperPresentation


Germany"What gets measured gets done" - Predictable verification with VMM Planner
Author(s): Tobias Leisgang [Texas Instruments]
PaperPresentation


IsraelSimulation Acceleration using Multicore Systems
Author(s): Yechiel Hefetz, Avi Green, Itai Yarom [Intel], Eran Mudayi [Jerusalem College of Technology]
PaperPresentation


Speeding PrimeTime's reports analysis
Author(s): Yossi Rindner, Ohad Meshulam [ASICServe]
PaperPresentation


San JoseClock Power Reduction-Analysis Metrics and Power Reduction Techniques
Author(s): Avishek Panigrahi, Arvind Parihar [MIPS Technologies, Inc.]
PaperPresentation


UKPhysical Design Practices for a 1 GHz SoC Block on 32nm
Author(s): Rashid Iqbal [Intel Shannon]
PaperPresentation


Technical Committee Award Honorable Mention
Austin
Explore Your Design Visually Using PrimeTime & Gnuplot
Author(s): John Paz, Sameer Shah and Colin MacDonald [Broadcom Corp.]
PaperPresentation


BostonCustomizing VMM Transactors with Options
Author(s): Joe Manzella [LSI Corp.]
PaperPresentation


FranceICC-IC Validator and ICC-PrimeRail New ‘In-Design’ Features: The ST/APG MSR 65nm) Testcase
Author(s): Salvatore D'Argenio [STMicroelectronics], Giuseppe Contarino [Synopsys]
PaperPresentation


GermanyMassive Test Cost Reduction by Advanced SCAN Testing
Author(s): Claus Kuntzsch, Malav Shah [Texas Instruments] Nikolaus Mittermaier [Synopsys, GmbH]
PaperPresentation


San JoseReusable UPF for Multi-Voltage Design & Handling Analog Macros in Power Subsystem
Author(s): Krishna Vittala [Microchip Technology Inc.]
PaperPresentation


Interoperable Testbenches using VMM TLM
Author(s): Asif Jafri [Verilab Inc.], Nasib Naser [Synopsys, Inc.]
PaperPresentation


TaiwanLow Power Design & Verification for PACDSP
Author(s): C. Y. Liao [ITRI]
PaperPresentation


Methodology of Executable Verification Plan
Author(s): Shang-Wei Tu [Sunplus]
PaperPresentation


UKScan Compression Without "Scan Compression"
Author(s): Richard Illman , Hans-Martin von Staudt [Dialog Semiconductor Ltd.]
PaperPresentation Webinar