SNUG Awards 

1st Place - Best Paper
Boston		SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification
Author(s): Clifford Cummings [Sunburst Design, Inc.]
PaperPresentation

EuropeAutomated Development of Schematic Documentation for Web-Delivery
Author(s): Kees Timmermans [TTA-International]
Presentation

India
Physical Design and Sign-Off
Challenges in Crosstalk-Aware Hierarchical STA for Multi-Million Gate VoIP SoC
Author(s): Aakash Agrawal, Subrangshu Das, Shailendra Dhuri, [Texas Instruments]
PaperPresentation

Synthesis and Test
Dynamic Shift Frequency Scaling Of ATPG Patterns
Author(s): Aditya Ramachandran [Open-Silicon Research Private Limited]
PaperPresentation

Verification
Usage of VMM to Address Gigabit Switch Verification Challenges
Author(s): Yogesh Mittal, Neeraj Chandak, Parag Goel [Transwitch]
PaperPresentation

AMS
Complex Signal Integrity Simulations for GPIOs using HSIM Hierarchical Flow
Author(s): Rakesh Sawant, Nagarathinam Senthil [Qualcomm]
PaperPresentation

IsraelBone: Custom Design Sizing Optimization Flow using NanoTime
Author(s): Gideon Reisfeld, Gregory Zabolotov [Intel]
PaperPresentation

San JoseWhere Have all the Phases Gone? Using Multiclock Propagation in PrimeTime
Author(s): Paul Zimmer [Zimmer Design Systems]
PaperPresentation

SingaporeHigh Quality Partition Boundary Modeling for Hierarchical Based Design
Author(s): Mr Yew, Edwin Hong Wei, Mr Tee, Kok Tiong [Intel Corporation]
PaperPresentation

TaiwanLow Power Emphasized PAC DSP Implementation
Author(s): Chiao-Ling Lung [Industrial Technology Research Institute]
Presentation

SoC Verification using VMM-Methodology
Author(s): Charles C. C. Liu [TSMC]
Presentation
2nd Place - Best Paper
Boston		Creating Stimulus and Stimulating Creativity: Using the VMM Scenario Generator
Author(s): Jonathan Bromley [Doulos Ltd.]
PaperPresentation

EuropeRegression & Random Sims: Techniques & Recommendations
Author(s): Dan Steinberg [Integrated Device Technology]
PaperPresentation

San JoseGotcha Again - More Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering], Chris Spear [Synopsys, Inc.]
PaperPresentation

SingaporeImproving Place and Route Flow Efficiency for Complex Design
Author(s): Teh Eng Keong, Vivian Teh Lin Hwei, Nah Bee Keng, Chin Chuang Shan [Intel Corporation]
PaperPresentation

TaiwanNew IP Deliverables for a Unified IP Simulation/STA Flow Using ILM+
Author(s): Ean Tzeng, J.D. Pan [Faraday Technology Corporation]
Presentation
3rd Place - Best Paper
Boston		The Ten Edits I Make Against Most IP
Author(s): Wilson Snyder [SiCortex, Inc.]
PaperPresentation

EuropeStandardizing Verification IP Reuse by Introducing SystemVerilog Verification Components
Author(s): Jacob Andersen, Peter Jensen, Stig Kofoed [SyoSil]
PaperPresentation

San JoseDon't Panic! What to do when Formality Doesn't Give You the "VERIFICATION SUCCEEDED" Message on the First Try.
Author(s): Leah Clark [Broadcom Corp.], Matt Dittrich [Synopsys, Inc]
PaperPresentation
Best First-Time Presenter
Boston		From Validation to Generation: Making Hercules do the Heavy Lifting
Author(s): Dale Donchin [Analog Devices, Inc.]
PaperPresentation

EuropeMix And Match of Flat, Hierarchical and Pseudo-Hierarchical Approaches for Different Steps of a Design Flow
Author(s): Juergen Dirks [LSI GmbH]
PaperPresentation

San JoseHow to Verify and Integrate Mixed Signal Third-Party IP
Author(s): Steven M Waldstein [Tundra Semiconductor], Navraj S Nandra [Synopsys, Inc.]
PaperPresentation
Technical Committee Award
Boston		When Floorplans Attack: How To Balance Routing, Timing and Area on Problematic Designs
Author(s): John Vargas [Unisys], Peter Jarvis [Synopsys, Inc.]
PaperPresentation

EuropeSmall Delay Defect Testing
Author(s): Roberto Mattiuzzo, Saverio Graniello [STMicroelectronics], Salvatore Talluto, Alfredo Conte, Adam Cron [Synopsys Inc.]
PaperPresentation

San JoseImplementation of an AHB Bus Subsystem with SystemVerilog
Author(s): Eliseu C Filho [Starport Systems, Inc.], Jim Maryoung [Synopsys, Inc.]
PaperPresentation

Technical Committee Award Honorable Mention
Boston		A SystemVerilog Coverage Driven Test Generator for Processor Design Verification
Author(s): David Brownell, Tushar Ringe [Analog Devices]
PaperPresentation

The Ten Edits I Make Against Most IP
Author(s): Wilson Snyder [SiCortex, Inc.]
PaperPresentation

EuropeEasing the Pain of Sign-off Timing and SI Closure using PrimeTime Distributed Multi-Scenario Analysis
Author(s): Stuart Vernon [Imagination Technologies Ltd], Simon Bloyce [Synopsys Inc.]
PaperPresentation

Analog Simulations of High-Speed Serial Chip-to-Chip Links with HSPICE
Author(s): Christoph Werner [Nokia Siemens Networks], David Sebastio [Texas Instruments]
PaperPresentation

San JoseGotcha Again - More Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering], Chris Spear [Synopsys, Inc.]
PaperPresentation

Where Have all the Phases Gone? Using Multiclock Propagation in PrimeTime
Author(s): Paul Zimmer [Zimmer Design Systems]
PaperPresentation


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