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| User Papers and Presentations |
| A2 - User Session & Tutorial: Low Power |
An ARM Cortex-M0 for Energy Harvesting Systems: A Novel Application of UPF with Synopsys Galaxy Platform
Author(s): Jatin Mistry [University of Southampton], James Myers [ARM] |
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| A3 - Tutorial & User Session: Front End Implementation & Signoff I |
Converting Existing Software to Hardware using SynphonyCC: A Case Study of an Open Source Connect-6 Solver
Author(s): Sumanta Chaudhuri, Peter Y. K. Cheung [Imperial College London] |
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| A4 - Tutorial & User Session: Verification I |
Easier RAL - All You Need to Know About the UVM Register Layer
Author(s): Doug Smith, Dr. David Long [Doulos] |
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| A6 - User Session & Tutorial: Design for Test |
DFT for Fragmented Digital Blocks in Mixed Signal Designs (2nd Place - Best Paper)
Author(s): Richard Illman [Dialog Semiconductor] |
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| B1 - User Session & Tutorial: FPGA Implementation and FPGA-based Prototyping II |
Experiences Porting a Design from an ASIC Implementation Flow to an FPGA Flow
Author(s): Mike Dunk [Infineon Technologies] |
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| B3 - Tutorial & User Session: Front End Implementation & Signoff II |
Applying Multi Corner Multi Mode Methodology on an Interface IP
Author(s): Seyda Aygin [Ericsson Microelectronic Design Center] |
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| B4 - User Session: Verification II |
A Beginner's Guide to Using SystemC TLM-2.0 IP with UVM
Author(s): Dr David Long, John Aynsley, Doug Smith [Doulos] |
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I Spy with My VPI: Monitoring Signals by Name, for the UVM Register Package and More (Technical Committee Award)
Author(s): Jonathan Bromley [Verilab] |
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| B5 - User and Tutorial: Analog Mixed-signal / Full Custom Design II |
An Alternative Approach to Connect Modules in Verilog-AMS
Author(s): Peter Grove [Wolfson Microelectronics] |
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| C1 - User Session & Tutorial: FPGA Implementation and FPGA-based Prototyping III |
Making the most of FPGA Prototyping with the Universal Multi-Resource Bus (UMRBus) (3rd Place - Best Paper)
Author(s): Paul Robertson [Broadcom] |
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| C2 - User Session & Tutorial: Back End Implementation II |
Reducing Silicon Real Estate Through Layer Aware Buffer Optimisation
Author(s): Nigel Hughes [Intel] |
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| C3 - User Session & Tutorial: Front End Implementation & Signoff III |
Timing Sign-off with Statistical Variability: Advanced On-Chip-Variation Modelling (AOCVM) - the theory and the practice (Technical Committee Award Honorable Mention)
Author(s): Andrew Appleby, Touqeer Azam, Sonia Caldwell, Feng Hong, Mark Scoones [CSR] |
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| C4 - User Session & Tutorial: Verification III |
Property Checking of Datapath using Word-Level Formal Equivalency Tools (1st Place - Best Paper, Best Paper Award)
Author(s): Theo Drane [Imagination Technologies], Himanshu Jain [Synopsys, Inc] |