SNUG UK 2012 Proceedings

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Complete Proceedings


User Papers and Presentations
A2 - User Session & Tutorial: Low Power
An ARM Cortex-M0 for Energy Harvesting Systems: A Novel Application of UPF with Synopsys Galaxy Platform
Author(s): Jatin Mistry [University of Southampton], James Myers [ARM]
PaperPresentation

A3 - Tutorial & User Session: Front End Implementation & Signoff I
Converting Existing Software to Hardware using SynphonyCC: A Case Study of an Open Source Connect-6 Solver
Author(s): Sumanta Chaudhuri, Peter Y. K. Cheung [Imperial College London]
PaperPresentation

A4 - Tutorial & User Session: Verification I
Easier RAL - All You Need to Know About the UVM Register Layer
Author(s): Doug Smith, Dr. David Long [Doulos]
PaperPresentation

A6 - User Session & Tutorial: Design for Test
DFT for Fragmented Digital Blocks in Mixed Signal Designs (2nd Place - Best Paper)
Author(s): Richard Illman [Dialog Semiconductor]
PaperPresentation

B1 - User Session & Tutorial: FPGA Implementation and FPGA-based Prototyping II
Experiences Porting a Design from an ASIC Implementation Flow to an FPGA Flow
Author(s): Mike Dunk [Infineon Technologies]
PaperPresentation

B3 - Tutorial & User Session: Front End Implementation & Signoff II
Applying Multi Corner Multi Mode Methodology on an Interface IP
Author(s): Seyda Aygin [Ericsson Microelectronic Design Center]
PaperPresentation

B4 - User Session: Verification II
A Beginner's Guide to Using SystemC TLM-2.0 IP with UVM
Author(s): Dr David Long, John Aynsley, Doug Smith [Doulos]
PaperPresentation

I Spy with My VPI: Monitoring Signals by Name, for the UVM Register Package and More (Technical Committee Award)
Author(s): Jonathan Bromley [Verilab]
PaperPresentation

B5 - User and Tutorial: Analog Mixed-signal / Full Custom Design II
An Alternative Approach to Connect Modules in Verilog-AMS
Author(s): Peter Grove [Wolfson Microelectronics]
PaperPresentation

C1 - User Session & Tutorial: FPGA Implementation and FPGA-based Prototyping III
Making the most of FPGA Prototyping with the Universal Multi-Resource Bus (UMRBus) (3rd Place - Best Paper)
Author(s): Paul Robertson [Broadcom]
PaperPresentation

C2 - User Session & Tutorial: Back End Implementation II
Reducing Silicon Real Estate Through Layer Aware Buffer Optimisation
Author(s): Nigel Hughes [Intel]
PaperPresentation

C3 - User Session & Tutorial: Front End Implementation & Signoff III
Timing Sign-off with Statistical Variability: Advanced On-Chip-Variation Modelling (AOCVM) - the theory and the practice (Technical Committee Award Honorable Mention)
Author(s): Andrew Appleby, Touqeer Azam, Sonia Caldwell, Feng Hong, Mark Scoones [CSR]
PaperPresentation

C4 - User Session & Tutorial: Verification III
Property Checking of Datapath using Word-Level Formal Equivalency Tools (1st Place - Best Paper, Best Paper Award)
Author(s): Theo Drane [Imagination Technologies], Himanshu Jain [Synopsys, Inc]
PaperPresentation

Publication Only
Non-Rectilinear FRAM Generation
Author(s): Chai Siew Fong, Ang Boon Ching, [Intel]
Paper

Tutorials
A1 - Tutorial: FPGA Implementation and FPGA-based Prototyping I
Synplify Pro/Premier Technology Enhancements for Next Generation High Capacity Designs
Author(s): Andy Jolley [Synopsys Ltd]
Tutorial

A2 - User Session & Tutorial: Low Power
Formality Low Power Equivalence Checking with UPF
Author(s): Tom Ryan [Synopsys Ltd]
Tutorial

A3 - Tutorial & User Session: Front End Implementation & Signoff I
Galaxy RTL: Design Compiler Family Update
Author(s): Rod Carroll [Synopsys Ltd]
Tutorial

A4 - Tutorial & User Session: Verification I
Next Generation VIP - UVM Methodology
Author(s): Fabian Delguste [Synopsys France]
Tutorial

A5 - Tutorial & User Session: Analog Mixed-signal / Full Custom Design I
Mixed-Signal Behavioural Models : A Necessary Evil
Author(s): Chris Brown [Mixed-Signal Verification Consultant]
Tutorial

Recent Developments in Field of SPICE and fastSPICE Circuit Simulation
Author(s): Damian Roberts [Synopsys Ltd.]
Tutorial

A6 - User Session & Tutorial: Design for Test
Galaxy Test and STAR Memory System Updates
Author(s): Dave Johnson [Synopsys Ltd], Yervant Zorian [Synopsys Inc]
Tutorial

B1 - User Session & Tutorial: FPGA Implementation and FPGA-based Prototyping II
Effective Strategies for Bringing Up and Debugging an FPGA-based Prototype
Author(s): Frank McMillan [Synopsys Ltd]
Tutorial

B2 - Tutorials: Back End Implementation I
Creating Multi-IO Ring Die Using IC Compiler
Author(s): Colin Davidson [Synopsys Ltd]
Tutorial

Dealing with Metal Fill in 28nm ECO Extraction Flows
Author(s): Clay McDonald [Synopsys]
Tutorial

Double-Patterning Aware Extraction & Signoff at 20nm
Author(s): Clay McDonald [Synopsys]
Tutorial

B3 - Tutorial & User Session: Front End Implementation & Signoff II
Getting the Most from Synthesis to Improve Your Datapath QoR
Author(s): Reto Zimmermann [Synopsys GmbH]
Tutorial

B5 - User and Tutorial: Analog Mixed-signal / Full Custom Design II
The Generation of Timing Views for Analogue IP Delivery
Author(s): Andy Milne, Synopsys Ltd. [Synopsy Ltd.]
Tutorial

B6 - Tutorial & User-Tutorial Session: Lynx Design System
A Complete Audio IP Subsystem for Your SoC in Minutes
Author(s): Raza Malik [Synopsys Inc.]
Tutorial

Taking the Cost and Guesswork out of Building a Technology Proven Flow
Author(s): Richard White [PicoChip]
Tutorial

C1 - User Session & Tutorial: FPGA Implementation and FPGA-based Prototyping III
Clash of the Titans: Hybrid Prototyping, the Combined Strength of both Virtual and FPGA-Based Prototyping
Author(s): Michael Posner [Synopsys Inc]
Tutorial

C2 - User Session & Tutorial: Back End Implementation II
Faster Top-Level Closure With Transparent Interface Optimization
Author(s): Jon Dawes [Synopsys Ltd]
Tutorial

C3 - User Session & Tutorial: Front End Implementation & Signoff III
ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Author(s): Simon Bloyce [Synopsys Ltd]
Tutorial

C4 - User Session & Tutorial: Verification III
Debugging Low-Power Simulations
Author(s): Bhavesh Patel [Synopsys, Ltd]
Tutorial

C5 - Tutorials: Analog Mixed-signal / Full Custom Design III
A Timing Shell Approach to Integrating Mixed-signal Macros into a Place and Route Flow
Author(s): Damian Roberts [Synopsys, Ltd]
Tutorial

CustomExplorer Ultra – Meeting the Mixed-signal Verification Challenge
Author(s): Paul Chapman [Synopsys, Ltd]
Tutorial

C6 - Tutorials: Design IP
Best Practices for Implementing Memories and Libraries to Deliver Superior PPA
Author(s): Zaka Bhatti [Synopsys, Inc]
Tutorial

The Evolving Integrated Communication AFE
Author(s): Luis Matias [Synopsys Portugal]
Tutorial