SNUG UK 2011 Proceedings

A2 - User Session: Back End Implementation I

ICC Hierarchy Insertion to Allow Simulation of Digital Sub-Blocks in an Analogue Environment
Author(s): James Lutley [Semtech Ltd.]

Using Synopsys IC Compiler for DFM optimization at 28nm
Author(s): Rainer Mann, Ulrich Hensel, Vito Dai, Shobhit Malik [GLOBALFOUNDRIES]

A3 - User Session: Design for Test I

Improving DFTMAX Compression Results in Latch Based Designs (2nd Place - Best Paper)
Author(s): Richard Illman [Dialog Semiconductor]

Retention Cell Test
Author(s): Shane Gallagher [Analog Devices]

A4 - Tutorial & User Session: Verification I

My First Testbench Using UVM
Author(s): Yassine Eben Aimine [Synopsys]

Tackling Memory Usage and CPU Time in a Large VMM VIP Project - Lessons Learned
Author(s): Andrew Kinane, Vishal Patel [CréVinn Teoranta]

A5 - Tutorial & User Session: Analog Mixed-Signal / Full Custom Design I

Creation of an Embedded Temperature Sensor for Low Geometry Nodes using Custom Designer Mixed-Signal Design Flow (3rd Place - Best Paper)
Author(s): Stephen Crosher, Neil Roberts [Moortec Semiconductor]

B3 - User Session & Tutorial: Design for Test II

Techniques for Achieving High Test Quality using DFT Compiler/DFTMAX Compression and TetraMAX (Technical Committee Award Honorable Mention)
Author(s): Derya Rutten-Eker [ST-Ericsson]

B4 - User Session: Verification II

Forks that Cut It: Applications for SystemVerilog Dynamic Processes
Author(s): David Long, Doug Smith [Doulos]

FPGA Verification – Bridging the Gap Between Simulation, and Validation with VCS, C-DPI and TCL
Author(s): Paul Furlong, Kevin Hyland, Niamh Scott [Intune Networks]

C2 - User Session & Tutorial: Low Power

What has UPF ever done for us?
Author(s): Michael Lynch, Colm O'Doherty [Analog Devices]

C3 - User Session: Design Verification

Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks (1st Place - Best Paper)
Author(s): Theo Drane [Imagination Technologies Ltd.], Himanshu Jain [Synopsys]

PrimeTime as an implementation tool
Author(s): Frank Vaneerdewegh [ST-Ericsson]

C4 - User Session & Tutorial: IP and Systems

CHIPS and iPEAS - It’s not Mushy
Author(s): Jonathan Young [Synopsys]

C5 - User Session & Tutorial: Analog Mixed-Signal / Full Custom Design III

AMS Verification with SystemVerilog (Technical Committee Award)
Author(s): Graeme Nunn [Calvatec]

Publication Only

Leakage Power Optimization Flow for Low Power Designs
Author(s): Ramy Gamal [Dubai Circuit Design]

Synthesizable Verification IP to Stress Test System-on-Chip Emulation and Prototyping Platforms
Author(s): Xu Bing Tao, Jayaratnam Siva Shankar, Subramanian Shiva Shankar [Lantiq]

Tutorials

A1 - Tutorial & Combo Session: FPGA Implementation and FPGA-based prototyping I

Latest Synthesis Technologies and Techniques for High-Capacity FPGA Designs
Author(s): Andy Jolley, Frank McMillan [Synopsys]

A5 - Tutorial & User Session: Analog Mixed-Signal / Full Custom Design I

Using ICC in an Analogue Top Custom Designer Flow
Author(s): Andy Milne [Synopsys]

B1 - Tutorials: FPGA Implementation and FPGA-based Prototyping II

From Programmable Logic to Programmable Platforms
Author(s): Jason Beil [Xilinx Inc.]

Synopsys’ FPGA-Based Prototyping Solution Introduction
Author(s): Mick Posner [Synopsys]

B2 - Tutorial: Back End Implementation II

IC Compiler Implementation Flow For Large Designs Using MCMM
Author(s): Simon Koval, Frank De Meersman [Synopsys Ltd.]

B3 - User Session & Tutorial: Design for Test II

Volume Diagnostics: The Key to Faster Yield Ramp at Nanometer Node Technologies
Author(s): Christophe Suzor [Synopsys France]

B5 - Tutorials: Analog Mixed-Signal / Full Custom Design II

Getting the Best Out of XA
Author(s): Peter Thompson [Synopsys]

VCS AMS-Testbench, a Unified Verification Methodology for Mixed-Signal Blocks
Author(s): Fabian Delguste [Synopsys]

C1 - Tutorials: FPGA Implementation and FPGA-based Prototyping III

Partitioning and Reconnecting
Author(s): Joseph Marceno, Doug Amos [Synopsys]

UMRBus for Advanced Prototyping Capabilities
Author(s): Andy Jolley [Synopsys]

C2 - User Session & Tutorial: Low Power

Successful Formality Equivalency Checking for Low Power Designs - Tips From the Experts
Author(s): Tom Ryan [Synopsys]

C4 - User Session & Tutorial: IP and Systems

Open Source SW on the DesignWare ARC Processor Architecture
Author(s): Jos Hegge [Synopsys], Mischa Jonker [Synopsys Netherlands]

C5 - User Session & Tutorial: Analog Mixed-Signal / Full Custom Design III

Introducing CustomExplorer Ultra, a Comprehensive Mixed-Signal Simulation Environment
Author(s): Dwayne Holst [Synopsys]