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| User Papers and Presentations |
| FA1 - Low Power Implementation |
A UPF Low Power Tapeout Project Case Study
Author(s): JianPing Chang [Progate Group Corp.] |
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Improving Turn-Around Time in Gas Station Design by Us-ing IC Compiler UPF Mode
Author(s): Yun-ChihChang [Realtek] |
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Low Power ARM CortexA9 Using ICC UPF Flow
Author(s): Tony Ku [TSMC] |
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UPF-Based MV+MCMM ImplementationExperience
Author(s): Jackie Wu [HT mMobile] |
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| FA2 - Functional Verification/Low Power |
Experience on Low Power Verification
Author(s): Vincent Lin [Via Labs] |
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Making Compile Faster using VCS Partition Compile
Author(s): Xiao-Cheng An, Chung-Yuan Cheng, Yung-Jen Chen [Realtek] |
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Techniques of Automatic Functional Coverage Convergence (Best Paper Award)
Author(s): Shang-WeiTu [Sunplus] |
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Using VMM RAL to Effectively Verify Complex User-specific Registers (Technical Committee Award Honorable Mention)
Author(s): Yung-Jen Chen [Realtek] |
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| FA3 - Fast SPICE |
Adv. node SRAM Design Verification with CustomSim(XA)
Author(s): Hsin-Wen Chen [UMC] |
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An Efficient and Accurate Instance-based Power Characterization Method for Nano-meter Memory Compiler (Technical Committee Award Honorable Mention)
Author(s): David Wu, Goldberg Lin, Willis Shih, Steve Tsai [Faraday] |
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Hybrid IR/EMAnalysis Flow with EM Rule Extension
Author(s): Gary Chan 詹偉閔 [TSMC] |
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Simulation Success with HSIM in DDR DRAM Design
Author(s): Jason Pang [ETRON] |
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| FB1 - Low Power Implementation/ DFM |
Proteus LRC Evaluate in OPC Application
Author(s): Jiunhau Fu [Nanya] |
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| FB2 - System Level Solution/Low Power |
Customized Programmer’s View Multi-DSP Virtual Platform for SW Development
Author(s): Bruce Huang [ITRI] |
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System Power Analysis with DVFS on ESL Virtual Platform (Best Paper Award)
Author(s): Wen-TsanHsieh [ITRI] |
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| FB3 - Fast SPICE/ESP |
Custom Memory Formal Checking methodology in using ESP Shell
Author(s): Chunhao, Charlie Yu [TSMC] |
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HSIM Flash Cell Model for NAND Flash
Author(s): Rocky Lo [Macronix] |
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| TA1 - Physical Implementation/Verification |
Explore Optimization Opportunities with Lynx Design System
Author(s): Kerwin Fu [Himax] |
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Tackling 1GHz Dual-core Cortex A9 using Synopsys ICC tool (Best Paper Award)
Author(s): CC Mao [Global Unichip] |
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TSMC Reference Flow 12.0 Overview
Author(s): Wen-Hao Chen [TSMC] |
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UMC-Synopsys 40nm UPF Low Power Reference Flow
Author(s): Zed Chiu [Global Unichip] |
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| TA2 - Synthesis/STA/Test |
Experience Sharing on Fast Timing ECO Using PrimeTime
Author(s): 孫維敏張進朝陳玉娟 [Nuvoton] |
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Exploring DFT Methodologies for 3D Integration Chip
Author(s): Chen-An Chen, Yee-Wen Chen, Ming-Hsueh Wu, Kun-Lun Luo, Liang-Chia Cheng [ITRI] |
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Solving Congestion and Improving Correlation using Design CompilerGraphical with Physical Guidance
Author(s): Jason Wang [Novatek], George Wang [Synopsys] |
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| TA3 - Fast Prototyping |
HDTV Prototyping Performance Comparisons Between HAPS54 and HAPS64
Author(s): Jovi Su [SiS] |
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Success of DSP Prototype with HAPS51T
Author(s): Chih-Wei Huang [ITRI] |
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| TB1 - Physical Verification/Implementation |
Apply ICC Methodology in Implementation Flow
Author(s): Alan Hsu [SiS] |
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| TB3 - Fast Prototyping/Certify/IP |
Certify in multi-FPGA partition
Author(s): Gary Tseng [Altek] |
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RTL Partition for HAPS with Certify -- Rapid Prototyping on Multi-FPGA
Author(s): Feng-Chi Chen [ITRI] |