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SNUG Singapore 2010 Proceedings
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Complete Proceedings
User Papers (zip file)
User Presentations (zip file)
Synopsys Presentations (zip file)
User Papers and Presentations
User Paper 1: Effective Design Partitioning & Floorplanning for Complex SoC
Author(s):
Avinash Rajah [Intel Corporation]
Paper
Presentation
User Paper 2: PrimeTime Advanced OCV - Another Way to Performance Confidence
(3rd Place - Best Paper)
Author(s):
Prashanth Sagar [GLOBALFOUNDRIES]
Paper
Presentation
User Paper 3: Hitting Bull's Eye Using HSIM in Nanometer Design
Author(s):
Lew Jer-Jiunn [Altera Corporation]
Paper
Presentation
User Paper 4: DFT for a Low Pin Count SoC
Author(s):
Shibu Menon [ST-Ericsson]
Paper
Presentation
User Paper 5: Clocking Methodology for Performance Verification in SoC Design
(2nd Place - Best Paper)
Author(s):
Tan Hon-Ee [Intel Corporation]
Paper
Presentation
User Paper 6: Using StarRC for Accurate Post-Layout SPICE Netlist Extraction
Author(s):
Yong Ai-Ling [Altera Corporation]
Paper
Presentation
User Paper 7: Custom ICC Flow For High Speed Long Channel Repeaters Insertion In SOC Design
Author(s):
Tneh Cheng Hui [Intel Corporation]
Paper
Presentation
User Paper 8: Making DFM Sense In Your Design
(1st Place - Best Paper)
Author(s):
Sky Yeo Wee Kwong [GLOBALFOUNDRIES]
Paper
Presentation
Publication Only
Automating Verification for Mask Identification Data with Hercules
Author(s):
Boon Hoe Teh, Brad Jensen [Altera Corporation]
Paper
Fast, Automated Timing Model Characterization for FPGA using NanoTime
Author(s):
Cherry Pua Siaw Fuang, Ng Boon Choon, Lim Yun Mei [Altera Corporation]
Paper
Optimal Decoupling Cap Placement Analysis
Author(s):
Ang Boon Chong [Altera Corporation]
Paper
Proximity Handling for Design Block Using StarRC Parasitic Extraction
Author(s):
Yong Ai-Ling, Lim Teck-Yunn, Sudheesh Madhavan [Altera Corporation]
Paper
Synthesis Timing Convergence Recipe for New Generation High Speed Design
Author(s):
Pik Lay Teo, Thomas Tan [Intel Corporation]
Paper
Test Cost Optimization with the Introduction of Effective Pattern Merging System
Author(s):
Kuit Chiew Khiang, Lim Ching Sia [Altera Corporation]
Paper
Tutorials
Tutorial : Feasibility for IC Implementation
Author(s):
Yeong Kig-Ling [Synopsys]
Tutorial
Tutorial: Design Compiler 2010.03 Update
Author(s):
Eric Lim [Synopsys]
Tutorial
Tutorial: PrimeTime | How to Improve runtime
Author(s):
Jagan Thinakaran [Synopsys]
Tutorial
Tutorial: LYNX
Author(s):
Teng Zhao-Wei [Synopsys]
Tutorial
Panel Presentation
Panel Discussion: Low-Power Design - Challenges and Solutions
Author(s):
Lam Lup-Meng [Synopsys]
SNUG Silicon Valley Keynote
Massive Innovation and Collaboration into the "GigaScale" Age!
- Synopsys
SNUG Silicon Valley Keynote
From Crystal Ball to Reality: The Impact of Silicon IP on SoC Design
- Imagination Technologies
Snug Proceedings
Proceedings
Germany, 2013
India, 2013
Silicon Valley, 2013
UK, 2013
Austin, 2012
Boston, 2012
Canada, 2012
France, 2012
Germany, 2012
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