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| Tutorials |
| A1 User Papers and Tutorial: xProp, Native Low Power, Soft Constraints |
Introduction to Soft Constraints in SystemVerilog
Author(s): Alex Shot, Jason Chen [Synopsys, Inc.] |
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| A2 Tutorial: Considerations in Using FPGAs as System Elements |
Considerations in Using FPGAs as System Elements
Author(s): Andrew Dauman [Synopsys, Inc.] |
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| A3 Tutorial and User Paper: Design Compiler 2012.06 Updates and Multibit FF Inferring |
Galaxy RTL: Design Compiler Family Update
Author(s): Eyal Odiz, Gal Hasson [Synopsys, Inc.] |
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| A4 Tutorial & Vision: ICC 2012.06 Updates and 2.5D IC Vision |
ICC 2012.06 Updates
Author(s): Ashwini Mulgaonkar [Synopsys, Inc.] |
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| A5 FastSPICE: Overview and User Experience |
FastSPICE Solutions Overview
Author(s): Dr. Isaac Zafrany [Synopsys, Inc.] |
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| A6 Tutorial: Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair |
Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair
Author(s): Zaka Bhatti [Synopsys, Inc.] |
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| B1 Tutorial: Leveraging Synopsys’ Next Generation SystemVerilog VIP |
Leveraging Synopsys’ Next Generation SystemVerilog VIP to Accelerate SoC Verification for the ARM AMBA 4 ACE Protocol
Author(s): Chris Thompson [Synopsys, Inc.] |
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| B2 Tutorial: FPGA Best Practices and Hybrid Prototyping |
FPGA-Based Prototyping with Certify & Identify
Author(s): Yair Dahan [Synopsys, Inc.] |
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Hybrid Prototyping - Connecting Virtual and FPGA Prototypes
Author(s): Ohad Amrami, Yair Dahan [Synopsys, Inc.] |
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| B3 Tutorial & Panel: Optimized Implementation for High-Performance Cores |
Ask the Experts Panel: Best Practices for High-Performance Processor Core Implementation
Author(s): |
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Techniques for High Performance Cores Using Synopsys Galaxy Platform - ARM® Cortex™-A15 Case Study
Author(s): Erik Olson [Synopsys, Inc.] |
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| B5 Tutorial: How to Get the Most from Your Circuit Simulation |
How to Get the Most from Your Circuit Simulation
Author(s): Dr. Isaac Zafrany [Synopsys, Inc.] |
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| B6 User Paper and Tutorial: Connectivity IPs |
Tutorial: Designing to the New PCI Express 3.0 Equalization Requirements
Author(s): Rita Horner [Synopsys, Inc.] |
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| C2 Tutorial: Software Development for ARM big.LITTLE and Processor Design |
Application-Specific Processor Design
Author(s): Achim Nohl [Synopsys, Inc.] |
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Tutorial: Developing Software for ARM big.LITTLE Based Designs Running Android
Author(s): Robert Kaye [ARM] ; Achim Nohl [Synopsys, Inc.] |
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| C3 Tutorial: IC Compiler Custom Co-Design |
C3 Tutorial: IC Compiler Custom Co-Design
Author(s): Dr. Isaac Zafrany, Mattan Tsachi [Synopsys, Inc.] |
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| C4 User & Tutorial Session: Design Planning; Top level closure (TIO); Flip-Chip |
Faster Top-Level Closure with Transparent Interface Optimization (TIO)
Author(s): Sharon Avital [ Synopsys, Inc.] |
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Flip-chip Package Support Solution Based on ICC 2012.06 Release
Author(s): Moshe Ashkenazi [Synopsys, Inc.] |
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Hippo Lake: A Case Study of Automated Design Planning in High-Speed Designs
Author(s): Oleg Milter, Justin Barber, Victoria Kolesov, Atul Walimbe, Michael McCoy [Intel] |
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| C5 Tutorials: IT for EDA |
Leveraging Adaptive Resource Optimization with Lynx
Author(s): Glenn Newell [Synopsys, Inc.] |
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Management of High-Performance Compute Resources - Understanding the Impact of NFS Overhead
Author(s): Glenn Newell [Synopsys, Inc.] |
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| C6 Tutorials: Enhancing DesignWare ARC Processor Performance; Complete Audio IP Subsystem for Your SoC |
Tutorial: Create a Complete Audio IP Subsystem for Your SoC
Author(s): Shlomi Dan [Synopsys, Inc.] |
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Tutorial: Enhancing DesignWare ARC Processor Performance using Custom Extension Instructions
Author(s): Steve Tateosian [Synopsys, Inc.] |