SNUG Israel 2012 Proceedings

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Complete Proceedings


User Papers and Presentations
A1 User Papers and Tutorial: xProp, Native Low Power, Soft Constraints
Improved X-Propagation using the xProp Technology
Author(s):
PaperPresentation

Power Aware Verification for CPU Designs: Challenges and Solutions
Author(s):
PaperPresentation

A3 Tutorial and User Paper: Design Compiler 2012.06 Updates and Multibit FF Inferring
Inferring Multi (dual) bit FFs in Synopsys RTL2GDSII flow
Author(s): Oren Unger, Raz Dagan, Omer Niv [CSR - Zoran Microelectronics]
PaperPresentation

A5 FastSPICE: Overview and User Experience
Methods for Running FastSPICE (XA) for SPICE-level Accuracy on Advanced Analog Circuits
Author(s):
PaperPresentation

Utilizing SystemVerilog for Mixed-Signal Validation
Author(s):
PaperPresentation

B4 User Papers: Load Density Driven Power Grid; Verification of Layout integration flow; OCC Controller
Load Density Driven Power Grid Design
Author(s): Farah Jubran [Mellanox Technologies]
PaperPresentation

On-Chip-Clock controller (OCC): An Alternative Approach
Author(s): Jalal Abu Teir, Joram Peer [ Nuvoton]
PaperPresentation

Verification of Layout Integration Flow
Author(s):
PaperPresentation

B6 User Paper and Tutorial: Connectivity IPs
Third Party Connectivity IP - Expectations and Experience
Author(s): Roman Mostinski [Freescale]

C1 User Papers: Verification Abstraction, Reusable Testbench, Design Patterns
Design Patterns in Verification
Author(s): Guy Levenbroun [Qualcomm]
PaperPresentation

The End of Verification?
Author(s): Kobi Pines [Marvell]
Presentation

Truly Reusable Testbench-to-RTL Connection for SystemVerilog
Author(s): Arik Shmayovitsh [Sigma Design]
PaperPresentation

Tutorials
A1 User Papers and Tutorial: xProp, Native Low Power, Soft Constraints
Introduction to Soft Constraints in SystemVerilog
Author(s): Alex Shot, Jason Chen [Synopsys, Inc.]
Tutorial

A2 Tutorial: Considerations in Using FPGAs as System Elements
Considerations in Using FPGAs as System Elements
Author(s): Andrew Dauman [Synopsys, Inc.]
Tutorial

A3 Tutorial and User Paper: Design Compiler 2012.06 Updates and Multibit FF Inferring
Galaxy RTL: Design Compiler Family Update
Author(s): Eyal Odiz, Gal Hasson [Synopsys, Inc.]
Tutorial

A4 Tutorial & Vision: ICC 2012.06 Updates and 2.5D IC Vision
ICC 2012.06 Updates
Author(s): Ashwini Mulgaonkar [Synopsys, Inc.]
Tutorial

A5 FastSPICE: Overview and User Experience
FastSPICE Solutions Overview
Author(s): Dr. Isaac Zafrany [Synopsys, Inc.]
Tutorial

A6 Tutorial: Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair
Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair
Author(s): Zaka Bhatti [Synopsys, Inc.]
Tutorial

B1 Tutorial: Leveraging Synopsys’ Next Generation SystemVerilog VIP
Leveraging Synopsys’ Next Generation SystemVerilog VIP to Accelerate SoC Verification for the ARM AMBA 4 ACE Protocol
Author(s): Chris Thompson [Synopsys, Inc.]
Tutorial

B2 Tutorial: FPGA Best Practices and Hybrid Prototyping
FPGA-Based Prototyping with Certify & Identify
Author(s): Yair Dahan [Synopsys, Inc.]
Tutorial

Hybrid Prototyping - Connecting Virtual and FPGA Prototypes
Author(s): Ohad Amrami, Yair Dahan [Synopsys, Inc.]
Tutorial

B3 Tutorial & Panel: Optimized Implementation for High-Performance Cores
Ask the Experts Panel: Best Practices for High-Performance Processor Core Implementation
Author(s):

Techniques for High Performance Cores Using Synopsys Galaxy Platform - ARM® Cortex™-A15 Case Study
Author(s): Erik Olson [Synopsys, Inc.]

B5 Tutorial: How to Get the Most from Your Circuit Simulation
How to Get the Most from Your Circuit Simulation
Author(s): Dr. Isaac Zafrany [Synopsys, Inc.]
Tutorial

B6 User Paper and Tutorial: Connectivity IPs
Tutorial: Designing to the New PCI Express 3.0 Equalization Requirements
Author(s): Rita Horner [Synopsys, Inc.]
Tutorial

C2 Tutorial: Software Development for ARM big.LITTLE and Processor Design
Application-Specific Processor Design
Author(s): Achim Nohl [Synopsys, Inc.]

Tutorial: Developing Software for ARM big.LITTLE Based Designs Running Android
Author(s): Robert Kaye [ARM] ; Achim Nohl [Synopsys, Inc.]
Tutorial

C3 Tutorial: IC Compiler Custom Co-Design
C3 Tutorial: IC Compiler Custom Co-Design
Author(s): Dr. Isaac Zafrany, Mattan Tsachi [Synopsys, Inc.]
Tutorial

C4 User & Tutorial Session: Design Planning; Top level closure (TIO); Flip-Chip
Faster Top-Level Closure with Transparent Interface Optimization (TIO)
Author(s): Sharon Avital [ Synopsys, Inc.]
Tutorial

Flip-chip Package Support Solution Based on ICC 2012.06 Release
Author(s): Moshe Ashkenazi [Synopsys, Inc.]
Tutorial

Hippo Lake: A Case Study of Automated Design Planning in High-Speed Designs
Author(s):
Presentation

C5 Tutorials: IT for EDA
Leveraging Adaptive Resource Optimization with Lynx
Author(s): Glenn Newell [Synopsys, Inc.]

Management of High-Performance Compute Resources - Understanding the Impact of NFS Overhead
Author(s): Glenn Newell [Synopsys, Inc.]

C6 Tutorials: Enhancing DesignWare ARC Processor Performance; Complete Audio IP Subsystem for Your SoC
Tutorial: Create a Complete Audio IP Subsystem for Your SoC
Author(s): Shlomi Dan [Synopsys, Inc.]
Tutorial

Tutorial: Enhancing DesignWare ARC Processor Performance using Custom Extension Instructions
Author(s): Steve Tateosian [Synopsys, Inc.]
Tutorial