SNUG Israel 2010 Proceedings
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Complete Proceedings
User Papers and Presentations
A2 - User Presentations: FPGA Design and prototyping experience
ASIC Prototyping on FPGA
Author(s): Robert Shilton [MulberryOne]
Presentation

Improving Timing Closure with Physical Synthesis Methodoloy
Author(s): David Wente [NDS Group Ltd.]
Presentation

Synplify - right from your first RTL line
Author(s): Ran Manor [MOD IDF]
Presentation
A4 - User Papers: Design Planning Experience
Automatic floor planner for huge blocks with lots of memories
Author(s): Yoav Kretchmer [Marvell]
PaperPresentation

Design planning flow
Author(s): Eyal Dancona, Sagi Zohar [CEVA]
PaperPresentation

Zoran RTL2GDSII Hierarchical Flows
Author(s): Eran Berman, Noga Dayag [Zoran Microelectronics]
Presentation
A6 - Vision & User Paper
Co-simulation using analog PLL with digital controller
Author(s): Lior Gil [Intel]
PaperPresentation
B1 - User Papers: Verification Experience 1
A Methodology for Timely Verification of a Complex SoC
Author(s): Peretz Landau, Guy Regev [Percello Ltd.]
PaperPresentation

Random Verification Environment Using Emulation Platform
Author(s): Alexander Khazin, Gabriel Drukman [Qualcomm]
PaperPresentation

Simulation Acceleration using Multicore Systems (Technical Committee Award)
Author(s): Yechiel Hefetz, Avi Green, Itai Yarom [Intel], Eran Mudayi [Jerusalem College of Technology]
PaperPresentation
B3 - User Paper & Tutorial
Iterative development - an approach for hitting power and frequency targets with the first silicon
Author(s): Amnon Rom [LSI Corp.]
PaperPresentation
B4 - User Papers: Design Implementation Experience
Clock Tree implementation techniques - a comparative analysis (Best Paper Award)
Author(s): Ina Shtarkberg [Intel Corp.]
PaperPresentation Webinar

Implementation tools correlation to signoff on designs above 1 M cells
Author(s): Hatem Yazbek [Marvell]
PaperPresentation

Speeding PrimeTime's reports analysis (Technical Committee Award)
Author(s): Yossi Rindner, Ohad Meshulam [ASICServe]
PaperPresentation
B5 - Tutorial & User Experience: DC2010.03 Update
Accelerated Design Convergence with Synthesis Physical Guidance to Place & Route
Author(s): Alon Goldstein [Intel Corp.]
C1 - User Papers: Verification Experience 2
Logic Modeling and Formal Equivalence Checking of Analog-based Design
Author(s): Moshe Emmer [Intel]
PaperPresentation

rvm_sc - OpenVera / RVM and systemC integration
Author(s): Guy Levenbroun, Guy Ben-Artzi [Qualcomm Inc.]
PaperPresentation

Using Coverage Convergence Technology (CCT) to reduce coverage convergence from 30 to 2 days
Author(s): Ron Ahronson [Tessera]
PaperPresentation
Tutorials
A1 - Vision & Tutorial
SystemVerilog is Getting Even Better! - An Update on SystemVerilog-2009
Author(s): Shalom Bresticker [Intel]
Tutorial
A3 - Tutorials: Signoff
Faster Timing Convergence with PrimeTime ECO
Author(s): Zohar Zoulty [Synopsys Inc.]
Tutorial

Galaxy Constraints Analyzer: Constraints Debugging Made Easy
Author(s): Erez Bar-Nir [Synopsys Inc.]
Tutorial

In-design physical verification
Author(s): Moti Zeltser [Synopsys Inc.]
Tutorial

In-design Rail Analysis
Author(s): Toovit Begun [Synopsys Inc.]
Tutorial
A7 - HDMI Tutorial and MIPI Demo
MIPI CSI-2 Host Demo
Author(s): Miguel Falcao Sousa [Synopsys Ltd.]
Tutorial

Understanding HDMI 1.4 and How to Integrate the New HEAC Feature into SoCs
Author(s): Manmeet Walia [Synopsys Inc.]
Tutorial
B2 - Tutorials: Rapid prototyping and FPGA design
HAPS - Reaching beyond traditional HW prototyping
Author(s): GunnarScholl [Synopsys Inc.]
Tutorial

Tips and Tricks for FPGA Synthesis QoR, Debug, and Faster Turnaround Time
Author(s): Yair Dahan [Synopsys Inc.]
Tutorial
B3 - User Paper & Tutorial
Increased Productivity and Higher Predictability with the Lynx Design System
Author(s): Leon Rabinovich [Synopsys Inc.]
Tutorial
B5 - Tutorial & User Experience: DC2010.03 Update
Galaxy RTL: Design Compiler Family 2010.03 Update
Author(s): Gal Hason, Ziv Leshem [Synopsys Inc.]
Tutorial
B6 - Tutorial & User Experience
Custom Designer Update
Author(s): Rudolf Walter, Dr. Isaac Zafrany [Synopsys Inc.]
Tutorial

TowerJazz iPDK design experience in Custom Designer environment
Author(s): Ofer Tamir [Tower Semiconductor]
Tutorial
B7 - Tutorial
Extreme Low-Power Datapath Design with DesignWare minPower Components
Author(s): Meni Jayaswal [Synopsys Inc.]
Tutorial
C2 - Tutorials
Combining Virtual and FPGASoftware Centric Power Optimizations Interconnect and Memory Performance Optimization
Author(s): Ohad Amrami [Synopsys Inc.]
Tutorial Use Model

Optimizing system performance for AMBA NIC-301 Network Interconnect* based designs
Author(s): Ohad Amrami, Yair Dahan, Jacob David [Synopsys Inc.]
Tutorial

Software centric, system level power optimization using Virtual Platforms
Author(s): Ohad Amrami [Synopsys Inc.]
Tutorial
C4 - Tutorials
IC Compiler 2010.03 Updates
Author(s): Sharon Avital, Mattan Tsachi, Moshe Ashkenazi [Synopsys Inc.]
Tutorial
C5 - Tutorial
From EDA Infrastructure to Cloud Computing
Author(s): Hasmukh Ranjan, John Mincarelli [Synopsys Inc.]
C7 - Tutorial
In-system Calibration for High Speed DDR Interfaces
Author(s): Stephen Bond [Synopsys Inc.]
Tutorial
Panel Presentation
C3 - Panel
Yield & DFM - it is never too early to plan for it!!
Author(s): Zachi Feldman [Broadcom], Farah Jubran [Mellanox], Leor Nevo [Intel], Doug Pattullo [TSMC], Marco Casale-Rossi [Synopsys], Moderator: Nir Sever [Tehuti Networks]
Workshop
C6 - Workshop
CustomDesigner Workshop and Contest!
Author(s):


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