SNUG Israel 2009 Proceedings
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Complete Proceedings
User Papers and Presentations
A2 - Hardware Assisted Verification & Prototyping
ASIC Prototyping with the CONFIRMA Solution
Author(s): Pavel Zilberstain [Qualcomm Incorporated]
PaperPresentation

Implementation of a Wireless Baseband System on a ChipIT Platform
Author(s): Noam Benayahu [Metalink]
Presentation
A3 - Methodology
Application of Accurate Physical Constraints Allocation in DCT and its Effect on the QoR
Author(s): Dan Saad, Yaar Keren, Alon Glick [TI]
PaperPresentation

Fast Flow for Power Prediction @ RTL Level in Deep Sub-micron Processes
Author(s): Hatem Yazbek, Yoav Kretchmer [Marvell]
PaperPresentation
A4 - Low Power Design Experience
Dynamic Power Reduction in High Frequency Designs Without the Use of Clock Gating
Author(s): Sagi Weiss, Michel Feldman [Intel]
PaperPresentation

Generic UPF Macro-Level Flow
Author(s): Yoav Kretchmer [Marvell]
PaperPresentation

Robust Power Gating Implementation Using ICC (1st Place - Best Paper)
Author(s): Ariel Wolf [Intel]
PaperPresentation
A6 - AMS
HSPICE Adoption and Integration Within Intel-LAD Analog Design Flow
Author(s): Yahav Bar-Yosef [Intel]
PaperPresentation

XA Based Flow for Image Sensor Innovative Chip Design
Author(s): Vadim Tkachev, Vladimir Polyak [Advasense]
Presentation
B1 - Functional Verification Techniques
From Dirt Road to Highway or How Can ExMan Contribute to Your Verification Productivity
Author(s): Doron Stein [Cisco]
PaperPresentation

Generic VMM/XVC Based Verification Environment Methodology
Author(s): Ron Ahronson, Nadav Gigi [DesignArt]
PaperPresentation

System Verilog Based Bottom-up Reuse Methodology for Complex Design-Verification Environments
Author(s): Alex Shot [TI]
PaperPresentation
B2 - FPGA Design and Verification Experience
Achieving 38.4Gbs Throughput on HyperTransport™ Bus Using Standard FPGA Solution
Author(s): Ziv Serlin [Commex]
PaperPresentation

Advanced Simulation Based Verification for FPGA Designs
Author(s): Akiva Michelson [ACE Verification]
PaperPresentation

ASIC Prototyping Platform Debugging Using Synplicity Identify
Author(s): Amos Freund [PMC-Sierra]
PaperPresentation
C1 - Functional Verification Experience and... Gotchas!
A Pseudo-Random “BIOS Simulator” for PCIe Based Systems
Author(s): Eduard Shusterman [LucidLogix]; Yossi Levhari [VeriSure]
PaperPresentation

Just When You Thought It Was Safe to Start Coding Again ... Return of the SystemVerilog Gotchas
Author(s): Shalom Bresticker [Intel]
PaperPresentation

Standard Gotchas Subtleties in an OpenVera Environment
Author(s): Guy Levenbroun, Asaf Markanti, Yossi Ginzburg [Qualcomm Incorporated]
PaperPresentation
C4 - Design Experience
Constraints Management Toolset (CMT) for Synopsys Flow (Technical Committee Award)
Author(s): Eyal Chen [AST]
PaperPresentation

Design Methodology for Soft Error Mitigation
Author(s): Tuvia Liran [Ramon Chips Ltd.]
PaperPresentation

SV Coding Style for Better Synthesis QoR
Author(s): Oren Kol, Roy Peretz [Intel]
PaperPresentation
Tutorials
A1
Advanced Verification: VMM Low Power, VMM Applications and Parallel Simulation
Author(s):
Tutorial
A4
B-2008.09 Power Compiler Clock Gating Updates
Author(s):
Tutorial
A5
Signoff Quality DRC & Fill using Hercules within IC Compiler
Author(s):
Tutorial

What Designers Need to Know about Full-Chip DFM
Author(s):
Tutorial
A6
What’s New in Analog/Transistor Simulation using HSPICE and XA
Author(s):
Tutorial
B3
Improving RTL-to-GDSII Design Efficiency
Author(s):
Tutorial
B4
ICC 2008.09 – Highlights
Author(s):
Tutorial
B5
Galaxy Test - Power-Aware DFT/ATPG and Technical Updates
Author(s):
Tutorial

Synopsys Test Overview
Author(s):
Tutorial
B6
Synopsys' Custom Design Solution
Author(s):
Tutorial
C2
Algorithm Implementation and Prototyping
Author(s):
Tutorial

FPGA: It’s all about Timing! Constraints, Analysis and Closure in Synplify Pro and Synplify Premier
Author(s):
Tutorial
C3
Multi-Voltage Implementation Methodology using UPF
Author(s):
Tutorial

PrimeRail Using UPF
Author(s):
Tutorial
C5
Advanced On-Chip Variation Tutorial
Author(s):
Tutorial

Faster Timing Closure in a Multi-Scenario World
Author(s):
Tutorial
C6
3rdGeneration Serial Interconnects and Advanced Technologies
Author(s):
Tutorial


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