SNUG Israel 2008 Proceedings
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User Papers and Presentations
A4 - Design Prediction with Design Compiler
Design Convergence Challenges on Deep Sub Micron High Speed Designs
Author(s): Alon Goldshtein [Intel]
Presentation

Reliable Frequency Prediction @ RTL Level in Deep Sub-Micron Processes (1st Place - Best Paper)
Author(s): Hatem Yazbek [Marvell]
PaperPresentation
A5 - Lysis Solution for Custom Design
Static Timing Analysis of High Performance Digital Designs Using NanoTime
Author(s): Enrique Brusilovsky [Marvell]
PaperPresentation
B1 - Functional Verification Techniques
Block Level or System Level- the Engineer-Manager Dilemma; A Case Study
Author(s): Yossi Ginzburg, Guy Levenbroun [Qualcomm]
PaperPresentation

Connect One DV Architecture using System Verilog
Author(s): Ilan Frisch, Tal Bakish [Connect One]
PaperPresentation

Power Aware Verification
Author(s): Claudiu Yanqo [Marvell]
PaperPresentation
B4 - Design Compiler Family
Enhancing Mudularity in SV with Parametrized Arrays
Author(s): Niloufar Dayanim [Amimon]
PaperPresentation

RTL Techniques for Global Skew Relaxation using Multiple Clock Domains
Author(s): Henri Meirov, Rafy Diaz [Texas Instruments]
PaperPresentation
B5 - Analog Mixed-Signal Simulation
Case Study - Using HSIMplus to Detect HiZ Problems in Design
Author(s): Alon Negev, Rom Bronfman [Saifun]
Presentation
B6 - Evaluation and Due Diligence Silicon Intellectual Property
Evaluation and Due Diligence Silicon Intellectual Property
Author(s): David Dahan [Prime Sense]
PaperPresentation
C3 - Physical Design Experience
A Safe Landing of 65nm Designs with the PrimeTime-SI Signoff Tool Suite
Author(s): Ezra Cohen-Yashar [Sondrel]
PaperPresentation

Leakage Power Optimization on a Post Layout Netlist
Author(s): Gilad Stossel [Ceva]
PaperPresentation

Route of Digital Signals in Analog Blocks with Jupiter & Astro
Author(s): Sagi Gabai [Zoran]
PaperPresentation
C4 - DFT
Full Scan System in High-Speed Design. Usage of ICC Capabilities for "Non-Standard" Scan Systems
Author(s): Oleg Milter [Intel]
PaperPresentation

Non Hierarchical Scan Partition & Inter Clock Domains Paths' Coverage
Author(s): Yaron Preisler [Texas Instruments]
PaperPresentation
C5 - ESL
How to Develop in a World of Platforms, Intel Experiences with ESL
Author(s): Itai Yarom [Intel]
PaperPresentation
Tutorials
A1
Advanced VMM – VMM Register Abstraction Layer
Author(s):
Tutorial
A2
Unified Power Format - UPF
Author(s):
Tutorial
A3
ICC 2007.12 Update
Author(s):
Tutorial
A5
NanoTime Increases Design Predictability for Nanometer Applications
Author(s):
Tutorial
A6
High Speed Design Challenges in DDR3/2
Author(s):
Tutorial
B2
Synopsys Power Management Verification
Author(s):
Tutorial
B3
IC Compiler Design Planning Reference Methodology (RM) and MinChip Die Reduction Flow
Author(s):
Tutorial
B4
Design Compiler Family 2007.12 update
Author(s):
Tutorial
B5
What’s New in Analog/Transistor Simulation Products
Author(s):
Tutorial
B6
USB Digital IP Verification
Author(s):
Tutorial

Verification of Hard IP Components
Author(s):
Tutorial
C1
VMM Planner Tutorial
Author(s):
Tutorial
C2
Eclypse Low Power Solution
Author(s):
Tutorial
C4
Achieving Ultra-High Test Quality: Small Delay Defect Testing
Author(s):
Tutorial
C5
Case Study: Accelerating Software Driver Development for the DesignWare® USB HS OTG Core Through Virtual Platforms
Author(s):
Tutorial
C6
Achieving Lower Power and Smaller Area with USB Link Power Management & High-Speed Inter-Chip
Author(s):
Tutorial
Panel Presentation
Panel Presentation
Removing Congestion with Design Compiler
Author(s):
Presentation


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