|
| User Papers and Presentations |
| TA1 Vision and User Session |
Improving TAT of DRC fixing by eliminating manual intervention using Auto DRC Repair flow
Author(s): Amar Chand Pallam [AMD], Ananda Veerasangaiah [Synopsys] |
|
Productivity Improvements and Faster DesignClosure Using DesignExplorer
Author(s): Girish T P, Shivaramakrishna Uddanti [AMD], George Jacob, Ramakrishna R [Synopsys] |
|
| TA2 User Session |
A Novel Implementation Approach for SoC Pin Timing Closure
Author(s): Deepak Tottempudi, Saj Kapoor, Rugmini K, Shrinivas MV [Analog Devices] |
|
Harnessing the flexibility of ICV for Methodology checking flow in advanced technology nodes
Author(s): Anand Kumaraswamy, Pardeep Saini, Dharmendra Varma, Harshit Agnihotri [IBM] |
|
Implementation of ARM Cortex-A9 Quad Core Processor with Synopsys Hierarchical Flow (Outstanding Technical Papers)
Author(s): Venu Gopal , Prem Kishor [Open-Silicon] |
|
Template based flow to resolve Congestion for High pin-Density cells using ICC
Author(s): Rajesh Arimilli , Murali Seshadri [Qualcomm] |
|
| TA3 User Session & Panel |
Garuda: Implementation of ARM CPU development chip
Author(s): Dipesh Bajaj [ARM] |
|
| TB1 User Session and Vision |
Forward looking Quick-PNR flow for early power estimation
Author(s): Anshuman Anand [Intel] |
|
Low Power design Implementation challenges & solutions with UPF
Author(s): Nitin Raverkar, Pradeep Sreenivasa [LSI] |
|
| TB2 User Session and Vision |
Challenges in designing LP SoCs using hierarchical UPF
Author(s): Vadivel Ramalingam, Syed S Thameem [Intel] |
|
Handling Power Challenges for Orphan IPs (Outstanding Technical Papers)
Author(s): Mahendra Singh [ST-Ericsson] |
|
Optimal Dynamic vs Leakage Power Trade-off using Statistical Intelligence
Author(s): Ravi Chhabra, Srijith R Nair [Intel] |
|
UPF-aware Formality Flow for Large Complex 40nm SoC
Author(s): Akhilesh Shukla, Avani Deshpande, Devendra Deshpande [LSI] |
|
| TC1 Vision & User Session |
A solution for quick verification of net-matching constraints
Author(s): Madan Lal, VeeraKumar Pitchiah [Intel] |
|
Single digital test bench for functional verification of multiple analog and digital blocks embedded deep inside mixed signal designs using XA-VCS cosim flow
Author(s): Sean Sequeira [AMD] |
|
| TC2 Tutorials & User Session |
CustomExplorer Waveform Comparison in a Fully Automated Silicon Device Models Validation Flow
Author(s): Vani Priya, Branimir Ivetic [STMicroelectronics] , Rakesh Shenoy [Synopsys] |
|
Fast spice simulator CustomSim XA for IO functional verification and reliability check
Author(s): Srinivasa Rao Kenguva, Srihari Mallavarapu, Sreenivasulu Ramavath [LSI], Sateesh Chandramohan [Synopsys] |
|
| TC3 User Session |
Advanced Regression & Verification of Mixed Signal Designs using CustomExplorer Ultra
Author(s): George Kuruvilla [AMD], Manu Velayudhan Pillai [Synopsys] |
|
Hybrid Full Chip SPICE Simulation Methodology for Complex Low-Power Mixed-Signal SoC (Outstanding Technical Papers)
Author(s): Kumar Abhishek, Sunny Gupta, Nari Reddy, Kushal Kamal [Freescale] |
|
Standard Cell Model Qualification Improvement using ESP-CV
Author(s): Rohit Bapna, Sarika Jain, Srihari Mallavarapu [LSI] , Rakesh Shenoy [Synopsys] |
|
| TD1 Tutorial & User Session |
Hardware/Software co-simulation using Virtualizer
Author(s): Sameer Kumar Gupta, Anil Kamboj, Anuj Kumar, Hemant Nigam [HCL Technologies] |
|
Recipe for flavored RTL & Packaging
Author(s): Deepmala Sachan, Bharathi V [Intel] |
|
| TD2 Tutorial & User Sessions |
Achieving First-pass Silicon Success using Synopsys Platform Tools
Author(s): Kiran S J, Manjunath Varadannanavar [AppsConnect Technologies] |
|
Generic MLM environment for SoC Performance Enhancements (Outstanding Technical Papers)
Author(s): Igal Mariasin, Jayaprakash Naradasi, Dayananda Yaraganalu [Sandisk] |
|
| WA1 Tutorials & User Session |
Improved X-propagation semantics: CPU server learning
Author(s): Peeyush Purohit, Ashish Alexander, Anees Sutarwala [Intel] |
|
Integration of Legacy Verilog BFMs and VMM VIP in UVM using Abstract Classes
Author(s): Santosh Sarma [Wipro] |
|
| WA2 User Session |
Gaps and Challenges with Reset Logic Verification (Outstanding Technical Papers)
Author(s): Deepak Jindal [Freescale Semiconductors], Mayank Digvijay Bindal [Synopsys] |
|
Integrating SystemC OSCI TLM 2.0 Models to OVM based SystemVerilog Verification Environments
Author(s): Subhra S Bandyopadhyay, Pavan N M [Intel] |
|
SOC Compilation and Runtime Optimization using VCS
Author(s): Santhosh K R, Sreenath Mandagani [Mindspeed], Gaurav Chugh , Ritesh Sharma [Synopsys] |
|
| WA3 User Session |
SoC Verification with Embedded Processor
Author(s): Vikash Dwivedi [Maxim Integrated Products] |
|
Verification methodology for dual NIC SoC using Verification IPs
Author(s): AV Anil Kumar, Mrinal Sarmah , Sunita Jain [Xilinx Technologies] |
|
| WB1 Tutorials & User Session |
An enhanced STA methodology considering simultaneous multiple input transition effect on complex gates (Outstanding Technical Papers)
Author(s): Satish Yada, Hanish Chowdary V, Mukesh Bhartiya [Intel] |
|
Early Power Estimation Using PrimeTime-PX
Author(s): Thenappan Meyyappan, Rajagopal K.A [Texas Instruments] |
|
| WB2 User Session |
Dynamic IR-Drop impact on High Speed Designs
Author(s): Arindam Dutta, Vishal Srivastava, Rajat Kukreja [ST Microelectronics] |
|
GCA methodology to improve the constraints quality and hence silicon failures
Author(s): Venkat Vemulapally, Ashish Mehta [Ikanos Communications], Natarajan Sridharan [Synopsys] |
|
Vector based Reliability Signoff for High Speed Serial IO Interfaces
Author(s): Sumeet Aggarwal [Intel] |
|
| WB3 Tutorial & User Session |
Faster Turnaround using PT-ECO
Author(s): Vikas Sharma, Atul Nauriyal, Dhiraj Jaiswal [ST Microelectronics] |
|
'Go Beyond' Standard Power Computation & IR drop Methodology for DDR PHY (IP): A way to ensure first pass Silicon
Author(s): Keshav Chintamani, Dhanapathy Krishnamoorthy [Texas Instruments] |
|
| WC1 User Session |
A Unique DFT Clocking Scheme to Reduce the Peak Power consumption during scan shift
Author(s): Jasvir Singh, Renuka Deshpande, Manoj Kumar Yadav [STMicroelectronics] |
|
Reducing Scan ATPG Overhead: Generation of Internal Scan Enable Control and its Qualification with ATPG Tool
Author(s): Rajesh Mittal, Puneet Sabbarwal, Rubin A. Parekhji, [Texas Instruments], Charles Kurian [Mirafra] |
|
TCAM BIST METHODOLOGY & TEST SCHEME
Author(s): Malthesh HG, Jay Shah [Open-Silicon], Hayk Chukhajyan, Gurgen Harutyunyan [Synopsys] |
|
Techniques to Improve Quality of Memory Interface Tests in SoCs Using Synopsys TetraMAX’s RAM Sequential ATPG (Outstanding Technical Papers)
Author(s): Sanjay Krishna H V, Srivaths Ravi [Texas Instruments] |
|
| WC2 User Session |
HAPS Based FPGA Prototype of Industrial Communication Subsystem for IP validation and Firmware Development (Outstanding Technical Papers)
Author(s): Kanad Kanhere [Texas Instruments] |
|
| WC3 User Session & Tutorials |
Pin reduction methodologies and novel approach for gated clock conversion while using multi FPGA platform
Author(s): Saransh Mehrotra, Charul Jain, Ambrish Pal [STMicroelectronics] |
|
Pre-silicon Verification and Validation using CHIPit
Author(s): D Naresh Kumar, Naveen Prasad [Mindspeed], Rajkumar Methuku [Synopsys] |
|
| Publication Only |
|
Behavioural Modeling of Split Capacitor SAR ADC for Predicting Non-Linearity accurately
Author(s): Srinivasan Gopal [Intersil Corporation] |
|
Integrate UVM Based Verification Components in Non- UVM Testbench
Author(s): Sidhesh Patel, Pratik Vasavda [LSI Corporation] |
|
Power - Being savvy at every step of implementation!!!
Author(s): Ishaan Biswas, Concept2Silicon Systems, Muniaswamy M [Cypress Semiconductor] |
|
A “Fool-Proof” Method to Negotiate Parasitic RC Delay in Memory Validation
Author(s): Harsh Rawat, Atul Bhargava, Sachin Gulyani, Rakesh Shenoy [STMicroelectronics] |
|
A Novel Approach Targeting Zero Timing ECO Cycle and Timing Sign Off within PnR Tool
Author(s): Nagarajan Venkatachalam, Parimal Das, Bamane Rupesh [Qualcomm India] |
|
Addressing DFT Challenges in a Low Power Design
Author(s): Poovaiah Palangappa, Praveen Sanjeev, Shrinivas M V [Analog Devices] |
|
Efficient, Reusable Methodology for developing automated Analog Mixed Signal Verification Environment
Author(s): Sunny Gupta, Kushal Kamal [Freescale] |
|
Hierarchical Static Timing Analysis (HSTA) on Complex Memory Physical Layer Designs
Author(s): Gundlapalli Shanmukha Srinivas, Norman Chan, Mahabaleshwara, Jammalamadugu Srinivasa Rao [Rambus Chip Technologies India (Pvt) Ltd.] |
|
Hierarchical UPF flow:A case study
Author(s): Dhruthi Uday, Debashish Sarkar [Cypress Semiconductor] |
|
Simple yet effective techniques for better FPGA prototyping
Author(s): Umesh Kumar Bhaskar, Arun Jain, Rahul Jain [Nvidia Graphics Pvt. Ltd.] |
|
System Level validation of DWC 10/100 Ethernet IP core
Author(s): Prasanth Rajagopal [Analog Devices Inc.] |
|
UPF-based Implementation of a 40nm Large SoC with Dis-joint Voltage Areas
Author(s): Anurag Mishra, Devendra Deshpande, Pritesh Pawaskar [LSI (India) R&D Pvt. Ltd] |
|
UVM: an experience of methodology from VIP development to Coverage Closure
Author(s): Rohit Srivastava, Gaurav Gupta, Nandini Mudgil, Sarvesh Patankar [Freescale Semiconductor] |