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| User Papers and Presentations |
| TA1 Whitepaper & User Papers |
Power Intent Specification Creation and Verification for Multi-Rail Cells using LEDA/MVSIM
Author(s): Anil Deshpande, Ramanan Balakrishnan [AMD], Vishwanath Sundararaman, Vikram Malik [Synopsys] |
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VMM based Multi-Layer Framework for System Level Verification
Author(s): Ashok Chandran, Sajeev Thomas, Saj Kapoor [Analog Devices] |
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| TA2 Tutorial & User Papers |
Pragmatic Approach for Reuse with VMM1.2 and RAL
Author(s): Sachin Sohale, Karthik Majeti, Pratish Kumar KT [Texas Instruments], Tushar Mattu [Synopsys] |
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Verification of Network Congestion Avoidance Algorithm Like WRED using VMM
Author(s): Puja Sethia [eInfochips] |
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| TA3 User Papers |
Low Power VMM for Telecom Designs
Author(s): Paul Kaunds, Asha Rai, Bhavani Shankar Kaggala, Sowmya Sullia [Kacper Technologies] |
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UPF specification and integration for a multiple sub-system low-power SoC
Author(s): Girish Kumar S N [NVIDIA], Krishna Theja Avvaru [Synopsys] |
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| TB1 Tutorial & User Papers |
Physical Implementation Challenges for a Very Large, Channel-Dominated, Multi-Clock Design in 45nm (1st Place - Best Paper; IC Design: Physical Design)
Author(s): Namit Varma, Madhusudan Rajagopal, Veena Radhakrishnan [Achronix] |
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Pre-Route Optimization Techniques Developed for High Performance Designs
Author(s): Nishant Gaidhani, Girish T Prabhakara [AMD] |
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| TB2 Tutorial & User Papers |
A Novel Methodology for High Performance Large Signal Memory Design
Author(s): Sumit Goswami, Sourashtra D Singh, Sanjeev K R [Intel] |
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Clock Power Reduction for Future Complex SOC using ICC
Author(s): Harmit Singh, Sourav Banerjee, Madhu Rao [Texas Instruments], Gaurav Ganeriwal [Synopsys] |
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Designing a GHz+ Cortex-A9 MPCore Dual Core Processor with Avanced Leakage Mitigation
Author(s): Sudhakar Maddi, Prasanth Gopinath, Roma Kundu [ARM], Anand Babu GS, Ananda Veerasangaiah [Synopsys] |
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| TB3 User Papers |
Automatic Cloning of Register and Combinational Logic
Author(s): Chakradhar Tallury, Vijay Kumar Budumuru [AMD] |
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Building IR Aware Power-Network for Complex Multi-Voltage Designs using ICC-PNS
Author(s): Prakash Janakiraman, Vipin Kumar Mishra [Intel] |
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| TC1 Tutorial & User Papers |
Efficient Prototyping of Multi-Million Gate SoCs using Accelerated Synthesis Feature of Synplify Premier (1st Place - Best Paper; FPGA and System Design)
Author(s): Sabyasachi Dey, Amit Siroya [Qualcomm] |
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Implementing high speed Serial interfaces in FPGA using HAPS Platform
Author(s): Umesh Huilgol, Vijay Chachra [LSI] |
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| TC2 User Papers & Tutorial |
FPGA Prototyping of a Multi-Media IP with Built-in Debug Capability using Synopsys-FPGA Tool and HAPS Platform
Author(s): Naveen T, Jagonda P, Subramanian P [Samsung] |
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System Performance Analysis - Modeling Approach
Author(s): Bhaarathe M, Amit S Kulkarni, Sonith T K [KPIT Cummins] |
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| TD1 Tutorial & User Papers |
Power and throughput optimization of pipelined custom processor designs using resource usage predictability with variable clock frequency
Author(s): Senthilkannan Chandrasekaran , Anuj Pratap Singh, Jasbir Singh Nayyar, Vivek Singhal [Texas Instruments] |
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Shrinking SoC Design Cycles using Designware Intellectual Property
Author(s): Rohitaswa Bhattacharya, Gaurav Bhatnaga, Vijay Mathur [STMicroelectronics] |
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| WA1 Vision & User Papers |
Identification of Non Resettable Flops for Faster Gate-Level Simulation
Author(s): Shankarnarayan Bhat, Shrivatsa Prahallada, Sriram Satakopan, Sanjay Muchini [Qualcomm] |
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Managing Gate Simulations for Large Designs using VCS-MX
Author(s): Lovleen Bhatia, Ish Kumar Dham, Rahul Maitra, Rama Kowsalya [Texas Instruments] |
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| WA2 User Papers |
Automating Functional Coverage Convergence and Avoiding Coverage Triage with ECHO Technology
Author(s): Pratish Kumar KT, Sachin Sohale, Ashish Chandra [Texas Instruments], Gaurav Gupta [Synopsys] |
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Challenges in SOC Integration -Verification and Reusable Methodology - to Overcome the Challenges
Author(s): Arif Mohammed, Paresh Joshi [Texas Instruments], Gaurav Gupta [Synopsys] |
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Efficient Use of SV Constraints for Optimum Simulation Performance
Author(s): Ujjal Bose, Deepa Ananthanarayanan [AMD] |
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Verification of Mixed-Signal Designs using System-Verilog Assertions in Co-simulation (1st Place - Best Paper; IC Verification)
Author(s): Somasunder Kattepura Sreenath, Sandeep Tare [Texas Instruments] |
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| WB1 User Papers & Tutorial |
Interconnect Variation Analysis
Author(s): Ajoy Mandal, Arvind N V, R Venkatraman, Kamal Kumar [Texas Instruments] |
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Timing Analysis on a Large High Performance 40nm Video SoC
Author(s): Pranav Murthy, Sanju Nair, Rajagopal K A [Texas Instruments] |
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| WB2 Tutorial & User Papers |
Accurate Early Power Roll-Up Methodology for High Speed IPs
Author(s): Arijit Mukhopadhyay [Intel] |
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Constraints Validation Using GCA
Author(s): Nupur Gupta, Pankaj Jain [STMicroelectronics] |
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On Analysis & Development of Sign-Off Quality Clock Gating Effectiveness Metrics (1st Place - Best Paper; IC Design: Signoff)
Author(s): Jairam Sukumar, Udayakumar H, Rajagopal K A [Texas Instruments], Maria Tovey [Synopsys] |
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| WB3 User Papers |
An Effective Approach for Better STA Sign-off with AOCVM Flow
Author(s): Swanand Palanki, Divya Srinath, Abhishek K, Jyothi Shankar Sen [Wipro Technologies] |
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Novel Approach to Reduce Runtime for Crosstalk Timing Closure
Author(s): Rangarajan Srinivasan [NVIDIA], Vivekanandan Muthuswami [Synopsys] |
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Three Step Methodology for Faster and Reliable Timing Signoff of Multimillion Gate Designs
Author(s): Mohit Verma, Azad Singh [STMicroelectronics], Vikas Choudhary [Synopsys] |
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| WC1 Vision & User Papers |
A Step Closer to First Pass Silicon Success Through *ANALOG* Checkers, Assertions and Functional Coverage using XMRs
Author(s): Joyodhree Biswas, Sean Sequeira [AMD] |
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Improving the Runtime of Memory Library Characterization Without Affecting the Accuracy using New Algorithms in HSIM.
Author(s): Shwetha Kamat, Asha [Qualcomm] |
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| WC2 Tutorial & User Papers |
Electromigration Analysis for ESD Circuits using HSIM-Plus
Author(s): Ranabir Dey, Kishan Chanumol, Manjunatha Prabh [ARM], Sateesh Chandramohan [Synopsys] |
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Finding Power-up Issues in Memories using ESP-CV (1st Place - Best Paper; Custom Design and AMS Verification)
Author(s): Premkumar, Sanjeev Suman [Texas Instruments], Rakesh Shenoy [Synopsys] |
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Memory Bitmap Verification using HERCULES and ESPCV.
Author(s): Viney Gautam [ARM] |
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| WC3 User Papers |
Experiences with XA for 32nm Memory Characterization for Fast Turn-Around.
Author(s): Nitin Gupta [STMicroelectronics], Rakesh Shenoy [Synopsys] |
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Interoperable PDKs - From Fad to Factor
Author(s): Baby Praveen Kollery, Jiju Paul [Wipro Technologies] |
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Using ESP-CV Symbolic Simulation for Standard Cell Functional Verification
Author(s): Sree Rama Chandra Gupta [Qualcomm], Rakesh Shenoy [Synopsys] |
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| WD1 Tutorial & User Paper |
Achieving Optimum Area & Power using MCMM
Author(s): Rajmohan Reddy Mandapati, Girish TP [AMD], Ramakrishna R [Synopsys] |
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Power and Performance Optimization for an Ultra High Performance Mobile Processor using Multiple VT Libraries
Author(s): Sourav Banerjee, Sreeram Chandrasekar, Yogesh Agarwal [Texas Instruments] |
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| WD2 User Papers & Tutorials |
Formality - An Integral Part of ASIC Design Flow
Author(s): Dayananda Yaraganalu Sadashivappa, Raghavendra G Palankar [Samsung] |
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| WD3 User Papers (Includes 1 Publication Only Paper) |
200X Combinational Scan Compression Architecture - Challenges and Results
Author(s): Rajesh Gottumukkala, Sarveswara Tammali, Aishwarya Singh [Texas Instruments], Mohanasundaram Selvam [Wipro Technologies] |
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Achieving massive multi-site testing without compromising on the test quality - Is Serializer the solution? (1st Place - Best Paper; IC Design: Synthesis and Test)
Author(s): Malav Shah, Claus kuntzsch, Nikolaus Mittermaier [Texas Instruments] |
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Compressed Pattern Debug and Diagnosis Flow Using X-tolerant DFTCMax Architecture
Author(s): Arvind Jain, Kanupriya Raturi, Sundarrajan Subramanian, Rubin Parekhji [Texas Instruments] |
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Publication Only: Multi-Power Design - DFT Challenges and Recommendations
Author(s): K. Rajesh, Kamal Jasti, Yogesh Thombre, [LSI], Daryl Pereira [Synopsys, Inc.] |